developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* |
| 3 | * |
| 4 | * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> |
| 5 | * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> |
| 6 | * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> |
| 7 | */ |
| 8 | |
| 9 | #ifndef MTK_ETH_H |
| 10 | #define MTK_ETH_H |
| 11 | |
| 12 | #include <linux/dma-mapping.h> |
| 13 | #include <linux/netdevice.h> |
| 14 | #include <linux/of_net.h> |
| 15 | #include <linux/u64_stats_sync.h> |
| 16 | #include <linux/refcount.h> |
| 17 | #include <linux/phylink.h> |
| 18 | |
| 19 | #define MTK_QDMA_PAGE_SIZE 2048 |
| 20 | #define MTK_MAX_RX_LENGTH 1536 |
developer | b3a9e7b | 2023-02-08 15:18:10 +0800 | [diff] [blame] | 21 | #define MTK_MIN_TX_LENGTH 60 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 22 | #define MTK_DMA_SIZE 2048 |
| 23 | #define MTK_NAPI_WEIGHT 256 |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 24 | |
| 25 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 26 | #define MTK_MAC_COUNT 3 |
| 27 | #else |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 28 | #define MTK_MAC_COUNT 2 |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 29 | #endif |
| 30 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 31 | #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) |
| 32 | #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) |
| 33 | #define MTK_DMA_DUMMY_DESC 0xffffffff |
| 34 | #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ |
| 35 | NETIF_MSG_PROBE | \ |
| 36 | NETIF_MSG_LINK | \ |
| 37 | NETIF_MSG_TIMER | \ |
| 38 | NETIF_MSG_IFDOWN | \ |
| 39 | NETIF_MSG_IFUP | \ |
| 40 | NETIF_MSG_RX_ERR | \ |
| 41 | NETIF_MSG_TX_ERR) |
| 42 | #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ |
| 43 | NETIF_F_RXCSUM | \ |
| 44 | NETIF_F_HW_VLAN_CTAG_TX | \ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 45 | NETIF_F_SG | NETIF_F_TSO | \ |
| 46 | NETIF_F_TSO6 | \ |
| 47 | NETIF_F_IPV6_CSUM) |
| 48 | #define MTK_SET_FEATURES (NETIF_F_LRO | \ |
| 49 | NETIF_F_HW_VLAN_CTAG_RX) |
| 50 | #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) |
| 51 | #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) |
| 52 | |
developer | 68ce74f | 2023-01-03 16:11:57 +0800 | [diff] [blame] | 53 | #define MTK_QRX_OFFSET 0x10 |
| 54 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 55 | #define MTK_HW_LRO_DMA_SIZE 8 |
| 56 | |
| 57 | #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) |
| 58 | #define MTK_MAX_LRO_IP_CNT 2 |
| 59 | #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ |
| 60 | #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ |
| 61 | #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ |
| 62 | #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ |
| 63 | #define MTK_HW_LRO_MAX_AGG_CNT 64 |
| 64 | #define MTK_HW_LRO_BW_THRE 3000 |
| 65 | #define MTK_HW_LRO_REPLACE_DELTA 1000 |
| 66 | #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 |
| 67 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 68 | /* Frame Engine Global Configuration */ |
| 69 | #define MTK_FE_GLO_CFG 0x00 |
| 70 | #define MTK_FE_LINK_DOWN_P3 BIT(11) |
| 71 | #define MTK_FE_LINK_DOWN_P4 BIT(12) |
| 72 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 73 | /* Frame Engine Global Reset Register */ |
| 74 | #define MTK_RST_GL 0x04 |
| 75 | #define RST_GL_PSE BIT(0) |
| 76 | |
| 77 | /* Frame Engine Interrupt Status Register */ |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 78 | #define MTK_FE_INT_STATUS 0x08 |
| 79 | #define MTK_FE_INT_STATUS2 0x28 |
| 80 | #define MTK_FE_INT_ENABLE 0x0C |
| 81 | #define MTK_FE_INT_FQ_EMPTY BIT(8) |
| 82 | #define MTK_FE_INT_TSO_FAIL BIT(12) |
| 83 | #define MTK_FE_INT_TSO_ILLEGAL BIT(13) |
| 84 | #define MTK_FE_INT_TSO_ALIGN BIT(14) |
| 85 | #define MTK_FE_INT_RFIFO_OV BIT(18) |
| 86 | #define MTK_FE_INT_RFIFO_UF BIT(19) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 87 | #define MTK_GDM1_AF BIT(28) |
| 88 | #define MTK_GDM2_AF BIT(29) |
| 89 | |
| 90 | /* PDMA HW LRO Alter Flow Timer Register */ |
| 91 | #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c |
| 92 | |
| 93 | /* Frame Engine Interrupt Grouping Register */ |
| 94 | #define MTK_FE_INT_GRP 0x20 |
| 95 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 96 | /* Frame Engine LRO auto-learn table info */ |
| 97 | #define MTK_FE_ALT_CF8 0x300 |
| 98 | #define MTK_FE_ALT_SGL_CFC 0x304 |
| 99 | #define MTK_FE_ALT_SEQ_CFC 0x308 |
| 100 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 101 | /* CDMP Ingress Control Register */ |
| 102 | #define MTK_CDMQ_IG_CTRL 0x1400 |
| 103 | #define MTK_CDMQ_STAG_EN BIT(0) |
| 104 | |
| 105 | /* CDMP Ingress Control Register */ |
| 106 | #define MTK_CDMP_IG_CTRL 0x400 |
| 107 | #define MTK_CDMP_STAG_EN BIT(0) |
| 108 | |
| 109 | /* CDMP Exgress Control Register */ |
| 110 | #define MTK_CDMP_EG_CTRL 0x404 |
| 111 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 112 | /* GDM Ingress Control Register */ |
| 113 | #define MTK_GDMA_FWD_CFG(x) ((x == MTK_GMAC3_ID) ? \ |
| 114 | 0x540 : 0x500 + (x * 0x1000)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 115 | #define MTK_GDMA_SPECIAL_TAG BIT(24) |
| 116 | #define MTK_GDMA_ICS_EN BIT(22) |
| 117 | #define MTK_GDMA_TCS_EN BIT(21) |
| 118 | #define MTK_GDMA_UCS_EN BIT(20) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 119 | #define MTK_GDMA_STRP_CRC BIT(16) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 120 | #define MTK_GDMA_TO_PDMA 0x0 |
| 121 | #define MTK_GDMA_DROP_ALL 0x7777 |
| 122 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 123 | /* GDM Egress Control Register */ |
| 124 | #define MTK_GDMA_EG_CTRL(x) ((x == MTK_GMAC3_ID) ? \ |
| 125 | 0x544 : 0x504 + (x * 0x1000)) |
| 126 | #define MTK_GDMA_XGDM_SEL BIT(31) |
| 127 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 128 | /* Unicast Filter MAC Address Register - Low */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 129 | #define MTK_GDMA_MAC_ADRL(x) ((x == MTK_GMAC3_ID) ? \ |
| 130 | 0x548 : 0x508 + (x * 0x1000)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 131 | |
| 132 | /* Unicast Filter MAC Address Register - High */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 133 | #define MTK_GDMA_MAC_ADRH(x) ((x == MTK_GMAC3_ID) ? \ |
| 134 | 0x54C : 0x50C + (x * 0x1000)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 135 | |
| 136 | /* Internal SRAM offset */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 137 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 138 | #define MTK_ETH_SRAM_OFFSET 0x300000 |
| 139 | #else |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 140 | #define MTK_ETH_SRAM_OFFSET 0x40000 |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 141 | #endif |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 142 | |
| 143 | /* FE global misc reg*/ |
| 144 | #define MTK_FE_GLO_MISC 0x124 |
| 145 | |
developer | fef9efd | 2021-06-16 18:28:09 +0800 | [diff] [blame] | 146 | /* PSE Free Queue Flow Control */ |
| 147 | #define PSE_FQFC_CFG1 0x100 |
| 148 | #define PSE_FQFC_CFG2 0x104 |
developer | 459b78e | 2022-07-01 17:25:10 +0800 | [diff] [blame] | 149 | #define PSE_NO_DROP_CFG 0x108 |
| 150 | #define PSE_PPE0_DROP 0x110 |
developer | fef9efd | 2021-06-16 18:28:09 +0800 | [diff] [blame] | 151 | |
developer | 15f760a | 2022-10-12 15:57:21 +0800 | [diff] [blame] | 152 | /* PSE Last FreeQ Page Request Control */ |
| 153 | #define PSE_DUMY_REQ 0x10C |
| 154 | #define PSE_DUMMY_WORK_GDM(x) BIT(16 + (x)) |
| 155 | #define DUMMY_PAGE_THR 0x151 |
| 156 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 157 | /* PSE Input Queue Reservation Register*/ |
| 158 | #define PSE_IQ_REV(x) (0x140 + ((x - 1) * 0x4)) |
| 159 | |
| 160 | /* PSE Output Queue Threshold Register*/ |
| 161 | #define PSE_OQ_TH(x) (0x160 + ((x - 1) * 0x4)) |
| 162 | |
developer | fef9efd | 2021-06-16 18:28:09 +0800 | [diff] [blame] | 163 | /* GDM and CDM Threshold */ |
| 164 | #define MTK_GDM2_THRES 0x1530 |
| 165 | #define MTK_CDMW0_THRES 0x164c |
| 166 | #define MTK_CDMW1_THRES 0x1650 |
| 167 | #define MTK_CDME0_THRES 0x1654 |
| 168 | #define MTK_CDME1_THRES 0x1658 |
| 169 | #define MTK_CDMM_THRES 0x165c |
| 170 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 171 | #define MTK_PDMA_V2 BIT(4) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 172 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 173 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 174 | #define PDMA_BASE 0x6800 |
| 175 | #define QDMA_BASE 0x4400 |
| 176 | #define WDMA_BASE(x) (0x4800 + ((x) * 0x400)) |
developer | 2a050ba | 2022-12-01 16:11:06 +0800 | [diff] [blame] | 177 | #define PPE_BASE(x) ((x == 2) ? 0x2E00 : 0x2200 + ((x) * 0x400)) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 178 | #elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 179 | #define PDMA_BASE 0x6000 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 180 | #define QDMA_BASE 0x4400 |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 181 | #define WDMA_BASE(x) (0x4800 + ((x) * 0x400)) |
| 182 | #define PPE_BASE(x) (0x2200 + ((x) * 0x400)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 183 | #else |
| 184 | #define PDMA_BASE 0x0800 |
| 185 | #define QDMA_BASE 0x1800 |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 186 | #define WDMA_BASE(x) (0x2800 + ((x) * 0x400)) |
| 187 | #define PPE_BASE(x) (0xE00 + ((x) * 0x400)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 188 | #endif |
| 189 | /* PDMA RX Base Pointer Register */ |
| 190 | #define MTK_PRX_BASE_PTR0 (PDMA_BASE + 0x100) |
| 191 | #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) |
| 192 | |
| 193 | /* PDMA RX Maximum Count Register */ |
| 194 | #define MTK_PRX_MAX_CNT0 (MTK_PRX_BASE_PTR0 + 0x04) |
| 195 | #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) |
| 196 | |
| 197 | /* PDMA RX CPU Pointer Register */ |
| 198 | #define MTK_PRX_CRX_IDX0 (MTK_PRX_BASE_PTR0 + 0x08) |
| 199 | #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) |
| 200 | |
developer | 77f3fd4 | 2021-10-05 15:16:05 +0800 | [diff] [blame] | 201 | /* PDMA RX DMA Pointer Register */ |
| 202 | #define MTK_PRX_DRX_IDX0 (MTK_PRX_BASE_PTR0 + 0x0c) |
| 203 | #define MTK_PRX_DRX_IDX_CFG(x) (MTK_PRX_DRX_IDX0 + (x * 0x10)) |
| 204 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 205 | /* PDMA HW LRO Control Registers */ |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 206 | #define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n))) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 207 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 208 | #define MTK_MAX_RX_RING_NUM (8) |
| 209 | #define MTK_HW_LRO_RING_NUM (4) |
| 210 | #define IS_HW_LRO_RING(ring_no) (((ring_no) > 3) && ((ring_no) < 8)) |
| 211 | #define MTK_PDMA_LRO_CTRL_DW0 (PDMA_BASE + 0x408) |
| 212 | #define MTK_LRO_ALT_SCORE_DELTA (PDMA_BASE + 0x41c) |
| 213 | #define MTK_LRO_RX_RING0_CTRL_DW1 (PDMA_BASE + 0x438) |
| 214 | #define MTK_LRO_RX_RING0_CTRL_DW2 (PDMA_BASE + 0x43c) |
| 215 | #define MTK_LRO_RX_RING0_CTRL_DW3 (PDMA_BASE + 0x440) |
| 216 | #define MTK_L3_CKS_UPD_EN BIT(19) |
| 217 | #define MTK_LRO_CRSN_BNW BIT(22) |
| 218 | #define MTK_LRO_RING_RELINGUISH_REQ (0xf << 24) |
| 219 | #define MTK_LRO_RING_RELINGUISH_DONE (0xf << 28) |
| 220 | #else |
| 221 | #define MTK_MAX_RX_RING_NUM (4) |
| 222 | #define MTK_HW_LRO_RING_NUM (3) |
| 223 | #define IS_HW_LRO_RING(ring_no) (((ring_no) > 0) && ((ring_no) < 4)) |
| 224 | #define MTK_PDMA_LRO_CTRL_DW0 (PDMA_BASE + 0x180) |
| 225 | #define MTK_LRO_ALT_SCORE_DELTA (PDMA_BASE + 0x24c) |
| 226 | #define MTK_LRO_RX_RING0_CTRL_DW1 (PDMA_BASE + 0x328) |
| 227 | #define MTK_LRO_RX_RING0_CTRL_DW2 (PDMA_BASE + 0x32c) |
| 228 | #define MTK_LRO_RX_RING0_CTRL_DW3 (PDMA_BASE + 0x330) |
| 229 | #define MTK_LRO_CRSN_BNW BIT(6) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 230 | #define MTK_L3_CKS_UPD_EN BIT(7) |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 231 | #define MTK_LRO_RING_RELINGUISH_REQ (0x7 << 26) |
| 232 | #define MTK_LRO_RING_RELINGUISH_DONE (0x7 << 29) |
| 233 | #endif |
| 234 | |
| 235 | #define IS_NORMAL_RING(ring_no) ((ring_no) == 0) |
| 236 | #define MTK_LRO_EN BIT(0) |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 237 | #define MTK_NON_LRO_MULTI_EN BIT(2) |
| 238 | #define MTK_LRO_DLY_INT_EN BIT(5) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 239 | #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 240 | #define MTK_LRO_L4_CTRL_PSH_EN BIT(23) |
| 241 | #define MTK_CTRL_DW0_SDL_OFFSET (3) |
| 242 | #define MTK_CTRL_DW0_SDL_MASK BITS(3, 18) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 243 | |
| 244 | #define MTK_PDMA_LRO_CTRL_DW1 (MTK_PDMA_LRO_CTRL_DW0 + 0x04) |
| 245 | #define MTK_PDMA_LRO_CTRL_DW2 (MTK_PDMA_LRO_CTRL_DW0 + 0x08) |
| 246 | #define MTK_PDMA_LRO_CTRL_DW3 (MTK_PDMA_LRO_CTRL_DW0 + 0x0c) |
| 247 | #define MTK_ADMA_MODE BIT(15) |
| 248 | #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) |
| 249 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 250 | /* PDMA RSS Control Registers */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 251 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 252 | #define MTK_PDMA_RSS_GLO_CFG (PDMA_BASE + 0x800) |
| 253 | #define MTK_RX_NAPI_NUM (2) |
| 254 | #define MTK_MAX_IRQ_NUM (4) |
| 255 | #else |
| 256 | #define MTK_PDMA_RSS_GLO_CFG 0x3000 |
| 257 | #define MTK_RX_NAPI_NUM (1) |
| 258 | #define MTK_MAX_IRQ_NUM (3) |
| 259 | #endif |
| 260 | #define MTK_RSS_RING1 (1) |
| 261 | #define MTK_RSS_EN BIT(0) |
| 262 | #define MTK_RSS_CFG_REQ BIT(2) |
| 263 | #define MTK_RSS_IPV6_STATIC_HASH (0x7 << 8) |
| 264 | #define MTK_RSS_IPV4_STATIC_HASH (0x7 << 12) |
| 265 | #define MTK_RSS_INDR_TABLE_DW0 (MTK_PDMA_RSS_GLO_CFG + 0x50) |
| 266 | #define MTK_RSS_INDR_TABLE_DW1 (MTK_PDMA_RSS_GLO_CFG + 0x54) |
| 267 | #define MTK_RSS_INDR_TABLE_DW2 (MTK_PDMA_RSS_GLO_CFG + 0x58) |
| 268 | #define MTK_RSS_INDR_TABLE_DW3 (MTK_PDMA_RSS_GLO_CFG + 0x5C) |
| 269 | #define MTK_RSS_INDR_TABLE_DW4 (MTK_PDMA_RSS_GLO_CFG + 0x60) |
| 270 | #define MTK_RSS_INDR_TABLE_DW5 (MTK_PDMA_RSS_GLO_CFG + 0x64) |
| 271 | #define MTK_RSS_INDR_TABLE_DW6 (MTK_PDMA_RSS_GLO_CFG + 0x68) |
| 272 | #define MTK_RSS_INDR_TABLE_DW7 (MTK_PDMA_RSS_GLO_CFG + 0x6C) |
| 273 | #define MTK_RSS_INDR_TABLE_SIZE4 0x44444444 |
| 274 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 275 | /* PDMA Global Configuration Register */ |
| 276 | #define MTK_PDMA_GLO_CFG (PDMA_BASE + 0x204) |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 277 | #define MTK_RX_DMA_LRO_EN BIT(8) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 278 | #define MTK_MULTI_EN BIT(10) |
| 279 | #define MTK_PDMA_SIZE_8DWORDS (1 << 4) |
| 280 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 281 | /* PDMA Global Configuration Register */ |
| 282 | #define MTK_PDMA_RX_CFG (PDMA_BASE + 0x210) |
| 283 | #define MTK_PDMA_LRO_SDL (0x3000) |
| 284 | #define MTK_RX_CFG_SDL_OFFSET (16) |
| 285 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 286 | /* PDMA Reset Index Register */ |
| 287 | #define MTK_PDMA_RST_IDX (PDMA_BASE + 0x208) |
| 288 | #define MTK_PST_DRX_IDX0 BIT(16) |
| 289 | #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) |
| 290 | |
| 291 | /* PDMA Delay Interrupt Register */ |
| 292 | #define MTK_PDMA_DELAY_INT (PDMA_BASE + 0x20c) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 293 | #define MTK_PDMA_RSS_DELAY_INT (PDMA_BASE + 0x2c0) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 294 | #define MTK_PDMA_DELAY_RX_EN BIT(15) |
| 295 | #define MTK_PDMA_DELAY_RX_PINT 4 |
| 296 | #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 |
| 297 | #define MTK_PDMA_DELAY_RX_PTIME 4 |
| 298 | #define MTK_PDMA_DELAY_RX_DELAY \ |
| 299 | (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \ |
| 300 | (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT)) |
| 301 | |
| 302 | /* PDMA Interrupt Status Register */ |
| 303 | #define MTK_PDMA_INT_STATUS (PDMA_BASE + 0x220) |
| 304 | |
| 305 | /* PDMA Interrupt Mask Register */ |
| 306 | #define MTK_PDMA_INT_MASK (PDMA_BASE + 0x228) |
| 307 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 308 | /* PDMA Interrupt grouping registers */ |
| 309 | #define MTK_PDMA_INT_GRP1 (PDMA_BASE + 0x250) |
| 310 | #define MTK_PDMA_INT_GRP2 (PDMA_BASE + 0x254) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 311 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 312 | #define MTK_PDMA_INT_GRP3 (PDMA_BASE + 0x258) |
| 313 | #else |
| 314 | #define MTK_PDMA_INT_GRP3 (PDMA_BASE + 0x22c) |
| 315 | #endif |
| 316 | #define MTK_LRO_RX1_DLY_INT 0xa70 |
| 317 | #define MTK_MAX_DELAY_INT 0x8f0f8f0f |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 318 | |
| 319 | /* PDMA HW LRO IP Setting Registers */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 320 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 321 | #define MTK_LRO_RX_RING0_DIP_DW0 (PDMA_BASE + 0x414) |
| 322 | #else |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 323 | #define MTK_LRO_RX_RING0_DIP_DW0 (PDMA_BASE + 0x304) |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 324 | #endif |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 325 | #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) |
| 326 | #define MTK_RING_MYIP_VLD BIT(9) |
| 327 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 328 | /* PDMA HW LRO ALT Debug Registers */ |
| 329 | #define MTK_LRO_ALT_DBG (PDMA_BASE + 0x440) |
| 330 | #define MTK_LRO_ALT_INDEX_OFFSET (8) |
| 331 | |
| 332 | /* PDMA HW LRO ALT Data Registers */ |
| 333 | #define MTK_LRO_ALT_DBG_DATA (PDMA_BASE + 0x444) |
| 334 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 335 | /* PDMA HW LRO Ring Control Registers */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 336 | #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) |
| 337 | #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) |
| 338 | #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) |
| 339 | #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) |
| 340 | #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 341 | #define MTK_RING_PSE_MODE (1 << 6) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 342 | #define MTK_RING_AUTO_LERAN_MODE (3 << 6) |
| 343 | #define MTK_RING_VLD BIT(8) |
| 344 | #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) |
| 345 | #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) |
| 346 | #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) |
| 347 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 348 | /* LRO_RX_RING_CTRL_DW masks */ |
| 349 | #define MTK_LRO_RING_AGG_TIME_MASK BITS(10, 25) |
| 350 | #define MTK_LRO_RING_AGG_CNT_L_MASK BITS(26, 31) |
| 351 | #define MTK_LRO_RING_AGG_CNT_H_MASK BITS(0, 1) |
| 352 | #define MTK_LRO_RING_AGE_TIME_L_MASK BITS(22, 31) |
| 353 | #define MTK_LRO_RING_AGE_TIME_H_MASK BITS(0, 5) |
| 354 | |
| 355 | /* LRO_RX_RING_CTRL_DW0 offsets */ |
| 356 | #define MTK_RX_IPV6_FORCE_OFFSET (0) |
| 357 | #define MTK_RX_IPV4_FORCE_OFFSET (1) |
| 358 | |
| 359 | /* LRO_RX_RING_CTRL_DW1 offsets */ |
| 360 | #define MTK_LRO_RING_AGE_TIME_L_OFFSET (22) |
| 361 | |
| 362 | /* LRO_RX_RING_CTRL_DW2 offsets */ |
| 363 | #define MTK_LRO_RING_AGE_TIME_H_OFFSET (0) |
| 364 | #define MTK_RX_MODE_OFFSET (6) |
| 365 | #define MTK_RX_PORT_VALID_OFFSET (8) |
| 366 | #define MTK_RX_MYIP_VALID_OFFSET (9) |
| 367 | #define MTK_LRO_RING_AGG_TIME_OFFSET (10) |
| 368 | #define MTK_LRO_RING_AGG_CNT_L_OFFSET (26) |
| 369 | |
| 370 | /* LRO_RX_RING_CTRL_DW3 offsets */ |
| 371 | #define MTK_LRO_RING_AGG_CNT_H_OFFSET (0) |
| 372 | |
| 373 | /* LRO_RX_RING_STP_DTP_DW offsets */ |
| 374 | #define MTK_RX_TCP_DEST_PORT_OFFSET (0) |
| 375 | #define MTK_RX_TCP_SRC_PORT_OFFSET (16) |
| 376 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 377 | /* QDMA TX Queue Configuration Registers */ |
| 378 | #define MTK_QTX_CFG(x) (QDMA_BASE + (x * 0x10)) |
| 379 | #define QDMA_RES_THRES 4 |
| 380 | |
| 381 | /* QDMA TX Queue Scheduler Registers */ |
| 382 | #define MTK_QTX_SCH(x) (QDMA_BASE + 4 + (x * 0x10)) |
| 383 | |
| 384 | /* QDMA RX Base Pointer Register */ |
| 385 | #define MTK_QRX_BASE_PTR0 (QDMA_BASE + 0x100) |
| 386 | #define MTK_QRX_BASE_PTR_CFG(x) (MTK_QRX_BASE_PTR0 + ((x) * 0x10)) |
| 387 | |
| 388 | /* QDMA RX Maximum Count Register */ |
| 389 | #define MTK_QRX_MAX_CNT0 (QDMA_BASE + 0x104) |
| 390 | #define MTK_QRX_MAX_CNT_CFG(x) (MTK_QRX_MAX_CNT0 + ((x) * 0x10)) |
| 391 | |
| 392 | /* QDMA RX CPU Pointer Register */ |
| 393 | #define MTK_QRX_CRX_IDX0 (QDMA_BASE + 0x108) |
| 394 | #define MTK_QRX_CRX_IDX_CFG(x) (MTK_QRX_CRX_IDX0 + ((x) * 0x10)) |
| 395 | |
| 396 | /* QDMA RX DMA Pointer Register */ |
| 397 | #define MTK_QRX_DRX_IDX0 (QDMA_BASE + 0x10c) |
| 398 | |
developer | 329d8ee | 2022-08-02 08:49:42 +0800 | [diff] [blame] | 399 | /* QDMA Page Configuration Register */ |
| 400 | #define MTK_QDMA_PAGE (QDMA_BASE + 0x1f0) |
| 401 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 402 | /* QDMA Global Configuration Register */ |
| 403 | #define MTK_QDMA_GLO_CFG (QDMA_BASE + 0x204) |
| 404 | #define MTK_RX_2B_OFFSET BIT(31) |
developer | 58ab584 | 2022-06-01 15:10:25 +0800 | [diff] [blame] | 405 | #define MTK_PKT_RX_WDONE BIT(27) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 406 | #define MTK_RX_BT_32DWORDS (3 << 11) |
| 407 | #define MTK_NDP_CO_PRO BIT(10) |
| 408 | #define MTK_TX_WB_DDONE BIT(6) |
| 409 | #define MTK_DMA_SIZE_16DWORDS (2 << 4) |
| 410 | #define MTK_DMA_SIZE_32DWORDS (3 << 4) |
| 411 | #define MTK_RX_DMA_BUSY BIT(3) |
| 412 | #define MTK_TX_DMA_BUSY BIT(1) |
| 413 | #define MTK_RX_DMA_EN BIT(2) |
| 414 | #define MTK_TX_DMA_EN BIT(0) |
| 415 | #define MTK_DMA_BUSY_TIMEOUT HZ |
| 416 | |
| 417 | /* QDMA V2 Global Configuration Register */ |
| 418 | #define MTK_CHK_DDONE_EN BIT(28) |
| 419 | #define MTK_DMAD_WR_WDONE BIT(26) |
| 420 | #define MTK_WCOMP_EN BIT(24) |
developer | 2cdef09 | 2022-04-15 17:27:55 +0800 | [diff] [blame] | 421 | #define MTK_RESV_BUF (0x80 << 16) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 422 | #define MTK_MUTLI_CNT (0x4 << 12) |
developer | 19d8456 | 2022-04-21 17:01:06 +0800 | [diff] [blame] | 423 | #define MTK_RESV_BUF_MASK (0xff << 16) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 424 | |
| 425 | /* QDMA Reset Index Register */ |
| 426 | #define MTK_QDMA_RST_IDX (QDMA_BASE + 0x208) |
| 427 | |
| 428 | /* QDMA Delay Interrupt Register */ |
| 429 | #define MTK_QDMA_DELAY_INT (QDMA_BASE + 0x20c) |
| 430 | |
| 431 | /* QDMA Flow Control Register */ |
| 432 | #define MTK_QDMA_FC_THRES (QDMA_BASE + 0x210) |
| 433 | #define FC_THRES_DROP_MODE BIT(20) |
| 434 | #define FC_THRES_DROP_EN (7 << 16) |
| 435 | #define FC_THRES_MIN 0x4444 |
| 436 | |
| 437 | /* QDMA Interrupt Status Register */ |
| 438 | #define MTK_QDMA_INT_STATUS (QDMA_BASE + 0x218) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 439 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 440 | #define MTK_RX_DONE_INT(ring_no) \ |
| 441 | (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS) ? (BIT(24 + (ring_no))) : \ |
| 442 | ((ring_no) ? BIT(16 + (ring_no)) : BIT(14))) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 443 | #else |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 444 | #define MTK_RX_DONE_INT(ring_no) \ |
| 445 | ((ring_no)? BIT(24 + (ring_no)) : BIT(30)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 446 | #endif |
| 447 | #define MTK_RX_DONE_INT3 BIT(19) |
| 448 | #define MTK_RX_DONE_INT2 BIT(18) |
| 449 | #define MTK_RX_DONE_INT1 BIT(17) |
| 450 | #define MTK_RX_DONE_INT0 BIT(16) |
| 451 | #define MTK_TX_DONE_INT3 BIT(3) |
| 452 | #define MTK_TX_DONE_INT2 BIT(2) |
| 453 | #define MTK_TX_DONE_INT1 BIT(1) |
| 454 | #define MTK_TX_DONE_INT0 BIT(0) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 455 | #define MTK_TX_DONE_DLY BIT(28) |
| 456 | #define MTK_TX_DONE_INT MTK_TX_DONE_DLY |
| 457 | |
| 458 | /* QDMA Interrupt grouping registers */ |
| 459 | #define MTK_QDMA_INT_GRP1 (QDMA_BASE + 0x220) |
| 460 | #define MTK_QDMA_INT_GRP2 (QDMA_BASE + 0x224) |
| 461 | #define MTK_RLS_DONE_INT BIT(0) |
| 462 | |
| 463 | /* QDMA Interrupt Status Register */ |
| 464 | #define MTK_QDMA_INT_MASK (QDMA_BASE + 0x21c) |
| 465 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 466 | /* QDMA DMA FSM */ |
| 467 | #define MTK_QDMA_FSM (QDMA_BASE + 0x234) |
| 468 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 469 | /* QDMA Interrupt Mask Register */ |
| 470 | #define MTK_QDMA_HRED2 (QDMA_BASE + 0x244) |
| 471 | |
| 472 | /* QDMA TX Forward CPU Pointer Register */ |
| 473 | #define MTK_QTX_CTX_PTR (QDMA_BASE +0x300) |
| 474 | |
| 475 | /* QDMA TX Forward DMA Pointer Register */ |
| 476 | #define MTK_QTX_DTX_PTR (QDMA_BASE +0x304) |
| 477 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 478 | /* QDMA TX Forward DMA Counter */ |
| 479 | #define MTK_QDMA_FWD_CNT (QDMA_BASE + 0x308) |
| 480 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 481 | /* QDMA TX Release CPU Pointer Register */ |
| 482 | #define MTK_QTX_CRX_PTR (QDMA_BASE +0x310) |
| 483 | |
| 484 | /* QDMA TX Release DMA Pointer Register */ |
| 485 | #define MTK_QTX_DRX_PTR (QDMA_BASE +0x314) |
| 486 | |
| 487 | /* QDMA FQ Head Pointer Register */ |
| 488 | #define MTK_QDMA_FQ_HEAD (QDMA_BASE +0x320) |
| 489 | |
| 490 | /* QDMA FQ Head Pointer Register */ |
| 491 | #define MTK_QDMA_FQ_TAIL (QDMA_BASE +0x324) |
| 492 | |
| 493 | /* QDMA FQ Free Page Counter Register */ |
| 494 | #define MTK_QDMA_FQ_CNT (QDMA_BASE +0x328) |
| 495 | |
| 496 | /* QDMA FQ Free Page Buffer Length Register */ |
| 497 | #define MTK_QDMA_FQ_BLEN (QDMA_BASE +0x32c) |
| 498 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 499 | /* WDMA Registers */ |
developer | 37482a4 | 2022-12-26 13:31:13 +0800 | [diff] [blame] | 500 | #define MTK_WDMA_CTX_PTR(x) (WDMA_BASE(x) + 0x8) |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 501 | #define MTK_WDMA_DTX_PTR(x) (WDMA_BASE(x) + 0xC) |
| 502 | #define MTK_WDMA_GLO_CFG(x) (WDMA_BASE(x) + 0x204) |
| 503 | #define MTK_WDMA_TX_DBG_MON0(x) (WDMA_BASE(x) + 0x230) |
developer | 37482a4 | 2022-12-26 13:31:13 +0800 | [diff] [blame] | 504 | #define MTK_WDMA_RX_DBG_MON1(x) (WDMA_BASE(x) + 0x3c4) |
| 505 | #define MTK_WDMA_CRX_PTR(x) (WDMA_BASE(x) + 0x108) |
| 506 | #define MTK_WDMA_DRX_PTR(x) (WDMA_BASE(x) + 0x10C) |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 507 | #define MTK_CDM_TXFIFO_RDY BIT(7) |
| 508 | |
developer | 37482a4 | 2022-12-26 13:31:13 +0800 | [diff] [blame] | 509 | /*TDMA Register*/ |
| 510 | #define MTK_TDMA_GLO_CFG (0x6204) |
| 511 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 512 | /* GMA1 Received Good Byte Count Register */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 513 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 514 | #define MTK_GDM1_TX_GBCNT 0x1C00 |
| 515 | #else |
| 516 | #define MTK_GDM1_TX_GBCNT 0x2400 |
| 517 | #endif |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 518 | |
| 519 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 520 | #define MTK_STAT_OFFSET 0x80 |
| 521 | #else |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 522 | #define MTK_STAT_OFFSET 0x40 |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 523 | #endif |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 524 | |
| 525 | /* QDMA TX NUM */ |
| 526 | #define MTK_QDMA_TX_NUM 16 |
developer | 797e46c | 2022-07-29 12:05:32 +0800 | [diff] [blame] | 527 | #define MTK_QDMA_PAGE_NUM 8 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 528 | #define MTK_QDMA_TX_MASK ((MTK_QDMA_TX_NUM) - 1) |
| 529 | #define QID_LOW_BITS(x) ((x) & 0xf) |
| 530 | #define QID_HIGH_BITS(x) ((((x) >> 4) & 0x3) << 20) |
| 531 | #define QID_BITS_V2(x) (((x) & 0x3f) << 16) |
| 532 | |
developer | dc0d45f | 2021-12-27 13:01:22 +0800 | [diff] [blame] | 533 | #define MTK_QDMA_GMAC2_QID 8 |
| 534 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 535 | /* QDMA V2 descriptor txd6 */ |
| 536 | #define TX_DMA_INS_VLAN_V2 BIT(16) |
| 537 | |
| 538 | /* QDMA V2 descriptor txd5 */ |
| 539 | #define TX_DMA_CHKSUM_V2 (0x7 << 28) |
| 540 | #define TX_DMA_TSO_V2 BIT(31) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 541 | #define TX_DMA_SPTAG_V3 BIT(27) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 542 | |
| 543 | /* QDMA V2 descriptor txd4 */ |
| 544 | #define TX_DMA_FPORT_SHIFT_V2 8 |
| 545 | #define TX_DMA_FPORT_MASK_V2 0xf |
| 546 | #define TX_DMA_SWC_V2 BIT(30) |
| 547 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 548 | #define MTK_TX_DMA_BUF_LEN 0x3fff |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 549 | #define MTK_TX_DMA_BUF_LEN_V2 0xffff |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 550 | #define MTK_TX_DMA_BUF_SHIFT 16 |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 551 | #define MTK_TX_DMA_BUF_SHIFT_V2 8 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 552 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 553 | #define RX_DMA_SPORT_SHIFT 19 |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 554 | #define RX_DMA_SPORT_SHIFT_V2 26 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 555 | #define RX_DMA_SPORT_MASK 0x7 |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 556 | #define RX_DMA_SPORT_MASK_V2 0xf |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 557 | |
| 558 | /* QDMA descriptor txd4 */ |
| 559 | #define TX_DMA_CHKSUM (0x7 << 29) |
| 560 | #define TX_DMA_TSO BIT(28) |
| 561 | #define TX_DMA_FPORT_SHIFT 25 |
| 562 | #define TX_DMA_FPORT_MASK 0x7 |
| 563 | #define TX_DMA_INS_VLAN BIT(16) |
| 564 | |
| 565 | /* QDMA descriptor txd3 */ |
| 566 | #define TX_DMA_OWNER_CPU BIT(31) |
| 567 | #define TX_DMA_LS0 BIT(30) |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 568 | #define TX_DMA_PLEN0(_x) (((_x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) |
| 569 | #define TX_DMA_PLEN1(_x) ((_x) & eth->soc->txrx.dma_max_len) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 570 | #define TX_DMA_SWC BIT(14) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 571 | #define TX_DMA_SDP1(_x) ((((u64)(_x)) >> 32) & 0xf) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 572 | |
| 573 | /* PDMA on MT7628 */ |
| 574 | #define TX_DMA_DONE BIT(31) |
| 575 | #define TX_DMA_LS1 BIT(14) |
| 576 | #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) |
| 577 | |
| 578 | /* QDMA descriptor rxd2 */ |
| 579 | #define RX_DMA_DONE BIT(31) |
| 580 | #define RX_DMA_LSO BIT(30) |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 581 | #define RX_DMA_PLEN0(_x) (((_x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) |
| 582 | #define RX_DMA_GET_PLEN0(_x) (((_x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 583 | #define RX_DMA_GET_AGG_CNT(_x) (((_x) >> 2) & 0xff) |
| 584 | #define RX_DMA_GET_REV(_x) (((_x) >> 10) & 0x1f) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 585 | #define RX_DMA_VTAG BIT(15) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 586 | #define RX_DMA_SDP1(_x) ((((u64)(_x)) >> 32) & 0xf) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 587 | |
| 588 | /* QDMA descriptor rxd3 */ |
| 589 | #define RX_DMA_VID(_x) ((_x) & VLAN_VID_MASK) |
| 590 | #define RX_DMA_TCI(_x) ((_x) & (VLAN_PRIO_MASK | VLAN_VID_MASK)) |
| 591 | #define RX_DMA_VPID(_x) (((_x) >> 16) & 0xffff) |
| 592 | |
| 593 | /* QDMA descriptor rxd4 */ |
| 594 | #define RX_DMA_L4_VALID BIT(24) |
| 595 | #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ |
| 596 | #define RX_DMA_SPECIAL_TAG BIT(22) /* switch header in packet */ |
| 597 | |
| 598 | #define RX_DMA_GET_SPORT(_x) (((_x) >> RX_DMA_SPORT_SHIFT) & RX_DMA_SPORT_MASK) |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 599 | #define RX_DMA_GET_SPORT_V2(_x) (((_x) >> RX_DMA_SPORT_SHIFT_V2) & RX_DMA_SPORT_MASK_V2) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 600 | |
| 601 | /* PDMA V2 descriptor rxd3 */ |
| 602 | #define RX_DMA_VTAG_V2 BIT(0) |
| 603 | #define RX_DMA_L4_VALID_V2 BIT(2) |
| 604 | |
| 605 | /* PDMA V2 descriptor rxd4 */ |
| 606 | #define RX_DMA_VID_V2(_x) RX_DMA_VID(_x) |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 607 | #define RX_DMA_TCI_V2(_x) RX_DMA_TCI(_x) |
| 608 | #define RX_DMA_VPID_V2(_x) RX_DMA_VPID(_x) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 609 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 610 | /* PDMA V2 descriptor rxd6 */ |
| 611 | #define RX_DMA_GET_FLUSH_RSN_V2(_x) ((_x) & 0x7) |
| 612 | #define RX_DMA_GET_AGG_CNT_V2(_x) (((_x) >> 16) & 0xff) |
developer | 006325c | 2022-10-06 16:39:50 +0800 | [diff] [blame] | 613 | #define RX_DMA_GET_TOPS_CRSN(_x) (((_x) >> 24) & 0xff) |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 614 | |
developer | c8acd8d | 2022-11-10 09:07:10 +0800 | [diff] [blame] | 615 | /* PHY Polling and SMI Master Control registers */ |
| 616 | #define MTK_PPSC 0x10000 |
| 617 | #define PPSC_MDC_CFG GENMASK(29, 24) |
| 618 | #define PPSC_MDC_TURBO BIT(20) |
| 619 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 620 | /* PHY Indirect Access Control registers */ |
| 621 | #define MTK_PHY_IAC 0x10004 |
| 622 | #define PHY_IAC_ACCESS BIT(31) |
| 623 | #define PHY_IAC_READ BIT(19) |
developer | 599cda4 | 2022-05-24 15:13:31 +0800 | [diff] [blame] | 624 | #define PHY_IAC_READ_C45 (3 << 18) |
| 625 | #define PHY_IAC_ADDR_C45 (0 << 18) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 626 | #define PHY_IAC_WRITE BIT(18) |
| 627 | #define PHY_IAC_START BIT(16) |
developer | 599cda4 | 2022-05-24 15:13:31 +0800 | [diff] [blame] | 628 | #define PHY_IAC_START_C45 (0 << 16) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 629 | #define PHY_IAC_ADDR_SHIFT 20 |
| 630 | #define PHY_IAC_REG_SHIFT 25 |
| 631 | #define PHY_IAC_TIMEOUT HZ |
| 632 | |
developer | c8acd8d | 2022-11-10 09:07:10 +0800 | [diff] [blame] | 633 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 634 | #define MTK_MAC_MISC 0x10010 |
| 635 | #else |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 636 | #define MTK_MAC_MISC 0x1000c |
developer | c8acd8d | 2022-11-10 09:07:10 +0800 | [diff] [blame] | 637 | #endif |
| 638 | #define MISC_MDC_TURBO BIT(4) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 639 | #define MTK_MUX_TO_ESW BIT(0) |
| 640 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 641 | /* XMAC status registers */ |
| 642 | #define MTK_XGMAC_STS(x) ((x == MTK_GMAC3_ID) ? 0x1001C : 0x1000C) |
| 643 | #define MTK_XGMAC_FORCE_LINK BIT(15) |
| 644 | #define MTK_USXGMII_PCS_LINK BIT(8) |
| 645 | #define MTK_XGMAC_RX_FC BIT(5) |
| 646 | #define MTK_XGMAC_TX_FC BIT(4) |
| 647 | #define MTK_USXGMII_PCS_MODE GENMASK(3, 1) |
| 648 | #define MTK_XGMAC_LINK_STS BIT(0) |
| 649 | |
| 650 | /* GSW bridge registers */ |
| 651 | #define MTK_GSW_CFG (0x10080) |
| 652 | #define GSWTX_IPG_MASK GENMASK(19, 16) |
| 653 | #define GSWTX_IPG_SHIFT 16 |
| 654 | #define GSWRX_IPG_MASK GENMASK(3, 0) |
| 655 | #define GSWRX_IPG_SHIFT 0 |
| 656 | #define GSW_IPG_11 11 |
| 657 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 658 | /* Mac control registers */ |
| 659 | #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) |
| 660 | #define MAC_MCR_MAX_RX_1536 BIT(24) |
developer | d8a2975 | 2022-08-19 13:32:03 +0800 | [diff] [blame] | 661 | #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16) | BIT(12)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 662 | #define MAC_MCR_FORCE_MODE BIT(15) |
| 663 | #define MAC_MCR_TX_EN BIT(14) |
| 664 | #define MAC_MCR_RX_EN BIT(13) |
| 665 | #define MAC_MCR_BACKOFF_EN BIT(9) |
| 666 | #define MAC_MCR_BACKPR_EN BIT(8) |
developer | 9b72593 | 2022-11-24 16:25:56 +0800 | [diff] [blame] | 667 | #define MAC_MCR_FORCE_EEE1000 BIT(7) |
| 668 | #define MAC_MCR_FORCE_EEE100 BIT(6) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 669 | #define MAC_MCR_FORCE_RX_FC BIT(5) |
| 670 | #define MAC_MCR_FORCE_TX_FC BIT(4) |
| 671 | #define MAC_MCR_SPEED_1000 BIT(3) |
| 672 | #define MAC_MCR_SPEED_100 BIT(2) |
| 673 | #define MAC_MCR_FORCE_DPX BIT(1) |
| 674 | #define MAC_MCR_FORCE_LINK BIT(0) |
| 675 | #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) |
| 676 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 677 | /* XFI Mac control registers */ |
| 678 | #define MTK_XMAC_MCR(x) (0x12000 + ((x - 1) * 0x1000)) |
| 679 | #define XMAC_MCR_TRX_DISABLE 0xf |
| 680 | #define XMAC_MCR_FORCE_TX_FC BIT(5) |
| 681 | #define XMAC_MCR_FORCE_RX_FC BIT(4) |
| 682 | |
developer | 9b72593 | 2022-11-24 16:25:56 +0800 | [diff] [blame] | 683 | /* Mac EEE control registers */ |
| 684 | #define MTK_MAC_EEE(x) (0x10104 + (x * 0x100)) |
| 685 | #define MAC_EEE_WAKEUP_TIME_1000 GENMASK(31, 24) |
| 686 | #define MAC_EEE_WAKEUP_TIME_100 GENMASK(23, 16) |
| 687 | #define MAC_EEE_LPI_TXIDLE_THD GENMASK(15, 8) |
| 688 | #define MAC_EEE_RESV0 GENMASK(7, 4) |
| 689 | #define MAC_EEE_CKG_TXILDE BIT(3) |
| 690 | #define MAC_EEE_CKG_RXLPI BIT(2) |
| 691 | #define MAC_EEE_TX_DOWN_REQ BIT(1) |
| 692 | #define MAC_EEE_LPI_MODE BIT(0) |
| 693 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 694 | /* Mac status registers */ |
| 695 | #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) |
| 696 | #define MAC_MSR_EEE1G BIT(7) |
| 697 | #define MAC_MSR_EEE100M BIT(6) |
| 698 | #define MAC_MSR_RX_FC BIT(5) |
| 699 | #define MAC_MSR_TX_FC BIT(4) |
| 700 | #define MAC_MSR_SPEED_1000 BIT(3) |
| 701 | #define MAC_MSR_SPEED_100 BIT(2) |
| 702 | #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) |
| 703 | #define MAC_MSR_DPX BIT(1) |
| 704 | #define MAC_MSR_LINK BIT(0) |
| 705 | |
| 706 | /* TRGMII RXC control register */ |
| 707 | #define TRGMII_RCK_CTRL 0x10300 |
| 708 | #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) |
| 709 | #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) |
| 710 | #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) |
| 711 | #define RXC_RST BIT(31) |
| 712 | #define RXC_DQSISEL BIT(30) |
| 713 | #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) |
| 714 | #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) |
| 715 | |
| 716 | #define NUM_TRGMII_CTRL 5 |
| 717 | |
| 718 | /* TRGMII RXC control register */ |
| 719 | #define TRGMII_TCK_CTRL 0x10340 |
| 720 | #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) |
| 721 | #define TXC_INV BIT(30) |
| 722 | #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) |
| 723 | #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) |
| 724 | |
| 725 | /* TRGMII TX Drive Strength */ |
| 726 | #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) |
| 727 | #define TD_DM_DRVP(x) ((x) & 0xf) |
| 728 | #define TD_DM_DRVN(x) (((x) & 0xf) << 4) |
| 729 | |
| 730 | /* TRGMII Interface mode register */ |
| 731 | #define INTF_MODE 0x10390 |
| 732 | #define TRGMII_INTF_DIS BIT(0) |
| 733 | #define TRGMII_MODE BIT(1) |
| 734 | #define TRGMII_CENTRAL_ALIGNED BIT(2) |
| 735 | #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) |
| 736 | #define INTF_MODE_RGMII_10_100 0 |
| 737 | |
| 738 | /* GPIO port control registers for GMAC 2*/ |
| 739 | #define GPIO_OD33_CTRL8 0x4c0 |
| 740 | #define GPIO_BIAS_CTRL 0xed0 |
| 741 | #define GPIO_DRV_SEL10 0xf00 |
| 742 | |
| 743 | /* ethernet subsystem chip id register */ |
| 744 | #define ETHSYS_CHIPID0_3 0x0 |
| 745 | #define ETHSYS_CHIPID4_7 0x4 |
| 746 | #define MT7623_ETH 7623 |
| 747 | #define MT7622_ETH 7622 |
| 748 | #define MT7621_ETH 7621 |
| 749 | |
| 750 | /* ethernet system control register */ |
| 751 | #define ETHSYS_SYSCFG 0x10 |
| 752 | #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) |
| 753 | |
| 754 | /* ethernet subsystem config register */ |
| 755 | #define ETHSYS_SYSCFG0 0x14 |
| 756 | #define SYSCFG0_GE_MASK 0x3 |
| 757 | #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 758 | #define SYSCFG0_SGMII_MASK GENMASK(9, 7) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 759 | #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) |
| 760 | #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) |
| 761 | #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) |
| 762 | #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 763 | #define SYSCFG0_SGMII_GMAC3_V2 BIT(7) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 764 | |
| 765 | |
| 766 | /* ethernet subsystem clock register */ |
| 767 | #define ETHSYS_CLKCFG0 0x2c |
| 768 | #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) |
| 769 | #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) |
| 770 | #define ETHSYS_TRGMII_MT7621_APLL BIT(6) |
| 771 | #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) |
| 772 | |
| 773 | /* ethernet reset control register */ |
developer | 545abf0 | 2021-07-15 17:47:01 +0800 | [diff] [blame] | 774 | #define ETHSYS_RSTCTRL 0x34 |
| 775 | #define RSTCTRL_FE BIT(6) |
developer | 545abf0 | 2021-07-15 17:47:01 +0800 | [diff] [blame] | 776 | #define RSTCTRL_ETH BIT(23) |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 777 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 778 | #define RSTCTRL_PPE0 BIT(30) |
| 779 | #define RSTCTRL_PPE1 BIT(31) |
developer | 37482a4 | 2022-12-26 13:31:13 +0800 | [diff] [blame] | 780 | #elif defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 781 | #define RSTCTRL_PPE0 BIT(29) |
| 782 | #define RSTCTRL_PPE1 BIT(30) |
| 783 | #define RSTCTRL_PPE2 BIT(31) |
| 784 | #define RSTCTRL_WDMA0 BIT(24) |
| 785 | #define RSTCTRL_WDMA1 BIT(25) |
| 786 | #define RSTCTRL_WDMA2 BIT(26) |
developer | a5eb8d6 | 2022-04-22 15:42:20 +0800 | [diff] [blame] | 787 | #else |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 788 | #define RSTCTRL_PPE0 BIT(31) |
developer | 37482a4 | 2022-12-26 13:31:13 +0800 | [diff] [blame] | 789 | #define RSTCTRL_PPE1 0 |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 790 | #endif |
developer | 545abf0 | 2021-07-15 17:47:01 +0800 | [diff] [blame] | 791 | |
| 792 | /* ethernet reset check idle register */ |
| 793 | #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28 |
| 794 | |
developer | 3f28d38 | 2023-03-07 16:06:30 +0800 | [diff] [blame^] | 795 | /* ethernet dma channel agent map */ |
| 796 | #define ETHSYS_DMA_AG_MAP 0x408 |
| 797 | #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) |
| 798 | #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) |
| 799 | #define ETHSYS_DMA_AG_MAP_PPE BIT(2) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 800 | |
| 801 | /* SGMII subsystem config registers */ |
| 802 | /* Register to auto-negotiation restart */ |
| 803 | #define SGMSYS_PCS_CONTROL_1 0x0 |
| 804 | #define SGMII_AN_RESTART BIT(9) |
| 805 | #define SGMII_ISOLATE BIT(10) |
| 806 | #define SGMII_AN_ENABLE BIT(12) |
| 807 | #define SGMII_LINK_STATYS BIT(18) |
| 808 | #define SGMII_AN_ABILITY BIT(19) |
| 809 | #define SGMII_AN_COMPLETE BIT(21) |
| 810 | #define SGMII_PCS_FAULT BIT(23) |
| 811 | #define SGMII_AN_EXPANSION_CLR BIT(30) |
| 812 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 813 | /* Register to set SGMII speed */ |
| 814 | #define SGMII_PCS_SPEED_ABILITY 0x08 |
| 815 | #define SGMII_PCS_SPEED_MASK GENMASK(11, 10) |
| 816 | #define SGMII_PCS_SPEED_10 0 |
| 817 | #define SGMII_PCS_SPEED_100 1 |
| 818 | #define SGMII_PCS_SPEED_1000 2 |
| 819 | #define SGMII_PCS_SPEED_DUPLEX BIT(12) |
| 820 | #define SGMII_PCS_SPEED_LINK BIT(15) |
| 821 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 822 | /* Register to programmable link timer, the unit in 2 * 8ns */ |
| 823 | #define SGMSYS_PCS_LINK_TIMER 0x18 |
| 824 | #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) |
| 825 | |
| 826 | /* Register to control remote fault */ |
| 827 | #define SGMSYS_SGMII_MODE 0x20 |
| 828 | #define SGMII_IF_MODE_BIT0 BIT(0) |
| 829 | #define SGMII_SPEED_DUPLEX_AN BIT(1) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 830 | #define SGMII_SPEED_MASK GENMASK(3, 2) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 831 | #define SGMII_SPEED_10 0x0 |
| 832 | #define SGMII_SPEED_100 BIT(2) |
| 833 | #define SGMII_SPEED_1000 BIT(3) |
| 834 | #define SGMII_DUPLEX_FULL BIT(4) |
| 835 | #define SGMII_IF_MODE_BIT5 BIT(5) |
| 836 | #define SGMII_REMOTE_FAULT_DIS BIT(8) |
| 837 | #define SGMII_CODE_SYNC_SET_VAL BIT(9) |
| 838 | #define SGMII_CODE_SYNC_SET_EN BIT(10) |
| 839 | #define SGMII_SEND_AN_ERROR_EN BIT(11) |
| 840 | #define SGMII_IF_MODE_MASK GENMASK(5, 1) |
| 841 | |
developer | 2b76a9d | 2022-09-20 14:59:45 +0800 | [diff] [blame] | 842 | /* Register to reset SGMII design */ |
| 843 | #define SGMII_RESERVED_0 0x34 |
| 844 | #define SGMII_SW_RESET BIT(0) |
| 845 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 846 | /* Register to set SGMII speed, ANA RG_ Control Signals III*/ |
| 847 | #define SGMSYS_ANA_RG_CS3 0x2028 |
| 848 | #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) |
| 849 | #define RG_PHY_SPEED_1_25G 0x0 |
| 850 | #define RG_PHY_SPEED_3_125G BIT(2) |
| 851 | |
| 852 | /* Register to power up QPHY */ |
| 853 | #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 |
| 854 | #define SGMII_PHYA_PWD BIT(4) |
| 855 | |
developer | f8ac94a | 2021-07-29 16:40:01 +0800 | [diff] [blame] | 856 | /* Register to QPHY wrapper control */ |
| 857 | #define SGMSYS_QPHY_WRAP_CTRL 0xec |
| 858 | #define SGMII_PN_SWAP_MASK GENMASK(1, 0) |
| 859 | #define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1)) |
| 860 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 861 | /* USXGMII subsystem config registers */ |
| 862 | /* Register to control speed */ |
| 863 | #define RG_PHY_TOP_SPEED_CTRL1 0x80C |
| 864 | #define RG_USXGMII_RATE_UPDATE_MODE BIT(31) |
| 865 | #define RG_MAC_CK_GATED BIT(29) |
| 866 | #define RG_IF_FORCE_EN BIT(28) |
| 867 | #define RG_RATE_ADAPT_MODE GENMASK(10, 8) |
| 868 | #define RG_RATE_ADAPT_MODE_X1 0 |
| 869 | #define RG_RATE_ADAPT_MODE_X2 1 |
| 870 | #define RG_RATE_ADAPT_MODE_X4 2 |
| 871 | #define RG_RATE_ADAPT_MODE_X10 3 |
| 872 | #define RG_RATE_ADAPT_MODE_X100 4 |
| 873 | #define RG_RATE_ADAPT_MODE_X5 5 |
| 874 | #define RG_RATE_ADAPT_MODE_X50 6 |
| 875 | #define RG_XFI_RX_MODE GENMASK(6, 4) |
| 876 | #define RG_XFI_RX_MODE_10G 0 |
| 877 | #define RG_XFI_RX_MODE_5G 1 |
| 878 | #define RG_XFI_TX_MODE GENMASK(2, 0) |
| 879 | #define RG_XFI_TX_MODE_10G 0 |
| 880 | #define RG_XFI_TX_MODE_5G 1 |
| 881 | |
| 882 | /* Register to control PCS AN */ |
| 883 | #define RG_PCS_AN_CTRL0 0x810 |
| 884 | #define RG_AN_ENABLE BIT(0) |
| 885 | |
| 886 | /* Register to control USXGMII XFI PLL digital */ |
| 887 | #define XFI_PLL_DIG_GLB8 0x08 |
| 888 | #define RG_XFI_PLL_EN BIT(31) |
| 889 | |
| 890 | /* Register to control USXGMII XFI PLL analog */ |
| 891 | #define XFI_PLL_ANA_GLB8 0x108 |
| 892 | #define RG_XFI_PLL_ANA_SWWA 0x02283248 |
| 893 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 894 | /* Infrasys subsystem config registers */ |
| 895 | #define INFRA_MISC2 0x70c |
| 896 | #define CO_QPHY_SEL BIT(0) |
| 897 | #define GEPHY_MAC_SEL BIT(1) |
| 898 | |
developer | 024387a | 2022-12-07 22:18:27 +0800 | [diff] [blame] | 899 | /* Toprgu subsystem config registers */ |
| 900 | #define TOPRGU_SWSYSRST 0x18 |
| 901 | #define SWSYSRST_UNLOCK_KEY GENMASK(31, 24) |
| 902 | #define SWSYSRST_XFI_PLL_GRST BIT(16) |
| 903 | #define SWSYSRST_XFI_PEXPT1_GRST BIT(15) |
| 904 | #define SWSYSRST_XFI_PEXPT0_GRST BIT(14) |
| 905 | #define SWSYSRST_SGMII1_GRST BIT(2) |
| 906 | #define SWSYSRST_SGMII0_GRST BIT(1) |
| 907 | #define TOPRGU_SWSYSRST_EN 0xFC |
| 908 | |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 909 | /* Top misc registers */ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 910 | #define TOP_MISC_NETSYS_PCS_MUX 0x84 |
| 911 | #define NETSYS_PCS_MUX_MASK GENMASK(1, 0) |
| 912 | #define MUX_G2_USXGMII_SEL BIT(1) |
| 913 | #define MUX_HSGMII1_G1_SEL BIT(0) |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 914 | #define USB_PHY_SWITCH_REG 0x218 |
| 915 | #define QPHY_SEL_MASK GENMASK(1, 0) |
developer | f1816a9 | 2021-11-15 12:18:02 +0800 | [diff] [blame] | 916 | #define SGMII_QPHY_SEL 0x2 |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 917 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 918 | /*MDIO control*/ |
| 919 | #define MII_MMD_ACC_CTL_REG 0x0d |
| 920 | #define MII_MMD_ADDR_DATA_REG 0x0e |
| 921 | #define MMD_OP_MODE_DATA BIT(14) |
| 922 | |
| 923 | /* MT7628/88 specific stuff */ |
| 924 | #define MT7628_PDMA_OFFSET 0x0800 |
| 925 | #define MT7628_SDM_OFFSET 0x0c00 |
| 926 | |
| 927 | #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) |
| 928 | #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) |
| 929 | #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) |
| 930 | #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) |
| 931 | #define MT7628_PST_DTX_IDX0 BIT(0) |
| 932 | |
| 933 | #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) |
| 934 | #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) |
| 935 | |
| 936 | struct mtk_rx_dma { |
| 937 | unsigned int rxd1; |
| 938 | unsigned int rxd2; |
| 939 | unsigned int rxd3; |
| 940 | unsigned int rxd4; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 941 | } __packed __aligned(4); |
| 942 | |
| 943 | struct mtk_rx_dma_v2 { |
| 944 | unsigned int rxd1; |
| 945 | unsigned int rxd2; |
| 946 | unsigned int rxd3; |
| 947 | unsigned int rxd4; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 948 | unsigned int rxd5; |
| 949 | unsigned int rxd6; |
| 950 | unsigned int rxd7; |
| 951 | unsigned int rxd8; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 952 | } __packed __aligned(4); |
| 953 | |
| 954 | struct mtk_tx_dma { |
| 955 | unsigned int txd1; |
| 956 | unsigned int txd2; |
| 957 | unsigned int txd3; |
| 958 | unsigned int txd4; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 959 | } __packed __aligned(4); |
| 960 | |
| 961 | struct mtk_tx_dma_v2 { |
| 962 | unsigned int txd1; |
| 963 | unsigned int txd2; |
| 964 | unsigned int txd3; |
| 965 | unsigned int txd4; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 966 | unsigned int txd5; |
| 967 | unsigned int txd6; |
| 968 | unsigned int txd7; |
| 969 | unsigned int txd8; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 970 | } __packed __aligned(4); |
| 971 | |
| 972 | struct mtk_eth; |
| 973 | struct mtk_mac; |
| 974 | |
| 975 | /* struct mtk_hw_stats - the structure that holds the traffic statistics. |
| 976 | * @stats_lock: make sure that stats operations are atomic |
| 977 | * @reg_offset: the status register offset of the SoC |
| 978 | * @syncp: the refcount |
| 979 | * |
| 980 | * All of the supported SoCs have hardware counters for traffic statistics. |
| 981 | * Whenever the status IRQ triggers we can read the latest stats from these |
| 982 | * counters and store them in this struct. |
| 983 | */ |
| 984 | struct mtk_hw_stats { |
| 985 | u64 tx_bytes; |
| 986 | u64 tx_packets; |
| 987 | u64 tx_skip; |
| 988 | u64 tx_collisions; |
| 989 | u64 rx_bytes; |
| 990 | u64 rx_packets; |
| 991 | u64 rx_overflow; |
| 992 | u64 rx_fcs_errors; |
| 993 | u64 rx_short_errors; |
| 994 | u64 rx_long_errors; |
| 995 | u64 rx_checksum_errors; |
| 996 | u64 rx_flow_control_packets; |
| 997 | |
| 998 | spinlock_t stats_lock; |
| 999 | u32 reg_offset; |
| 1000 | struct u64_stats_sync syncp; |
| 1001 | }; |
| 1002 | |
| 1003 | enum mtk_tx_flags { |
| 1004 | /* PDMA descriptor can point at 1-2 segments. This enum allows us to |
| 1005 | * track how memory was allocated so that it can be freed properly. |
| 1006 | */ |
| 1007 | MTK_TX_FLAGS_SINGLE0 = 0x01, |
| 1008 | MTK_TX_FLAGS_PAGE0 = 0x02, |
| 1009 | |
| 1010 | /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted |
| 1011 | * SKB out instead of looking up through hardware TX descriptor. |
| 1012 | */ |
| 1013 | MTK_TX_FLAGS_FPORT0 = 0x04, |
| 1014 | MTK_TX_FLAGS_FPORT1 = 0x08, |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1015 | MTK_TX_FLAGS_FPORT2 = 0x10, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1016 | }; |
| 1017 | |
| 1018 | /* This enum allows us to identify how the clock is defined on the array of the |
| 1019 | * clock in the order |
| 1020 | */ |
| 1021 | enum mtk_clks_map { |
| 1022 | MTK_CLK_ETHIF, |
| 1023 | MTK_CLK_SGMIITOP, |
| 1024 | MTK_CLK_ESW, |
| 1025 | MTK_CLK_GP0, |
| 1026 | MTK_CLK_GP1, |
| 1027 | MTK_CLK_GP2, |
developer | 1bbcf51 | 2022-11-18 16:09:33 +0800 | [diff] [blame] | 1028 | MTK_CLK_GP3, |
| 1029 | MTK_CLK_XGP1, |
| 1030 | MTK_CLK_XGP2, |
| 1031 | MTK_CLK_XGP3, |
| 1032 | MTK_CLK_CRYPTO, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1033 | MTK_CLK_FE, |
| 1034 | MTK_CLK_TRGPLL, |
| 1035 | MTK_CLK_SGMII_TX_250M, |
| 1036 | MTK_CLK_SGMII_RX_250M, |
| 1037 | MTK_CLK_SGMII_CDR_REF, |
| 1038 | MTK_CLK_SGMII_CDR_FB, |
| 1039 | MTK_CLK_SGMII2_TX_250M, |
| 1040 | MTK_CLK_SGMII2_RX_250M, |
| 1041 | MTK_CLK_SGMII2_CDR_REF, |
| 1042 | MTK_CLK_SGMII2_CDR_FB, |
| 1043 | MTK_CLK_SGMII_CK, |
| 1044 | MTK_CLK_ETH2PLL, |
| 1045 | MTK_CLK_WOCPU0, |
| 1046 | MTK_CLK_WOCPU1, |
developer | 5cfc67a | 2022-12-29 19:06:51 +0800 | [diff] [blame] | 1047 | MTK_CLK_ETHWARP_WOCPU2, |
| 1048 | MTK_CLK_ETHWARP_WOCPU1, |
| 1049 | MTK_CLK_ETHWARP_WOCPU0, |
| 1050 | MTK_CLK_TOP_USXGMII_SBUS_0_SEL, |
| 1051 | MTK_CLK_TOP_USXGMII_SBUS_1_SEL, |
| 1052 | MTK_CLK_TOP_SGM_0_SEL, |
| 1053 | MTK_CLK_TOP_SGM_1_SEL, |
| 1054 | MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL, |
| 1055 | MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL, |
| 1056 | MTK_CLK_TOP_ETH_GMII_SEL, |
| 1057 | MTK_CLK_TOP_ETH_REFCK_50M_SEL, |
| 1058 | MTK_CLK_TOP_ETH_SYS_200M_SEL, |
| 1059 | MTK_CLK_TOP_ETH_SYS_SEL, |
| 1060 | MTK_CLK_TOP_ETH_XGMII_SEL, |
| 1061 | MTK_CLK_TOP_ETH_MII_SEL, |
| 1062 | MTK_CLK_TOP_NETSYS_SEL, |
| 1063 | MTK_CLK_TOP_NETSYS_500M_SEL, |
| 1064 | MTK_CLK_TOP_NETSYS_PAO_2X_SEL, |
| 1065 | MTK_CLK_TOP_NETSYS_SYNC_250M_SEL, |
| 1066 | MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL, |
| 1067 | MTK_CLK_TOP_NETSYS_WARP_SEL, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1068 | MTK_CLK_MAX |
| 1069 | }; |
| 1070 | |
| 1071 | #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ |
| 1072 | BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ |
| 1073 | BIT(MTK_CLK_TRGPLL)) |
| 1074 | #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ |
| 1075 | BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ |
| 1076 | BIT(MTK_CLK_GP2) | \ |
| 1077 | BIT(MTK_CLK_SGMII_TX_250M) | \ |
| 1078 | BIT(MTK_CLK_SGMII_RX_250M) | \ |
| 1079 | BIT(MTK_CLK_SGMII_CDR_REF) | \ |
| 1080 | BIT(MTK_CLK_SGMII_CDR_FB) | \ |
| 1081 | BIT(MTK_CLK_SGMII_CK) | \ |
| 1082 | BIT(MTK_CLK_ETH2PLL)) |
| 1083 | #define MT7621_CLKS_BITMAP (0) |
| 1084 | #define MT7628_CLKS_BITMAP (0) |
| 1085 | #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ |
| 1086 | BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ |
| 1087 | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ |
| 1088 | BIT(MTK_CLK_SGMII_TX_250M) | \ |
| 1089 | BIT(MTK_CLK_SGMII_RX_250M) | \ |
| 1090 | BIT(MTK_CLK_SGMII_CDR_REF) | \ |
| 1091 | BIT(MTK_CLK_SGMII_CDR_FB) | \ |
| 1092 | BIT(MTK_CLK_SGMII2_TX_250M) | \ |
| 1093 | BIT(MTK_CLK_SGMII2_RX_250M) | \ |
| 1094 | BIT(MTK_CLK_SGMII2_CDR_REF) | \ |
| 1095 | BIT(MTK_CLK_SGMII2_CDR_FB) | \ |
| 1096 | BIT(MTK_CLK_SGMII_CK) | \ |
| 1097 | BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) |
| 1098 | |
| 1099 | #define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ |
| 1100 | BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ |
| 1101 | BIT(MTK_CLK_SGMII_TX_250M) | \ |
| 1102 | BIT(MTK_CLK_SGMII_RX_250M) | \ |
| 1103 | BIT(MTK_CLK_SGMII_CDR_REF) | \ |
| 1104 | BIT(MTK_CLK_SGMII_CDR_FB) | \ |
| 1105 | BIT(MTK_CLK_SGMII2_TX_250M) | \ |
| 1106 | BIT(MTK_CLK_SGMII2_RX_250M) | \ |
| 1107 | BIT(MTK_CLK_SGMII2_CDR_REF) | \ |
| 1108 | BIT(MTK_CLK_SGMII2_CDR_FB)) |
| 1109 | |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 1110 | |
developer | 9e9fb4c | 2021-11-30 17:33:04 +0800 | [diff] [blame] | 1111 | #define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ |
| 1112 | BIT(MTK_CLK_WOCPU0) | \ |
| 1113 | BIT(MTK_CLK_SGMII_TX_250M) | \ |
| 1114 | BIT(MTK_CLK_SGMII_RX_250M) | \ |
| 1115 | BIT(MTK_CLK_SGMII_CDR_REF) | \ |
| 1116 | BIT(MTK_CLK_SGMII_CDR_FB) | \ |
| 1117 | BIT(MTK_CLK_SGMII2_TX_250M) | \ |
| 1118 | BIT(MTK_CLK_SGMII2_RX_250M) | \ |
| 1119 | BIT(MTK_CLK_SGMII2_CDR_REF) | \ |
| 1120 | BIT(MTK_CLK_SGMII2_CDR_FB)) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1121 | |
developer | 1bbcf51 | 2022-11-18 16:09:33 +0800 | [diff] [blame] | 1122 | #define MT7988_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_ESW) | \ |
| 1123 | BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ |
| 1124 | BIT(MTK_CLK_GP3) | BIT(MTK_CLK_XGP1) | \ |
| 1125 | BIT(MTK_CLK_XGP2) | BIT(MTK_CLK_XGP3) | \ |
| 1126 | BIT(MTK_CLK_CRYPTO) | \ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1127 | BIT(MTK_CLK_SGMII_TX_250M) | \ |
| 1128 | BIT(MTK_CLK_SGMII_RX_250M) | \ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1129 | BIT(MTK_CLK_SGMII2_TX_250M) | \ |
| 1130 | BIT(MTK_CLK_SGMII2_RX_250M) | \ |
developer | 5cfc67a | 2022-12-29 19:06:51 +0800 | [diff] [blame] | 1131 | BIT(MTK_CLK_ETHWARP_WOCPU2) | \ |
| 1132 | BIT(MTK_CLK_ETHWARP_WOCPU1) | \ |
| 1133 | BIT(MTK_CLK_ETHWARP_WOCPU0) | \ |
| 1134 | BIT(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \ |
| 1135 | BIT(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \ |
| 1136 | BIT(MTK_CLK_TOP_SGM_0_SEL) | \ |
| 1137 | BIT(MTK_CLK_TOP_SGM_1_SEL) | \ |
| 1138 | BIT(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \ |
| 1139 | BIT(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \ |
| 1140 | BIT(MTK_CLK_TOP_ETH_GMII_SEL) | \ |
| 1141 | BIT(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \ |
| 1142 | BIT(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \ |
| 1143 | BIT(MTK_CLK_TOP_ETH_SYS_SEL) | \ |
| 1144 | BIT(MTK_CLK_TOP_ETH_XGMII_SEL) | \ |
| 1145 | BIT(MTK_CLK_TOP_ETH_MII_SEL) | \ |
| 1146 | BIT(MTK_CLK_TOP_NETSYS_SEL) | \ |
| 1147 | BIT(MTK_CLK_TOP_NETSYS_500M_SEL) | \ |
| 1148 | BIT(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \ |
| 1149 | BIT(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \ |
| 1150 | BIT(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \ |
| 1151 | BIT(MTK_CLK_TOP_NETSYS_WARP_SEL)) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1152 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1153 | enum mtk_dev_state { |
| 1154 | MTK_HW_INIT, |
| 1155 | MTK_RESETTING |
| 1156 | }; |
| 1157 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1158 | /* PSE Port Definition */ |
| 1159 | enum mtk_pse_port { |
| 1160 | PSE_ADMA_PORT = 0, |
| 1161 | PSE_GDM1_PORT, |
| 1162 | PSE_GDM2_PORT, |
| 1163 | PSE_PPE0_PORT, |
| 1164 | PSE_PPE1_PORT, |
| 1165 | PSE_QDMA_TX_PORT, |
| 1166 | PSE_QDMA_RX_PORT, |
| 1167 | PSE_DROP_PORT, |
| 1168 | PSE_WDMA0_PORT, |
| 1169 | PSE_WDMA1_PORT, |
| 1170 | PSE_TDMA_PORT, |
| 1171 | PSE_NONE_PORT, |
| 1172 | PSE_PPE2_PORT, |
| 1173 | PSE_WDMA2_PORT, |
| 1174 | PSE_EIP197_PORT, |
| 1175 | PSE_GDM3_PORT, |
| 1176 | PSE_PORT_MAX |
| 1177 | }; |
| 1178 | |
| 1179 | /* GMAC Identifier */ |
| 1180 | enum mtk_gmac_id { |
| 1181 | MTK_GMAC1_ID = 0, |
| 1182 | MTK_GMAC2_ID, |
| 1183 | MTK_GMAC3_ID, |
| 1184 | MTK_GMAC_ID_MAX |
| 1185 | }; |
| 1186 | |
| 1187 | /* GDM Type */ |
| 1188 | enum mtk_gdm_type { |
| 1189 | MTK_GDM_TYPE = 0, |
| 1190 | MTK_XGDM_TYPE, |
| 1191 | MTK_GDM_TYPE_MAX |
| 1192 | }; |
| 1193 | |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 1194 | static inline const char *gdm_type(int type) |
| 1195 | { |
| 1196 | switch (type) { |
| 1197 | case MTK_GDM_TYPE: |
| 1198 | return "gdm"; |
| 1199 | case MTK_XGDM_TYPE: |
| 1200 | return "xgdm"; |
| 1201 | default: |
| 1202 | return "unkown"; |
| 1203 | } |
| 1204 | } |
| 1205 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1206 | /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at |
| 1207 | * by the TX descriptor s |
| 1208 | * @skb: The SKB pointer of the packet being sent |
| 1209 | * @dma_addr0: The base addr of the first segment |
| 1210 | * @dma_len0: The length of the first segment |
| 1211 | * @dma_addr1: The base addr of the second segment |
| 1212 | * @dma_len1: The length of the second segment |
| 1213 | */ |
| 1214 | struct mtk_tx_buf { |
| 1215 | struct sk_buff *skb; |
| 1216 | u32 flags; |
| 1217 | DEFINE_DMA_UNMAP_ADDR(dma_addr0); |
| 1218 | DEFINE_DMA_UNMAP_LEN(dma_len0); |
| 1219 | DEFINE_DMA_UNMAP_ADDR(dma_addr1); |
| 1220 | DEFINE_DMA_UNMAP_LEN(dma_len1); |
| 1221 | }; |
| 1222 | |
| 1223 | /* struct mtk_tx_ring - This struct holds info describing a TX ring |
| 1224 | * @dma: The descriptor ring |
| 1225 | * @buf: The memory pointed at by the ring |
| 1226 | * @phys: The physical addr of tx_buf |
| 1227 | * @next_free: Pointer to the next free descriptor |
| 1228 | * @last_free: Pointer to the last free descriptor |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1229 | * @last_free_ptr: Hardware pointer value of the last free descriptor |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1230 | * @thresh: The threshold of minimum amount of free descriptors |
| 1231 | * @free_count: QDMA uses a linked list. Track how many free descriptors |
| 1232 | * are present |
| 1233 | */ |
| 1234 | struct mtk_tx_ring { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1235 | void *dma; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1236 | struct mtk_tx_buf *buf; |
| 1237 | dma_addr_t phys; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1238 | void *next_free; |
| 1239 | void *last_free; |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1240 | u32 last_free_ptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1241 | u16 thresh; |
| 1242 | atomic_t free_count; |
| 1243 | int dma_size; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1244 | void *dma_pdma; /* For MT7628/88 PDMA handling */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1245 | dma_addr_t phys_pdma; |
| 1246 | int cpu_idx; |
| 1247 | }; |
| 1248 | |
| 1249 | /* PDMA rx ring mode */ |
| 1250 | enum mtk_rx_flags { |
| 1251 | MTK_RX_FLAGS_NORMAL = 0, |
| 1252 | MTK_RX_FLAGS_HWLRO, |
| 1253 | MTK_RX_FLAGS_QDMA, |
| 1254 | }; |
| 1255 | |
| 1256 | /* struct mtk_rx_ring - This struct holds info describing a RX ring |
| 1257 | * @dma: The descriptor ring |
| 1258 | * @data: The memory pointed at by the ring |
| 1259 | * @phys: The physical addr of rx_buf |
| 1260 | * @frag_size: How big can each fragment be |
| 1261 | * @buf_size: The size of each packet buffer |
| 1262 | * @calc_idx: The current head of ring |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 1263 | * @ring_no: The index of ring |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1264 | */ |
| 1265 | struct mtk_rx_ring { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1266 | void *dma; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1267 | u8 **data; |
| 1268 | dma_addr_t phys; |
| 1269 | u16 frag_size; |
| 1270 | u16 buf_size; |
| 1271 | u16 dma_size; |
| 1272 | bool calc_idx_update; |
| 1273 | u16 calc_idx; |
| 1274 | u32 crx_idx_reg; |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 1275 | u32 ring_no; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1276 | }; |
| 1277 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1278 | /* struct mtk_napi - This is the structure holding NAPI-related information, |
| 1279 | * and a mtk_napi struct is binding to one interrupt group |
| 1280 | * @napi: The NAPI struct |
| 1281 | * @rx_ring: Pointer to the memory holding info about the RX ring |
| 1282 | * @irq_grp_idx: The index indicates which interrupt group that this |
| 1283 | * mtk_napi is binding to |
| 1284 | */ |
| 1285 | struct mtk_napi { |
| 1286 | struct napi_struct napi; |
| 1287 | struct mtk_eth *eth; |
| 1288 | struct mtk_rx_ring *rx_ring; |
| 1289 | u32 irq_grp_no; |
| 1290 | }; |
| 1291 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1292 | enum mkt_eth_capabilities { |
| 1293 | MTK_RGMII_BIT = 0, |
| 1294 | MTK_TRGMII_BIT, |
| 1295 | MTK_SGMII_BIT, |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 1296 | MTK_XGMII_BIT, |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1297 | MTK_USXGMII_BIT, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1298 | MTK_ESW_BIT, |
| 1299 | MTK_GEPHY_BIT, |
| 1300 | MTK_MUX_BIT, |
| 1301 | MTK_INFRA_BIT, |
| 1302 | MTK_SHARED_SGMII_BIT, |
| 1303 | MTK_HWLRO_BIT, |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1304 | MTK_RSS_BIT, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1305 | MTK_SHARED_INT_BIT, |
| 1306 | MTK_TRGMII_MT7621_CLK_BIT, |
| 1307 | MTK_QDMA_BIT, |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1308 | MTK_NETSYS_V1_BIT, |
developer | a2bdbd5 | 2021-05-31 19:10:17 +0800 | [diff] [blame] | 1309 | MTK_NETSYS_V2_BIT, |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1310 | MTK_NETSYS_V3_BIT, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1311 | MTK_SOC_MT7628_BIT, |
developer | 545abf0 | 2021-07-15 17:47:01 +0800 | [diff] [blame] | 1312 | MTK_RSTCTRL_PPE1_BIT, |
developer | 37482a4 | 2022-12-26 13:31:13 +0800 | [diff] [blame] | 1313 | MTK_RSTCTRL_PPE2_BIT, |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 1314 | MTK_U3_COPHY_V2_BIT, |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1315 | MTK_8GB_ADDRESSING_BIT, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1316 | |
| 1317 | /* MUX BITS*/ |
| 1318 | MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, |
| 1319 | MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, |
| 1320 | MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 1321 | MTK_ETH_MUX_GMAC2_TO_XGMII_BIT, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1322 | MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, |
| 1323 | MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1324 | MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT, |
| 1325 | MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1326 | |
| 1327 | /* PATH BITS */ |
| 1328 | MTK_ETH_PATH_GMAC1_RGMII_BIT, |
| 1329 | MTK_ETH_PATH_GMAC1_TRGMII_BIT, |
| 1330 | MTK_ETH_PATH_GMAC1_SGMII_BIT, |
| 1331 | MTK_ETH_PATH_GMAC2_RGMII_BIT, |
| 1332 | MTK_ETH_PATH_GMAC2_SGMII_BIT, |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 1333 | MTK_ETH_PATH_GMAC2_XGMII_BIT, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1334 | MTK_ETH_PATH_GMAC2_GEPHY_BIT, |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1335 | MTK_ETH_PATH_GMAC3_SGMII_BIT, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1336 | MTK_ETH_PATH_GDM1_ESW_BIT, |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1337 | MTK_ETH_PATH_GMAC1_USXGMII_BIT, |
| 1338 | MTK_ETH_PATH_GMAC2_USXGMII_BIT, |
| 1339 | MTK_ETH_PATH_GMAC3_USXGMII_BIT, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1340 | }; |
| 1341 | |
| 1342 | /* Supported hardware group on SoCs */ |
developer | 425b23a | 2022-10-12 16:00:41 +0800 | [diff] [blame] | 1343 | #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT) |
| 1344 | #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) |
| 1345 | #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 1346 | #define MTK_XGMII BIT_ULL(MTK_XGMII_BIT) |
developer | 425b23a | 2022-10-12 16:00:41 +0800 | [diff] [blame] | 1347 | #define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT) |
| 1348 | #define MTK_ESW BIT_ULL(MTK_ESW_BIT) |
| 1349 | #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) |
| 1350 | #define MTK_MUX BIT_ULL(MTK_MUX_BIT) |
| 1351 | #define MTK_INFRA BIT_ULL(MTK_INFRA_BIT) |
| 1352 | #define MTK_SHARED_SGMII BIT_ULL(MTK_SHARED_SGMII_BIT) |
| 1353 | #define MTK_HWLRO BIT_ULL(MTK_HWLRO_BIT) |
| 1354 | #define MTK_RSS BIT_ULL(MTK_RSS_BIT) |
| 1355 | #define MTK_SHARED_INT BIT_ULL(MTK_SHARED_INT_BIT) |
| 1356 | #define MTK_TRGMII_MT7621_CLK BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT) |
| 1357 | #define MTK_QDMA BIT_ULL(MTK_QDMA_BIT) |
| 1358 | #define MTK_NETSYS_V1 BIT_ULL(MTK_NETSYS_V1_BIT) |
| 1359 | #define MTK_NETSYS_V2 BIT_ULL(MTK_NETSYS_V2_BIT) |
| 1360 | #define MTK_NETSYS_V3 BIT_ULL(MTK_NETSYS_V3_BIT) |
| 1361 | #define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT) |
| 1362 | #define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT) |
developer | 37482a4 | 2022-12-26 13:31:13 +0800 | [diff] [blame] | 1363 | #define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT) |
developer | 425b23a | 2022-10-12 16:00:41 +0800 | [diff] [blame] | 1364 | #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) |
| 1365 | #define MTK_8GB_ADDRESSING BIT_ULL(MTK_8GB_ADDRESSING_BIT) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1366 | |
| 1367 | #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ |
developer | 425b23a | 2022-10-12 16:00:41 +0800 | [diff] [blame] | 1368 | BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1369 | #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ |
developer | 425b23a | 2022-10-12 16:00:41 +0800 | [diff] [blame] | 1370 | BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1371 | #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ |
developer | 425b23a | 2022-10-12 16:00:41 +0800 | [diff] [blame] | 1372 | BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 1373 | #define MTK_ETH_MUX_GMAC2_TO_XGMII \ |
| 1374 | BIT_ULL(MTK_ETH_MUX_GMAC2_TO_XGMII_BIT) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1375 | #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ |
developer | 425b23a | 2022-10-12 16:00:41 +0800 | [diff] [blame] | 1376 | BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1377 | #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ |
developer | 425b23a | 2022-10-12 16:00:41 +0800 | [diff] [blame] | 1378 | BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1379 | #define MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII \ |
developer | 425b23a | 2022-10-12 16:00:41 +0800 | [diff] [blame] | 1380 | BIT_ULL(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1381 | #define MTK_ETH_MUX_GMAC123_TO_USXGMII \ |
developer | 425b23a | 2022-10-12 16:00:41 +0800 | [diff] [blame] | 1382 | BIT_ULL(MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1383 | |
| 1384 | /* Supported path present on SoCs */ |
developer | 425b23a | 2022-10-12 16:00:41 +0800 | [diff] [blame] | 1385 | #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT) |
| 1386 | #define MTK_ETH_PATH_GMAC1_TRGMII BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT) |
| 1387 | #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT) |
| 1388 | #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) |
| 1389 | #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 1390 | #define MTK_ETH_PATH_GMAC2_XGMII BIT_ULL(MTK_ETH_PATH_GMAC2_XGMII_BIT) |
developer | 425b23a | 2022-10-12 16:00:41 +0800 | [diff] [blame] | 1391 | #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) |
| 1392 | #define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT) |
| 1393 | #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) |
| 1394 | #define MTK_ETH_PATH_GMAC1_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC1_USXGMII_BIT) |
| 1395 | #define MTK_ETH_PATH_GMAC2_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC2_USXGMII_BIT) |
| 1396 | #define MTK_ETH_PATH_GMAC3_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC3_USXGMII_BIT) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1397 | |
| 1398 | #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) |
| 1399 | #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) |
| 1400 | #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) |
| 1401 | #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) |
| 1402 | #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 1403 | #define MTK_GMAC2_XGMII (MTK_ETH_PATH_GMAC2_XGMII | MTK_XGMII) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1404 | #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1405 | #define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1406 | #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1407 | #define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII) |
| 1408 | #define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII) |
| 1409 | #define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1410 | |
| 1411 | /* MUXes present on SoCs */ |
| 1412 | /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ |
| 1413 | #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) |
| 1414 | |
| 1415 | /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ |
| 1416 | #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ |
| 1417 | (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) |
| 1418 | |
| 1419 | /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ |
| 1420 | #define MTK_MUX_U3_GMAC2_TO_QPHY \ |
| 1421 | (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) |
| 1422 | |
| 1423 | /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ |
| 1424 | #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ |
| 1425 | (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ |
| 1426 | MTK_SHARED_SGMII) |
| 1427 | |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 1428 | /* 2: GMAC2 -> XGMII */ |
| 1429 | #define MTK_MUX_GMAC2_TO_XGMII \ |
| 1430 | (MTK_ETH_MUX_GMAC2_TO_XGMII | MTK_MUX | MTK_INFRA) |
| 1431 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1432 | /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ |
| 1433 | #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ |
| 1434 | (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) |
| 1435 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1436 | #define MTK_MUX_GMAC123_TO_GEPHY_SGMII \ |
| 1437 | (MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX) |
| 1438 | |
| 1439 | #define MTK_MUX_GMAC123_TO_USXGMII \ |
| 1440 | (MTK_ETH_MUX_GMAC123_TO_USXGMII | MTK_MUX | MTK_INFRA) |
| 1441 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1442 | #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) |
| 1443 | |
| 1444 | #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ |
| 1445 | MTK_GMAC2_RGMII | MTK_SHARED_INT | \ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1446 | MTK_TRGMII_MT7621_CLK | MTK_QDMA | MTK_NETSYS_V1) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1447 | |
| 1448 | #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ |
| 1449 | MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1450 | MTK_MUX_GDM1_TO_GMAC1_ESW | MTK_NETSYS_V1 | \ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1451 | MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) |
| 1452 | |
| 1453 | #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1454 | MTK_QDMA | MTK_NETSYS_V1) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1455 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1456 | #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628 | MTK_NETSYS_V1) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1457 | |
| 1458 | #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ |
| 1459 | MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ |
| 1460 | MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1461 | MTK_MUX_U3_GMAC2_TO_QPHY | MTK_NETSYS_V1 | \ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1462 | MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) |
| 1463 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1464 | #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ |
| 1465 | MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 1466 | MTK_NETSYS_V2) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1467 | |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 1468 | #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ |
| 1469 | MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ |
| 1470 | MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ |
| 1471 | MTK_NETSYS_V2) |
| 1472 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1473 | #define MT7988_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC3_SGMII | \ |
| 1474 | MTK_MUX_GMAC123_TO_GEPHY_SGMII | MTK_QDMA | \ |
developer | 37482a4 | 2022-12-26 13:31:13 +0800 | [diff] [blame] | 1475 | MTK_NETSYS_V3 | MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | \ |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1476 | MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII | \ |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 1477 | MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII | \ |
| 1478 | MTK_GMAC2_XGMII | MTK_MUX_GMAC2_TO_XGMII | MTK_RSS) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1479 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1480 | struct mtk_tx_dma_desc_info { |
| 1481 | dma_addr_t addr; |
| 1482 | u32 size; |
| 1483 | u16 vlan_tci; |
| 1484 | u16 qid; |
| 1485 | u8 gso:1; |
| 1486 | u8 csum:1; |
| 1487 | u8 vlan:1; |
| 1488 | u8 first:1; |
| 1489 | u8 last:1; |
| 1490 | }; |
| 1491 | |
developer | 68ce74f | 2023-01-03 16:11:57 +0800 | [diff] [blame] | 1492 | struct mtk_reg_map { |
| 1493 | u32 tx_irq_mask; |
| 1494 | u32 tx_irq_status; |
| 1495 | struct { |
| 1496 | u32 rx_ptr; /* rx base pointer */ |
| 1497 | u32 rx_cnt_cfg; /* rx max count configuration */ |
| 1498 | u32 pcrx_ptr; /* rx cpu pointer */ |
| 1499 | u32 glo_cfg; /* global configuration */ |
| 1500 | u32 rst_idx; /* reset index */ |
| 1501 | u32 delay_irq; /* delay interrupt */ |
| 1502 | u32 irq_status; /* interrupt status */ |
| 1503 | u32 irq_mask; /* interrupt mask */ |
| 1504 | u32 int_grp; /* interrupt group1 */ |
| 1505 | u32 int_grp2; /* interrupt group2 */ |
| 1506 | } pdma; |
| 1507 | struct { |
| 1508 | u32 qtx_cfg; /* tx queue configuration */ |
| 1509 | u32 qtx_sch; /* tx queue scheduler configuration */ |
| 1510 | u32 rx_ptr; /* rx base pointer */ |
| 1511 | u32 rx_cnt_cfg; /* rx max count configuration */ |
| 1512 | u32 qcrx_ptr; /* rx cpu pointer */ |
| 1513 | u32 glo_cfg; /* global configuration */ |
| 1514 | u32 rst_idx; /* reset index */ |
| 1515 | u32 delay_irq; /* delay interrupt */ |
| 1516 | u32 fc_th; /* flow control */ |
| 1517 | u32 int_grp; /* interrupt group1 */ |
| 1518 | u32 int_grp2; /* interrupt group2 */ |
| 1519 | u32 hred2; /* interrupt mask */ |
| 1520 | u32 ctx_ptr; /* tx acquire cpu pointer */ |
| 1521 | u32 dtx_ptr; /* tx acquire dma pointer */ |
| 1522 | u32 crx_ptr; /* tx release cpu pointer */ |
| 1523 | u32 drx_ptr; /* tx release dma pointer */ |
| 1524 | u32 fq_head; /* fq head pointer */ |
| 1525 | u32 fq_tail; /* fq tail pointer */ |
| 1526 | u32 fq_count; /* fq free page count */ |
| 1527 | u32 fq_blen; /* fq free page buffer length */ |
| 1528 | u32 tx_sch_rate; /* tx scheduler rate control |
| 1529 | registers */ |
| 1530 | } qdma; |
| 1531 | u32 gdm1_cnt; |
| 1532 | u32 gdma_to_ppe0; |
| 1533 | u32 ppe_base[3]; |
| 1534 | u32 wdma_base[3]; |
| 1535 | }; |
| 1536 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1537 | /* struct mtk_eth_data - This is the structure holding all differences |
| 1538 | * among various plaforms |
developer | 68ce74f | 2023-01-03 16:11:57 +0800 | [diff] [blame] | 1539 | * @reg_map Soc register map. |
| 1540 | * @ana_rgc3: The offset for register ANA_RGC3 related to |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1541 | * sgmiisys syscon |
| 1542 | * @caps Flags shown the extra capability for the SoC |
| 1543 | * @hw_features Flags shown HW features |
| 1544 | * @required_clks Flags shown the bitmap for required clocks on |
| 1545 | * the target SoC |
| 1546 | * @required_pctl A bool value to show whether the SoC requires |
| 1547 | * the extra setup for those pins used by GMAC. |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1548 | * @txd_size Tx DMA descriptor size. |
| 1549 | * @rxd_size Rx DMA descriptor size. |
developer | 68ce74f | 2023-01-03 16:11:57 +0800 | [diff] [blame] | 1550 | * @rx_dma_l4_valid Rx DMA valid register mask. |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1551 | * @dma_max_len Max DMA tx/rx buffer length. |
| 1552 | * @dma_len_offset Tx/Rx DMA length field offset. |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1553 | */ |
| 1554 | struct mtk_soc_data { |
developer | 68ce74f | 2023-01-03 16:11:57 +0800 | [diff] [blame] | 1555 | const struct mtk_reg_map *reg_map; |
| 1556 | u32 ana_rgc3; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1557 | u64 caps; |
developer | 5cfc67a | 2022-12-29 19:06:51 +0800 | [diff] [blame] | 1558 | u64 required_clks; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1559 | bool required_pctl; |
| 1560 | netdev_features_t hw_features; |
| 1561 | bool has_sram; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1562 | struct { |
| 1563 | u32 txd_size; |
| 1564 | u32 rxd_size; |
developer | 68ce74f | 2023-01-03 16:11:57 +0800 | [diff] [blame] | 1565 | u32 rx_dma_l4_valid; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1566 | u32 dma_max_len; |
| 1567 | u32 dma_len_offset; |
| 1568 | } txrx; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1569 | }; |
| 1570 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1571 | /* currently no SoC has more than 3 macs */ |
| 1572 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 1573 | #define MTK_MAX_DEVS 3 |
| 1574 | #else |
| 1575 | #define MTK_MAX_DEVS 2 |
| 1576 | #endif |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1577 | |
| 1578 | #define MTK_SGMII_PHYSPEED_AN BIT(31) |
| 1579 | #define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0) |
| 1580 | #define MTK_SGMII_PHYSPEED_1000 BIT(0) |
| 1581 | #define MTK_SGMII_PHYSPEED_2500 BIT(1) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1582 | #define MTK_SGMII_PHYSPEED_5000 BIT(2) |
| 1583 | #define MTK_SGMII_PHYSPEED_10000 BIT(3) |
developer | f8ac94a | 2021-07-29 16:40:01 +0800 | [diff] [blame] | 1584 | #define MTK_SGMII_PN_SWAP BIT(16) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1585 | #define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x)) |
| 1586 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1587 | /* struct mtk_xgmii - This is the structure holding sgmii/usxgmii regmap and |
| 1588 | * its characteristics |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1589 | * @regmap: The register map pointing at the range used to setup |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1590 | * SGMII/USXGMII modes |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1591 | * @flags: The enum refers to which mode the sgmii wants to run on |
| 1592 | * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap |
| 1593 | */ |
| 1594 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1595 | struct mtk_xgmii { |
| 1596 | struct mtk_eth *eth; |
| 1597 | struct regmap *regmap_sgmii[MTK_MAX_DEVS]; |
| 1598 | struct regmap *regmap_usxgmii[MTK_MAX_DEVS]; |
| 1599 | struct regmap *regmap_pextp[MTK_MAX_DEVS]; |
| 1600 | struct regmap *regmap_pll; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1601 | u32 flags[MTK_MAX_DEVS]; |
| 1602 | u32 ana_rgc3; |
| 1603 | }; |
| 1604 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 1605 | |
| 1606 | /* struct mtk_reset_event - This is the structure holding statistics counters |
| 1607 | * for reset events |
| 1608 | * @count: The counter is used to record the number of events |
| 1609 | */ |
| 1610 | struct mtk_reset_event { |
| 1611 | u32 count[32]; |
| 1612 | }; |
| 1613 | |
developer | a2613e6 | 2022-07-01 18:29:37 +0800 | [diff] [blame] | 1614 | /* struct mtk_phylink_priv - This is the structure holding private data for phylink |
| 1615 | * @desc: Pointer to the memory holding info about the phylink gpio |
| 1616 | * @id: The element is used to record the phy index of phylink |
| 1617 | * @phyaddr: The element is used to record the phy address of phylink |
| 1618 | * @link: The element is used to record the phy link status of phylink |
| 1619 | */ |
| 1620 | struct mtk_phylink_priv { |
| 1621 | struct net_device *dev; |
| 1622 | struct gpio_desc *desc; |
| 1623 | char label[16]; |
| 1624 | int id; |
| 1625 | int phyaddr; |
| 1626 | int link; |
| 1627 | }; |
| 1628 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1629 | /* struct mtk_eth - This is the main datasructure for holding the state |
| 1630 | * of the driver |
| 1631 | * @dev: The device pointer |
developer | 3f28d38 | 2023-03-07 16:06:30 +0800 | [diff] [blame^] | 1632 | * @dma_dev: The device pointer used for dma mapping/alloc |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1633 | * @base: The mapped register i/o base |
| 1634 | * @page_lock: Make sure that register operations are atomic |
| 1635 | * @tx_irq__lock: Make sure that IRQ register operations are atomic |
| 1636 | * @rx_irq__lock: Make sure that IRQ register operations are atomic |
| 1637 | * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a |
| 1638 | * dummy for NAPI to work |
| 1639 | * @netdev: The netdev instances |
| 1640 | * @mac: Each netdev is linked to a physical MAC |
| 1641 | * @irq: The IRQ that we are using |
| 1642 | * @msg_enable: Ethtool msg level |
| 1643 | * @ethsys: The register map pointing at the range used to setup |
| 1644 | * MII modes |
| 1645 | * @infra: The register map pointing at the range used to setup |
| 1646 | * SGMII and GePHY path |
| 1647 | * @pctl: The register map pointing at the range used to setup |
| 1648 | * GMAC port drive/slew values |
| 1649 | * @dma_refcnt: track how many netdevs are using the DMA engine |
| 1650 | * @tx_ring: Pointer to the memory holding info about the TX ring |
| 1651 | * @rx_ring: Pointer to the memory holding info about the RX ring |
| 1652 | * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring |
| 1653 | * @tx_napi: The TX NAPI struct |
| 1654 | * @rx_napi: The RX NAPI struct |
| 1655 | * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring |
| 1656 | * @phy_scratch_ring: physical address of scratch_ring |
| 1657 | * @scratch_head: The scratch memory that scratch_ring points to. |
| 1658 | * @clks: clock array for all clocks required |
| 1659 | * @mii_bus: If there is a bus we need to create an instance for it |
| 1660 | * @pending_work: The workqueue used to reset the dma ring |
| 1661 | * @state: Initialization and runtime state of the device |
| 1662 | * @soc: Holding specific data among vaious SoCs |
| 1663 | */ |
| 1664 | |
| 1665 | struct mtk_eth { |
| 1666 | struct device *dev; |
developer | 3f28d38 | 2023-03-07 16:06:30 +0800 | [diff] [blame^] | 1667 | struct device *dma_dev; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1668 | void __iomem *base; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1669 | void __iomem *sram_base; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1670 | spinlock_t page_lock; |
| 1671 | spinlock_t tx_irq_lock; |
| 1672 | spinlock_t rx_irq_lock; |
| 1673 | struct net_device dummy_dev; |
| 1674 | struct net_device *netdev[MTK_MAX_DEVS]; |
| 1675 | struct mtk_mac *mac[MTK_MAX_DEVS]; |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1676 | int irq[MTK_MAX_IRQ_NUM]; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1677 | u32 msg_enable; |
| 1678 | unsigned long sysclk; |
| 1679 | struct regmap *ethsys; |
| 1680 | struct regmap *infra; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1681 | struct regmap *toprgu; |
| 1682 | struct mtk_xgmii *xgmii; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1683 | struct regmap *pctl; |
| 1684 | bool hwlro; |
| 1685 | refcount_t dma_refcnt; |
| 1686 | struct mtk_tx_ring tx_ring; |
| 1687 | struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; |
| 1688 | struct mtk_rx_ring rx_ring_qdma; |
| 1689 | struct napi_struct tx_napi; |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1690 | struct mtk_napi rx_napi[MTK_RX_NAPI_NUM]; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1691 | void *scratch_ring; |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 1692 | struct mtk_reset_event reset_event; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1693 | dma_addr_t phy_scratch_ring; |
| 1694 | void *scratch_head; |
| 1695 | struct clk *clks[MTK_CLK_MAX]; |
| 1696 | |
| 1697 | struct mii_bus *mii_bus; |
| 1698 | struct work_struct pending_work; |
| 1699 | unsigned long state; |
| 1700 | |
| 1701 | const struct mtk_soc_data *soc; |
| 1702 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1703 | u32 rx_dma_l4_valid; |
| 1704 | int ip_align; |
developer | d82e837 | 2022-02-09 15:00:09 +0800 | [diff] [blame] | 1705 | spinlock_t syscfg0_lock; |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 1706 | struct timer_list mtk_dma_monitor_timer; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1707 | }; |
| 1708 | |
| 1709 | /* struct mtk_mac - the structure that holds the info about the MACs of the |
| 1710 | * SoC |
| 1711 | * @id: The number of the MAC |
| 1712 | * @interface: Interface mode kept for detecting change in hw settings |
| 1713 | * @of_node: Our devicetree node |
| 1714 | * @hw: Backpointer to our main datastruture |
| 1715 | * @hw_stats: Packet statistics counter |
| 1716 | */ |
| 1717 | struct mtk_mac { |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 1718 | unsigned int id; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1719 | phy_interface_t interface; |
| 1720 | unsigned int mode; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1721 | unsigned int type; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1722 | int speed; |
| 1723 | struct device_node *of_node; |
| 1724 | struct phylink *phylink; |
| 1725 | struct phylink_config phylink_config; |
developer | a2613e6 | 2022-07-01 18:29:37 +0800 | [diff] [blame] | 1726 | struct mtk_phylink_priv phylink_priv; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1727 | struct mtk_eth *hw; |
| 1728 | struct mtk_hw_stats *hw_stats; |
| 1729 | __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; |
| 1730 | int hwlro_ip_cnt; |
developer | 9b72593 | 2022-11-24 16:25:56 +0800 | [diff] [blame] | 1731 | bool tx_lpi_enabled; |
| 1732 | u32 tx_lpi_timer; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1733 | }; |
| 1734 | |
| 1735 | /* the struct describing the SoC. these are declared in the soc_xyz.c files */ |
developer | 7cd7e5e | 2022-11-17 13:57:32 +0800 | [diff] [blame] | 1736 | extern struct mtk_eth *g_eth; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1737 | extern const struct of_device_id of_mtk_match[]; |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 1738 | extern u32 mtk_hwlro_stats_ebl; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1739 | |
| 1740 | /* read the hardware status register */ |
| 1741 | void mtk_stats_update_mac(struct mtk_mac *mac); |
| 1742 | |
| 1743 | void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); |
| 1744 | u32 mtk_r32(struct mtk_eth *eth, unsigned reg); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 1745 | u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1746 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1747 | int mtk_sgmii_init(struct mtk_xgmii *ss, struct device_node *np, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1748 | u32 ana_rgc3); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1749 | int mtk_sgmii_setup_mode_an(struct mtk_xgmii *ss, unsigned int mac_id); |
| 1750 | int mtk_sgmii_setup_mode_force(struct mtk_xgmii *ss, unsigned int mac_id, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1751 | const struct phylink_link_state *state); |
| 1752 | void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1753 | void mtk_sgmii_setup_phya_gen2(struct mtk_xgmii *ss, int mac_id); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1754 | |
| 1755 | int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 1756 | int mtk_gmac_xgmii_path_setup(struct mtk_eth *eth, int mac_id); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1757 | int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); |
| 1758 | int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1759 | int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id); |
developer | dca0fde | 2022-12-14 11:40:35 +0800 | [diff] [blame] | 1760 | void mtk_gdm_config(struct mtk_eth *eth, u32 id, u32 config); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 1761 | void ethsys_reset(struct mtk_eth *eth, u32 reset_bits); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1762 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1763 | int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id); |
| 1764 | int mtk_usxgmii_init(struct mtk_xgmii *ss, struct device_node *r); |
| 1765 | int mtk_xfi_pextp_init(struct mtk_xgmii *ss, struct device_node *r); |
| 1766 | int mtk_xfi_pll_init(struct mtk_xgmii *ss, struct device_node *r); |
| 1767 | int mtk_toprgu_init(struct mtk_eth *eth, struct device_node *r); |
| 1768 | int mtk_xfi_pll_enable(struct mtk_xgmii *ss); |
| 1769 | int mtk_usxgmii_setup_mode_an(struct mtk_xgmii *ss, int mac_id, |
| 1770 | int max_speed); |
| 1771 | int mtk_usxgmii_setup_mode_force(struct mtk_xgmii *ss, int mac_id, |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 1772 | const struct phylink_link_state *state); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1773 | void mtk_usxgmii_setup_phya_an_10000(struct mtk_xgmii *ss, int mac_id); |
| 1774 | void mtk_usxgmii_reset(struct mtk_xgmii *ss, int mac_id); |
developer | 0baa696 | 2023-01-31 14:25:23 +0800 | [diff] [blame] | 1775 | int mtk_dump_usxgmii(struct regmap *pmap, char *name, u32 offset, u32 range); |
developer | 3f28d38 | 2023-03-07 16:06:30 +0800 | [diff] [blame^] | 1776 | |
| 1777 | void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1778 | #endif /* MTK_ETH_H */ |