[][kernel][common][eth][Add MDC divider support]
[Description]
Add MDC divider support.
User can specify MDC speed by adding mdc-max-frequency property
to the mdio nodes.
================================================================
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
mdc-max-frequency = <10500000>;
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
...
};
...
};
================================================================
Example: PHY device support 10.5MHz Maximum MDC clock.
User just need to declare this information in the DTS, driver will
find out a proper MDC divider(25MHz/3=8.33MHz) and setup
controller automatically.
If without this patch, MDC always running on 2.5MHz.
[Release-log]
N/A
Change-Id: If9171730373692243f02ceb9077bb496a774c8d0
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6756759
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index a961042..d1e1d65 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -602,6 +602,11 @@
#define RX_DMA_GET_AGG_CNT_V2(_x) (((_x) >> 16) & 0xff)
#define RX_DMA_GET_TOPS_CRSN(_x) (((_x) >> 24) & 0xff)
+/* PHY Polling and SMI Master Control registers */
+#define MTK_PPSC 0x10000
+#define PPSC_MDC_CFG GENMASK(29, 24)
+#define PPSC_MDC_TURBO BIT(20)
+
/* PHY Indirect Access Control registers */
#define MTK_PHY_IAC 0x10004
#define PHY_IAC_ACCESS BIT(31)
@@ -615,7 +620,12 @@
#define PHY_IAC_REG_SHIFT 25
#define PHY_IAC_TIMEOUT HZ
+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
+#define MTK_MAC_MISC 0x10010
+#else
#define MTK_MAC_MISC 0x1000c
+#endif
+#define MISC_MDC_TURBO BIT(4)
#define MTK_MUX_TO_ESW BIT(0)
/* XMAC status registers */