blob: 3922064d056b9cda935a8721138b6c30f4267f85 [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +08001/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7 */
8
9#ifndef MTK_ETH_H
10#define MTK_ETH_H
11
12#include <linux/dma-mapping.h>
13#include <linux/netdevice.h>
14#include <linux/of_net.h>
15#include <linux/u64_stats_sync.h>
16#include <linux/refcount.h>
17#include <linux/phylink.h>
18
19#define MTK_QDMA_PAGE_SIZE 2048
20#define MTK_MAX_RX_LENGTH 1536
21#define MTK_DMA_SIZE 2048
22#define MTK_NAPI_WEIGHT 256
23#define MTK_MAC_COUNT 2
24#define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
25#define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
26#define MTK_DMA_DUMMY_DESC 0xffffffff
27#define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \
28 NETIF_MSG_PROBE | \
29 NETIF_MSG_LINK | \
30 NETIF_MSG_TIMER | \
31 NETIF_MSG_IFDOWN | \
32 NETIF_MSG_IFUP | \
33 NETIF_MSG_RX_ERR | \
34 NETIF_MSG_TX_ERR)
35#define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \
36 NETIF_F_RXCSUM | \
37 NETIF_F_HW_VLAN_CTAG_TX | \
developerfd40db22021-04-29 10:08:25 +080038 NETIF_F_SG | NETIF_F_TSO | \
39 NETIF_F_TSO6 | \
40 NETIF_F_IPV6_CSUM)
41#define MTK_SET_FEATURES (NETIF_F_LRO | \
42 NETIF_F_HW_VLAN_CTAG_RX)
43#define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM)
44#define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
45
developerfd40db22021-04-29 10:08:25 +080046#define MTK_HW_LRO_DMA_SIZE 8
47
48#define MTK_MAX_LRO_RX_LENGTH (4096 * 3)
49#define MTK_MAX_LRO_IP_CNT 2
50#define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */
51#define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */
52#define MTK_HW_LRO_AGG_TIME 10 /* 200us */
53#define MTK_HW_LRO_AGE_TIME 50 /* 1ms */
54#define MTK_HW_LRO_MAX_AGG_CNT 64
55#define MTK_HW_LRO_BW_THRE 3000
56#define MTK_HW_LRO_REPLACE_DELTA 1000
57#define MTK_HW_LRO_SDL_REMAIN_ROOM 1522
58
59/* Frame Engine Global Reset Register */
60#define MTK_RST_GL 0x04
61#define RST_GL_PSE BIT(0)
62
63/* Frame Engine Interrupt Status Register */
developer77f3fd42021-10-05 15:16:05 +080064#define MTK_INT_STATUS 0x08
65#define MTK_INT_STATUS2 0x28
developerfd40db22021-04-29 10:08:25 +080066#define MTK_GDM1_AF BIT(28)
67#define MTK_GDM2_AF BIT(29)
68
69/* PDMA HW LRO Alter Flow Timer Register */
70#define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
71
72/* Frame Engine Interrupt Grouping Register */
73#define MTK_FE_INT_GRP 0x20
74
developer77d03a72021-06-06 00:06:00 +080075/* Frame Engine LRO auto-learn table info */
76#define MTK_FE_ALT_CF8 0x300
77#define MTK_FE_ALT_SGL_CFC 0x304
78#define MTK_FE_ALT_SEQ_CFC 0x308
79
developerfd40db22021-04-29 10:08:25 +080080/* CDMP Ingress Control Register */
81#define MTK_CDMQ_IG_CTRL 0x1400
82#define MTK_CDMQ_STAG_EN BIT(0)
83
84/* CDMP Ingress Control Register */
85#define MTK_CDMP_IG_CTRL 0x400
86#define MTK_CDMP_STAG_EN BIT(0)
87
88/* CDMP Exgress Control Register */
89#define MTK_CDMP_EG_CTRL 0x404
90
91/* GDM Exgress Control Register */
92#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
93#define MTK_GDMA_SPECIAL_TAG BIT(24)
94#define MTK_GDMA_ICS_EN BIT(22)
95#define MTK_GDMA_TCS_EN BIT(21)
96#define MTK_GDMA_UCS_EN BIT(20)
97#define MTK_GDMA_TO_PDMA 0x0
98#define MTK_GDMA_DROP_ALL 0x7777
99
100/* Unicast Filter MAC Address Register - Low */
101#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
102
103/* Unicast Filter MAC Address Register - High */
104#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
105
106/* Internal SRAM offset */
107#define MTK_ETH_SRAM_OFFSET 0x40000
108
109/* FE global misc reg*/
110#define MTK_FE_GLO_MISC 0x124
111
developerfef9efd2021-06-16 18:28:09 +0800112/* PSE Free Queue Flow Control */
113#define PSE_FQFC_CFG1 0x100
114#define PSE_FQFC_CFG2 0x104
developer81bcad32021-07-15 14:14:38 +0800115#define PSE_DROP_CFG 0x108
developerfef9efd2021-06-16 18:28:09 +0800116
developerfd40db22021-04-29 10:08:25 +0800117/* PSE Input Queue Reservation Register*/
118#define PSE_IQ_REV(x) (0x140 + ((x - 1) * 0x4))
119
120/* PSE Output Queue Threshold Register*/
121#define PSE_OQ_TH(x) (0x160 + ((x - 1) * 0x4))
122
developerfef9efd2021-06-16 18:28:09 +0800123/* GDM and CDM Threshold */
124#define MTK_GDM2_THRES 0x1530
125#define MTK_CDMW0_THRES 0x164c
126#define MTK_CDMW1_THRES 0x1650
127#define MTK_CDME0_THRES 0x1654
128#define MTK_CDME1_THRES 0x1658
129#define MTK_CDMM_THRES 0x165c
130
developerfd40db22021-04-29 10:08:25 +0800131#define MTK_PDMA_V2 BIT(4)
developerfd40db22021-04-29 10:08:25 +0800132
developera2bdbd52021-05-31 19:10:17 +0800133#if defined(CONFIG_MEDIATEK_NETSYS_V2)
developerfd40db22021-04-29 10:08:25 +0800134#define PDMA_BASE 0x6000
developerfd40db22021-04-29 10:08:25 +0800135#define QDMA_BASE 0x4400
136#else
137#define PDMA_BASE 0x0800
138#define QDMA_BASE 0x1800
139#endif
140/* PDMA RX Base Pointer Register */
141#define MTK_PRX_BASE_PTR0 (PDMA_BASE + 0x100)
142#define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10))
143
144/* PDMA RX Maximum Count Register */
145#define MTK_PRX_MAX_CNT0 (MTK_PRX_BASE_PTR0 + 0x04)
146#define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10))
147
148/* PDMA RX CPU Pointer Register */
149#define MTK_PRX_CRX_IDX0 (MTK_PRX_BASE_PTR0 + 0x08)
150#define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10))
151
developer77f3fd42021-10-05 15:16:05 +0800152/* PDMA RX DMA Pointer Register */
153#define MTK_PRX_DRX_IDX0 (MTK_PRX_BASE_PTR0 + 0x0c)
154#define MTK_PRX_DRX_IDX_CFG(x) (MTK_PRX_DRX_IDX0 + (x * 0x10))
155
developerfd40db22021-04-29 10:08:25 +0800156/* PDMA HW LRO Control Registers */
developer77d03a72021-06-06 00:06:00 +0800157#define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n)))
158#if defined(CONFIG_MEDIATEK_NETSYS_V2)
159#define MTK_MAX_RX_RING_NUM (8)
160#define MTK_HW_LRO_RING_NUM (4)
161#define IS_HW_LRO_RING(ring_no) (((ring_no) > 3) && ((ring_no) < 8))
162#define MTK_PDMA_LRO_CTRL_DW0 (PDMA_BASE + 0x408)
163#define MTK_LRO_ALT_SCORE_DELTA (PDMA_BASE + 0x41c)
164#define MTK_LRO_RX_RING0_CTRL_DW1 (PDMA_BASE + 0x438)
165#define MTK_LRO_RX_RING0_CTRL_DW2 (PDMA_BASE + 0x43c)
166#define MTK_LRO_RX_RING0_CTRL_DW3 (PDMA_BASE + 0x440)
167#define MTK_L3_CKS_UPD_EN BIT(19)
168#define MTK_LRO_CRSN_BNW BIT(22)
169#define MTK_LRO_RING_RELINGUISH_REQ (0xf << 24)
170#define MTK_LRO_RING_RELINGUISH_DONE (0xf << 28)
171#else
172#define MTK_MAX_RX_RING_NUM (4)
173#define MTK_HW_LRO_RING_NUM (3)
174#define IS_HW_LRO_RING(ring_no) (((ring_no) > 0) && ((ring_no) < 4))
175#define MTK_PDMA_LRO_CTRL_DW0 (PDMA_BASE + 0x180)
176#define MTK_LRO_ALT_SCORE_DELTA (PDMA_BASE + 0x24c)
177#define MTK_LRO_RX_RING0_CTRL_DW1 (PDMA_BASE + 0x328)
178#define MTK_LRO_RX_RING0_CTRL_DW2 (PDMA_BASE + 0x32c)
179#define MTK_LRO_RX_RING0_CTRL_DW3 (PDMA_BASE + 0x330)
180#define MTK_LRO_CRSN_BNW BIT(6)
developerfd40db22021-04-29 10:08:25 +0800181#define MTK_L3_CKS_UPD_EN BIT(7)
developer77d03a72021-06-06 00:06:00 +0800182#define MTK_LRO_RING_RELINGUISH_REQ (0x7 << 26)
183#define MTK_LRO_RING_RELINGUISH_DONE (0x7 << 29)
184#endif
185
186#define IS_NORMAL_RING(ring_no) ((ring_no) == 0)
187#define MTK_LRO_EN BIT(0)
developer18f46a82021-07-20 21:08:21 +0800188#define MTK_NON_LRO_MULTI_EN BIT(2)
189#define MTK_LRO_DLY_INT_EN BIT(5)
developerfd40db22021-04-29 10:08:25 +0800190#define MTK_LRO_ALT_PKT_CNT_MODE BIT(21)
developer77d03a72021-06-06 00:06:00 +0800191#define MTK_LRO_L4_CTRL_PSH_EN BIT(23)
192#define MTK_CTRL_DW0_SDL_OFFSET (3)
193#define MTK_CTRL_DW0_SDL_MASK BITS(3, 18)
developerfd40db22021-04-29 10:08:25 +0800194
195#define MTK_PDMA_LRO_CTRL_DW1 (MTK_PDMA_LRO_CTRL_DW0 + 0x04)
196#define MTK_PDMA_LRO_CTRL_DW2 (MTK_PDMA_LRO_CTRL_DW0 + 0x08)
197#define MTK_PDMA_LRO_CTRL_DW3 (MTK_PDMA_LRO_CTRL_DW0 + 0x0c)
198#define MTK_ADMA_MODE BIT(15)
199#define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
200
developer18f46a82021-07-20 21:08:21 +0800201/* PDMA RSS Control Registers */
202#if defined(CONFIG_MEDIATEK_NETSYS_V2)
203#define MTK_PDMA_RSS_GLO_CFG (PDMA_BASE + 0x800)
204#define MTK_RX_NAPI_NUM (2)
205#define MTK_MAX_IRQ_NUM (4)
206#else
207#define MTK_PDMA_RSS_GLO_CFG 0x3000
208#define MTK_RX_NAPI_NUM (1)
209#define MTK_MAX_IRQ_NUM (3)
210#endif
211#define MTK_RSS_RING1 (1)
212#define MTK_RSS_EN BIT(0)
213#define MTK_RSS_CFG_REQ BIT(2)
214#define MTK_RSS_IPV6_STATIC_HASH (0x7 << 8)
215#define MTK_RSS_IPV4_STATIC_HASH (0x7 << 12)
216#define MTK_RSS_INDR_TABLE_DW0 (MTK_PDMA_RSS_GLO_CFG + 0x50)
217#define MTK_RSS_INDR_TABLE_DW1 (MTK_PDMA_RSS_GLO_CFG + 0x54)
218#define MTK_RSS_INDR_TABLE_DW2 (MTK_PDMA_RSS_GLO_CFG + 0x58)
219#define MTK_RSS_INDR_TABLE_DW3 (MTK_PDMA_RSS_GLO_CFG + 0x5C)
220#define MTK_RSS_INDR_TABLE_DW4 (MTK_PDMA_RSS_GLO_CFG + 0x60)
221#define MTK_RSS_INDR_TABLE_DW5 (MTK_PDMA_RSS_GLO_CFG + 0x64)
222#define MTK_RSS_INDR_TABLE_DW6 (MTK_PDMA_RSS_GLO_CFG + 0x68)
223#define MTK_RSS_INDR_TABLE_DW7 (MTK_PDMA_RSS_GLO_CFG + 0x6C)
224#define MTK_RSS_INDR_TABLE_SIZE4 0x44444444
225
developerfd40db22021-04-29 10:08:25 +0800226/* PDMA Global Configuration Register */
227#define MTK_PDMA_GLO_CFG (PDMA_BASE + 0x204)
developer77d03a72021-06-06 00:06:00 +0800228#define MTK_RX_DMA_LRO_EN BIT(8)
developerfd40db22021-04-29 10:08:25 +0800229#define MTK_MULTI_EN BIT(10)
230#define MTK_PDMA_SIZE_8DWORDS (1 << 4)
231
developer77d03a72021-06-06 00:06:00 +0800232/* PDMA Global Configuration Register */
233#define MTK_PDMA_RX_CFG (PDMA_BASE + 0x210)
234#define MTK_PDMA_LRO_SDL (0x3000)
235#define MTK_RX_CFG_SDL_OFFSET (16)
236
developerfd40db22021-04-29 10:08:25 +0800237/* PDMA Reset Index Register */
238#define MTK_PDMA_RST_IDX (PDMA_BASE + 0x208)
239#define MTK_PST_DRX_IDX0 BIT(16)
240#define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x))
241
242/* PDMA Delay Interrupt Register */
243#define MTK_PDMA_DELAY_INT (PDMA_BASE + 0x20c)
244#define MTK_PDMA_DELAY_RX_EN BIT(15)
245#define MTK_PDMA_DELAY_RX_PINT 4
246#define MTK_PDMA_DELAY_RX_PINT_SHIFT 8
247#define MTK_PDMA_DELAY_RX_PTIME 4
248#define MTK_PDMA_DELAY_RX_DELAY \
249 (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \
250 (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT))
251
252/* PDMA Interrupt Status Register */
253#define MTK_PDMA_INT_STATUS (PDMA_BASE + 0x220)
254
255/* PDMA Interrupt Mask Register */
256#define MTK_PDMA_INT_MASK (PDMA_BASE + 0x228)
257
developerfd40db22021-04-29 10:08:25 +0800258/* PDMA Interrupt grouping registers */
259#define MTK_PDMA_INT_GRP1 (PDMA_BASE + 0x250)
260#define MTK_PDMA_INT_GRP2 (PDMA_BASE + 0x254)
developer18f46a82021-07-20 21:08:21 +0800261#if defined(CONFIG_MEDIATEK_NETSYS_V2)
262#define MTK_PDMA_INT_GRP3 (PDMA_BASE + 0x258)
263#else
264#define MTK_PDMA_INT_GRP3 (PDMA_BASE + 0x22c)
265#endif
266#define MTK_LRO_RX1_DLY_INT 0xa70
267#define MTK_MAX_DELAY_INT 0x8f0f8f0f
developerfd40db22021-04-29 10:08:25 +0800268
269/* PDMA HW LRO IP Setting Registers */
developer77d03a72021-06-06 00:06:00 +0800270#if defined(CONFIG_MEDIATEK_NETSYS_V2)
271#define MTK_LRO_RX_RING0_DIP_DW0 (PDMA_BASE + 0x414)
272#else
developerfd40db22021-04-29 10:08:25 +0800273#define MTK_LRO_RX_RING0_DIP_DW0 (PDMA_BASE + 0x304)
developer77d03a72021-06-06 00:06:00 +0800274#endif
developerfd40db22021-04-29 10:08:25 +0800275#define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
276#define MTK_RING_MYIP_VLD BIT(9)
277
developer77d03a72021-06-06 00:06:00 +0800278/* PDMA HW LRO ALT Debug Registers */
279#define MTK_LRO_ALT_DBG (PDMA_BASE + 0x440)
280#define MTK_LRO_ALT_INDEX_OFFSET (8)
281
282/* PDMA HW LRO ALT Data Registers */
283#define MTK_LRO_ALT_DBG_DATA (PDMA_BASE + 0x444)
284
developerfd40db22021-04-29 10:08:25 +0800285/* PDMA HW LRO Ring Control Registers */
developerfd40db22021-04-29 10:08:25 +0800286#define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
287#define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
288#define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
289#define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
290#define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
developer18f46a82021-07-20 21:08:21 +0800291#define MTK_RING_PSE_MODE (1 << 6)
developerfd40db22021-04-29 10:08:25 +0800292#define MTK_RING_AUTO_LERAN_MODE (3 << 6)
293#define MTK_RING_VLD BIT(8)
294#define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
295#define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
296#define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
297
developer77d03a72021-06-06 00:06:00 +0800298/* LRO_RX_RING_CTRL_DW masks */
299#define MTK_LRO_RING_AGG_TIME_MASK BITS(10, 25)
300#define MTK_LRO_RING_AGG_CNT_L_MASK BITS(26, 31)
301#define MTK_LRO_RING_AGG_CNT_H_MASK BITS(0, 1)
302#define MTK_LRO_RING_AGE_TIME_L_MASK BITS(22, 31)
303#define MTK_LRO_RING_AGE_TIME_H_MASK BITS(0, 5)
304
305/* LRO_RX_RING_CTRL_DW0 offsets */
306#define MTK_RX_IPV6_FORCE_OFFSET (0)
307#define MTK_RX_IPV4_FORCE_OFFSET (1)
308
309/* LRO_RX_RING_CTRL_DW1 offsets */
310#define MTK_LRO_RING_AGE_TIME_L_OFFSET (22)
311
312/* LRO_RX_RING_CTRL_DW2 offsets */
313#define MTK_LRO_RING_AGE_TIME_H_OFFSET (0)
314#define MTK_RX_MODE_OFFSET (6)
315#define MTK_RX_PORT_VALID_OFFSET (8)
316#define MTK_RX_MYIP_VALID_OFFSET (9)
317#define MTK_LRO_RING_AGG_TIME_OFFSET (10)
318#define MTK_LRO_RING_AGG_CNT_L_OFFSET (26)
319
320/* LRO_RX_RING_CTRL_DW3 offsets */
321#define MTK_LRO_RING_AGG_CNT_H_OFFSET (0)
322
323/* LRO_RX_RING_STP_DTP_DW offsets */
324#define MTK_RX_TCP_DEST_PORT_OFFSET (0)
325#define MTK_RX_TCP_SRC_PORT_OFFSET (16)
326
developerfd40db22021-04-29 10:08:25 +0800327/* QDMA TX Queue Configuration Registers */
328#define MTK_QTX_CFG(x) (QDMA_BASE + (x * 0x10))
329#define QDMA_RES_THRES 4
330
331/* QDMA TX Queue Scheduler Registers */
332#define MTK_QTX_SCH(x) (QDMA_BASE + 4 + (x * 0x10))
333
334/* QDMA RX Base Pointer Register */
335#define MTK_QRX_BASE_PTR0 (QDMA_BASE + 0x100)
336#define MTK_QRX_BASE_PTR_CFG(x) (MTK_QRX_BASE_PTR0 + ((x) * 0x10))
337
338/* QDMA RX Maximum Count Register */
339#define MTK_QRX_MAX_CNT0 (QDMA_BASE + 0x104)
340#define MTK_QRX_MAX_CNT_CFG(x) (MTK_QRX_MAX_CNT0 + ((x) * 0x10))
341
342/* QDMA RX CPU Pointer Register */
343#define MTK_QRX_CRX_IDX0 (QDMA_BASE + 0x108)
344#define MTK_QRX_CRX_IDX_CFG(x) (MTK_QRX_CRX_IDX0 + ((x) * 0x10))
345
346/* QDMA RX DMA Pointer Register */
347#define MTK_QRX_DRX_IDX0 (QDMA_BASE + 0x10c)
348
349/* QDMA Global Configuration Register */
350#define MTK_QDMA_GLO_CFG (QDMA_BASE + 0x204)
351#define MTK_RX_2B_OFFSET BIT(31)
352#define MTK_RX_BT_32DWORDS (3 << 11)
353#define MTK_NDP_CO_PRO BIT(10)
354#define MTK_TX_WB_DDONE BIT(6)
355#define MTK_DMA_SIZE_16DWORDS (2 << 4)
356#define MTK_DMA_SIZE_32DWORDS (3 << 4)
357#define MTK_RX_DMA_BUSY BIT(3)
358#define MTK_TX_DMA_BUSY BIT(1)
359#define MTK_RX_DMA_EN BIT(2)
360#define MTK_TX_DMA_EN BIT(0)
361#define MTK_DMA_BUSY_TIMEOUT HZ
362
363/* QDMA V2 Global Configuration Register */
364#define MTK_CHK_DDONE_EN BIT(28)
365#define MTK_DMAD_WR_WDONE BIT(26)
366#define MTK_WCOMP_EN BIT(24)
367#define MTK_RESV_BUF (0x40 << 16)
368#define MTK_MUTLI_CNT (0x4 << 12)
369
370/* QDMA Reset Index Register */
371#define MTK_QDMA_RST_IDX (QDMA_BASE + 0x208)
372
373/* QDMA Delay Interrupt Register */
374#define MTK_QDMA_DELAY_INT (QDMA_BASE + 0x20c)
375
376/* QDMA Flow Control Register */
377#define MTK_QDMA_FC_THRES (QDMA_BASE + 0x210)
378#define FC_THRES_DROP_MODE BIT(20)
379#define FC_THRES_DROP_EN (7 << 16)
380#define FC_THRES_MIN 0x4444
381
382/* QDMA Interrupt Status Register */
383#define MTK_QDMA_INT_STATUS (QDMA_BASE + 0x218)
developera2bdbd52021-05-31 19:10:17 +0800384#if defined(CONFIG_MEDIATEK_NETSYS_V2)
developer18f46a82021-07-20 21:08:21 +0800385#define MTK_RX_DONE_INT(ring_no) \
386 ((ring_no)? BIT(16 + (ring_no)) : BIT(14))
developerfd40db22021-04-29 10:08:25 +0800387#else
developer18f46a82021-07-20 21:08:21 +0800388#define MTK_RX_DONE_INT(ring_no) \
389 ((ring_no)? BIT(24 + (ring_no)) : BIT(30))
developerfd40db22021-04-29 10:08:25 +0800390#endif
391#define MTK_RX_DONE_INT3 BIT(19)
392#define MTK_RX_DONE_INT2 BIT(18)
393#define MTK_RX_DONE_INT1 BIT(17)
394#define MTK_RX_DONE_INT0 BIT(16)
395#define MTK_TX_DONE_INT3 BIT(3)
396#define MTK_TX_DONE_INT2 BIT(2)
397#define MTK_TX_DONE_INT1 BIT(1)
398#define MTK_TX_DONE_INT0 BIT(0)
developerfd40db22021-04-29 10:08:25 +0800399#define MTK_TX_DONE_DLY BIT(28)
400#define MTK_TX_DONE_INT MTK_TX_DONE_DLY
401
402/* QDMA Interrupt grouping registers */
403#define MTK_QDMA_INT_GRP1 (QDMA_BASE + 0x220)
404#define MTK_QDMA_INT_GRP2 (QDMA_BASE + 0x224)
405#define MTK_RLS_DONE_INT BIT(0)
406
407/* QDMA Interrupt Status Register */
408#define MTK_QDMA_INT_MASK (QDMA_BASE + 0x21c)
409
410/* QDMA Interrupt Mask Register */
411#define MTK_QDMA_HRED2 (QDMA_BASE + 0x244)
412
413/* QDMA TX Forward CPU Pointer Register */
414#define MTK_QTX_CTX_PTR (QDMA_BASE +0x300)
415
416/* QDMA TX Forward DMA Pointer Register */
417#define MTK_QTX_DTX_PTR (QDMA_BASE +0x304)
418
419/* QDMA TX Release CPU Pointer Register */
420#define MTK_QTX_CRX_PTR (QDMA_BASE +0x310)
421
422/* QDMA TX Release DMA Pointer Register */
423#define MTK_QTX_DRX_PTR (QDMA_BASE +0x314)
424
425/* QDMA FQ Head Pointer Register */
426#define MTK_QDMA_FQ_HEAD (QDMA_BASE +0x320)
427
428/* QDMA FQ Head Pointer Register */
429#define MTK_QDMA_FQ_TAIL (QDMA_BASE +0x324)
430
431/* QDMA FQ Free Page Counter Register */
432#define MTK_QDMA_FQ_CNT (QDMA_BASE +0x328)
433
434/* QDMA FQ Free Page Buffer Length Register */
435#define MTK_QDMA_FQ_BLEN (QDMA_BASE +0x32c)
436
437/* GMA1 Received Good Byte Count Register */
438#if defined(CONFIG_MEDIATEK_NETSYS_V2)
439#define MTK_GDM1_TX_GBCNT 0x1C00
440#else
441#define MTK_GDM1_TX_GBCNT 0x2400
442#endif
443#define MTK_STAT_OFFSET 0x40
444
445/* QDMA TX NUM */
446#define MTK_QDMA_TX_NUM 16
447#define MTK_QDMA_TX_MASK ((MTK_QDMA_TX_NUM) - 1)
448#define QID_LOW_BITS(x) ((x) & 0xf)
449#define QID_HIGH_BITS(x) ((((x) >> 4) & 0x3) << 20)
450#define QID_BITS_V2(x) (((x) & 0x3f) << 16)
451
452/* QDMA V2 descriptor txd6 */
453#define TX_DMA_INS_VLAN_V2 BIT(16)
454
455/* QDMA V2 descriptor txd5 */
456#define TX_DMA_CHKSUM_V2 (0x7 << 28)
457#define TX_DMA_TSO_V2 BIT(31)
458
459/* QDMA V2 descriptor txd4 */
460#define TX_DMA_FPORT_SHIFT_V2 8
461#define TX_DMA_FPORT_MASK_V2 0xf
462#define TX_DMA_SWC_V2 BIT(30)
463
464#if defined(CONFIG_MEDIATEK_NETSYS_V2)
465#define MTK_TX_DMA_BUF_LEN 0xffff
466#define MTK_TX_DMA_BUF_SHIFT 8
467#else
468#define MTK_TX_DMA_BUF_LEN 0x3fff
469#define MTK_TX_DMA_BUF_SHIFT 16
470#endif
471
developera2bdbd52021-05-31 19:10:17 +0800472#if defined(CONFIG_MEDIATEK_NETSYS_V2)
developerfd40db22021-04-29 10:08:25 +0800473#define MTK_RX_DMA_BUF_LEN 0xffff
474#define MTK_RX_DMA_BUF_SHIFT 8
475#define RX_DMA_SPORT_SHIFT 26
476#define RX_DMA_SPORT_MASK 0xf
477#else
478#define MTK_RX_DMA_BUF_LEN 0x3fff
479#define MTK_RX_DMA_BUF_SHIFT 16
480#define RX_DMA_SPORT_SHIFT 19
481#define RX_DMA_SPORT_MASK 0x7
482#endif
483
484/* QDMA descriptor txd4 */
485#define TX_DMA_CHKSUM (0x7 << 29)
486#define TX_DMA_TSO BIT(28)
487#define TX_DMA_FPORT_SHIFT 25
488#define TX_DMA_FPORT_MASK 0x7
489#define TX_DMA_INS_VLAN BIT(16)
490
491/* QDMA descriptor txd3 */
492#define TX_DMA_OWNER_CPU BIT(31)
493#define TX_DMA_LS0 BIT(30)
494#define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << MTK_TX_DMA_BUF_SHIFT)
495#define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN)
496#define TX_DMA_SWC BIT(14)
497#define TX_DMA_SDL(_x) (TX_DMA_PLEN0(_x))
498
499/* PDMA on MT7628 */
500#define TX_DMA_DONE BIT(31)
501#define TX_DMA_LS1 BIT(14)
502#define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
503
504/* QDMA descriptor rxd2 */
505#define RX_DMA_DONE BIT(31)
506#define RX_DMA_LSO BIT(30)
507#define RX_DMA_PLEN0(_x) (((_x) & MTK_RX_DMA_BUF_LEN) << MTK_RX_DMA_BUF_SHIFT)
508#define RX_DMA_GET_PLEN0(_x) (((_x) >> MTK_RX_DMA_BUF_SHIFT) & MTK_RX_DMA_BUF_LEN)
developer77d03a72021-06-06 00:06:00 +0800509#define RX_DMA_GET_AGG_CNT(_x) (((_x) >> 2) & 0xff)
510#define RX_DMA_GET_REV(_x) (((_x) >> 10) & 0x1f)
developerfd40db22021-04-29 10:08:25 +0800511#define RX_DMA_VTAG BIT(15)
512
513/* QDMA descriptor rxd3 */
514#define RX_DMA_VID(_x) ((_x) & VLAN_VID_MASK)
515#define RX_DMA_TCI(_x) ((_x) & (VLAN_PRIO_MASK | VLAN_VID_MASK))
516#define RX_DMA_VPID(_x) (((_x) >> 16) & 0xffff)
517
518/* QDMA descriptor rxd4 */
519#define RX_DMA_L4_VALID BIT(24)
520#define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
521#define RX_DMA_SPECIAL_TAG BIT(22) /* switch header in packet */
522
523#define RX_DMA_GET_SPORT(_x) (((_x) >> RX_DMA_SPORT_SHIFT) & RX_DMA_SPORT_MASK)
524
525/* PDMA V2 descriptor rxd3 */
526#define RX_DMA_VTAG_V2 BIT(0)
527#define RX_DMA_L4_VALID_V2 BIT(2)
528
529/* PDMA V2 descriptor rxd4 */
530#define RX_DMA_VID_V2(_x) RX_DMA_VID(_x)
developer255bba22021-07-27 15:16:33 +0800531#define RX_DMA_TCI_V2(_x) RX_DMA_TCI(_x)
532#define RX_DMA_VPID_V2(_x) RX_DMA_VPID(_x)
developerfd40db22021-04-29 10:08:25 +0800533
developer77d03a72021-06-06 00:06:00 +0800534/* PDMA V2 descriptor rxd6 */
535#define RX_DMA_GET_FLUSH_RSN_V2(_x) ((_x) & 0x7)
536#define RX_DMA_GET_AGG_CNT_V2(_x) (((_x) >> 16) & 0xff)
537
developerfd40db22021-04-29 10:08:25 +0800538/* PHY Indirect Access Control registers */
539#define MTK_PHY_IAC 0x10004
540#define PHY_IAC_ACCESS BIT(31)
541#define PHY_IAC_READ BIT(19)
542#define PHY_IAC_WRITE BIT(18)
543#define PHY_IAC_START BIT(16)
544#define PHY_IAC_ADDR_SHIFT 20
545#define PHY_IAC_REG_SHIFT 25
546#define PHY_IAC_TIMEOUT HZ
547
548#define MTK_MAC_MISC 0x1000c
549#define MTK_MUX_TO_ESW BIT(0)
550
551/* Mac control registers */
552#define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
553#define MAC_MCR_MAX_RX_1536 BIT(24)
554#define MAC_MCR_IPG_CFG (BIT(18) | BIT(16))
555#define MAC_MCR_FORCE_MODE BIT(15)
556#define MAC_MCR_TX_EN BIT(14)
557#define MAC_MCR_RX_EN BIT(13)
558#define MAC_MCR_BACKOFF_EN BIT(9)
559#define MAC_MCR_BACKPR_EN BIT(8)
560#define MAC_MCR_FORCE_RX_FC BIT(5)
561#define MAC_MCR_FORCE_TX_FC BIT(4)
562#define MAC_MCR_SPEED_1000 BIT(3)
563#define MAC_MCR_SPEED_100 BIT(2)
564#define MAC_MCR_FORCE_DPX BIT(1)
565#define MAC_MCR_FORCE_LINK BIT(0)
566#define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE)
567
568/* Mac status registers */
569#define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
570#define MAC_MSR_EEE1G BIT(7)
571#define MAC_MSR_EEE100M BIT(6)
572#define MAC_MSR_RX_FC BIT(5)
573#define MAC_MSR_TX_FC BIT(4)
574#define MAC_MSR_SPEED_1000 BIT(3)
575#define MAC_MSR_SPEED_100 BIT(2)
576#define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)
577#define MAC_MSR_DPX BIT(1)
578#define MAC_MSR_LINK BIT(0)
579
580/* TRGMII RXC control register */
581#define TRGMII_RCK_CTRL 0x10300
582#define DQSI0(x) ((x << 0) & GENMASK(6, 0))
583#define DQSI1(x) ((x << 8) & GENMASK(14, 8))
584#define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
585#define RXC_RST BIT(31)
586#define RXC_DQSISEL BIT(30)
587#define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
588#define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2)
589
590#define NUM_TRGMII_CTRL 5
591
592/* TRGMII RXC control register */
593#define TRGMII_TCK_CTRL 0x10340
594#define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
595#define TXC_INV BIT(30)
596#define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2)
597#define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2))
598
599/* TRGMII TX Drive Strength */
600#define TRGMII_TD_ODT(i) (0x10354 + 8 * (i))
601#define TD_DM_DRVP(x) ((x) & 0xf)
602#define TD_DM_DRVN(x) (((x) & 0xf) << 4)
603
604/* TRGMII Interface mode register */
605#define INTF_MODE 0x10390
606#define TRGMII_INTF_DIS BIT(0)
607#define TRGMII_MODE BIT(1)
608#define TRGMII_CENTRAL_ALIGNED BIT(2)
609#define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
610#define INTF_MODE_RGMII_10_100 0
611
612/* GPIO port control registers for GMAC 2*/
613#define GPIO_OD33_CTRL8 0x4c0
614#define GPIO_BIAS_CTRL 0xed0
615#define GPIO_DRV_SEL10 0xf00
616
617/* ethernet subsystem chip id register */
618#define ETHSYS_CHIPID0_3 0x0
619#define ETHSYS_CHIPID4_7 0x4
620#define MT7623_ETH 7623
621#define MT7622_ETH 7622
622#define MT7621_ETH 7621
623
624/* ethernet system control register */
625#define ETHSYS_SYSCFG 0x10
626#define SYSCFG_DRAM_TYPE_DDR2 BIT(4)
627
628/* ethernet subsystem config register */
629#define ETHSYS_SYSCFG0 0x14
630#define SYSCFG0_GE_MASK 0x3
631#define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2)))
632#define SYSCFG0_SGMII_MASK GENMASK(9, 8)
633#define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK)
634#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
635#define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
636#define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
637
638
639/* ethernet subsystem clock register */
640#define ETHSYS_CLKCFG0 0x2c
641#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
642#define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6))
643#define ETHSYS_TRGMII_MT7621_APLL BIT(6)
644#define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5)
645
646/* ethernet reset control register */
developer545abf02021-07-15 17:47:01 +0800647#define ETHSYS_RSTCTRL 0x34
648#define RSTCTRL_FE BIT(6)
649#define RSTCTRL_PPE BIT(31)
650#define RSTCTRL_PPE1 BIT(30)
651#define RSTCTRL_ETH BIT(23)
652
653/* ethernet reset check idle register */
654#define ETHSYS_FE_RST_CHK_IDLE_EN 0x28
655
developerfd40db22021-04-29 10:08:25 +0800656
657/* SGMII subsystem config registers */
658/* Register to auto-negotiation restart */
659#define SGMSYS_PCS_CONTROL_1 0x0
660#define SGMII_AN_RESTART BIT(9)
661#define SGMII_ISOLATE BIT(10)
662#define SGMII_AN_ENABLE BIT(12)
663#define SGMII_LINK_STATYS BIT(18)
664#define SGMII_AN_ABILITY BIT(19)
665#define SGMII_AN_COMPLETE BIT(21)
666#define SGMII_PCS_FAULT BIT(23)
667#define SGMII_AN_EXPANSION_CLR BIT(30)
668
669/* Register to programmable link timer, the unit in 2 * 8ns */
670#define SGMSYS_PCS_LINK_TIMER 0x18
671#define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0))
672
673/* Register to control remote fault */
674#define SGMSYS_SGMII_MODE 0x20
675#define SGMII_IF_MODE_BIT0 BIT(0)
676#define SGMII_SPEED_DUPLEX_AN BIT(1)
677#define SGMII_SPEED_10 0x0
678#define SGMII_SPEED_100 BIT(2)
679#define SGMII_SPEED_1000 BIT(3)
680#define SGMII_DUPLEX_FULL BIT(4)
681#define SGMII_IF_MODE_BIT5 BIT(5)
682#define SGMII_REMOTE_FAULT_DIS BIT(8)
683#define SGMII_CODE_SYNC_SET_VAL BIT(9)
684#define SGMII_CODE_SYNC_SET_EN BIT(10)
685#define SGMII_SEND_AN_ERROR_EN BIT(11)
686#define SGMII_IF_MODE_MASK GENMASK(5, 1)
687
688/* Register to set SGMII speed, ANA RG_ Control Signals III*/
689#define SGMSYS_ANA_RG_CS3 0x2028
690#define RG_PHY_SPEED_MASK (BIT(2) | BIT(3))
691#define RG_PHY_SPEED_1_25G 0x0
692#define RG_PHY_SPEED_3_125G BIT(2)
693
694/* Register to power up QPHY */
695#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
696#define SGMII_PHYA_PWD BIT(4)
697
developerf8ac94a2021-07-29 16:40:01 +0800698/* Register to QPHY wrapper control */
699#define SGMSYS_QPHY_WRAP_CTRL 0xec
700#define SGMII_PN_SWAP_MASK GENMASK(1, 0)
701#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1))
702
developerfd40db22021-04-29 10:08:25 +0800703/* Infrasys subsystem config registers */
704#define INFRA_MISC2 0x70c
705#define CO_QPHY_SEL BIT(0)
706#define GEPHY_MAC_SEL BIT(1)
707
developer255bba22021-07-27 15:16:33 +0800708/* Top misc registers */
709#define USB_PHY_SWITCH_REG 0x218
710#define QPHY_SEL_MASK GENMASK(1, 0)
711#define SGMII_QPHY_SEL 0x10
712
developerfd40db22021-04-29 10:08:25 +0800713/*MDIO control*/
714#define MII_MMD_ACC_CTL_REG 0x0d
715#define MII_MMD_ADDR_DATA_REG 0x0e
716#define MMD_OP_MODE_DATA BIT(14)
717
718/* MT7628/88 specific stuff */
719#define MT7628_PDMA_OFFSET 0x0800
720#define MT7628_SDM_OFFSET 0x0c00
721
722#define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00)
723#define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04)
724#define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08)
725#define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c)
726#define MT7628_PST_DTX_IDX0 BIT(0)
727
728#define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c)
729#define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10)
730
731struct mtk_rx_dma {
732 unsigned int rxd1;
733 unsigned int rxd2;
734 unsigned int rxd3;
735 unsigned int rxd4;
developera2bdbd52021-05-31 19:10:17 +0800736#if defined(CONFIG_MEDIATEK_NETSYS_V2)
developerfd40db22021-04-29 10:08:25 +0800737 unsigned int rxd5;
738 unsigned int rxd6;
739 unsigned int rxd7;
740 unsigned int rxd8;
741#endif
742} __packed __aligned(4);
743
744struct mtk_tx_dma {
745 unsigned int txd1;
746 unsigned int txd2;
747 unsigned int txd3;
748 unsigned int txd4;
749#if defined(CONFIG_MEDIATEK_NETSYS_V2)
750 unsigned int txd5;
751 unsigned int txd6;
752 unsigned int txd7;
753 unsigned int txd8;
754#endif
755} __packed __aligned(4);
756
757struct mtk_eth;
758struct mtk_mac;
759
760/* struct mtk_hw_stats - the structure that holds the traffic statistics.
761 * @stats_lock: make sure that stats operations are atomic
762 * @reg_offset: the status register offset of the SoC
763 * @syncp: the refcount
764 *
765 * All of the supported SoCs have hardware counters for traffic statistics.
766 * Whenever the status IRQ triggers we can read the latest stats from these
767 * counters and store them in this struct.
768 */
769struct mtk_hw_stats {
770 u64 tx_bytes;
771 u64 tx_packets;
772 u64 tx_skip;
773 u64 tx_collisions;
774 u64 rx_bytes;
775 u64 rx_packets;
776 u64 rx_overflow;
777 u64 rx_fcs_errors;
778 u64 rx_short_errors;
779 u64 rx_long_errors;
780 u64 rx_checksum_errors;
781 u64 rx_flow_control_packets;
782
783 spinlock_t stats_lock;
784 u32 reg_offset;
785 struct u64_stats_sync syncp;
786};
787
788enum mtk_tx_flags {
789 /* PDMA descriptor can point at 1-2 segments. This enum allows us to
790 * track how memory was allocated so that it can be freed properly.
791 */
792 MTK_TX_FLAGS_SINGLE0 = 0x01,
793 MTK_TX_FLAGS_PAGE0 = 0x02,
794
795 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted
796 * SKB out instead of looking up through hardware TX descriptor.
797 */
798 MTK_TX_FLAGS_FPORT0 = 0x04,
799 MTK_TX_FLAGS_FPORT1 = 0x08,
800};
801
802/* This enum allows us to identify how the clock is defined on the array of the
803 * clock in the order
804 */
805enum mtk_clks_map {
806 MTK_CLK_ETHIF,
807 MTK_CLK_SGMIITOP,
808 MTK_CLK_ESW,
809 MTK_CLK_GP0,
810 MTK_CLK_GP1,
811 MTK_CLK_GP2,
812 MTK_CLK_FE,
813 MTK_CLK_TRGPLL,
814 MTK_CLK_SGMII_TX_250M,
815 MTK_CLK_SGMII_RX_250M,
816 MTK_CLK_SGMII_CDR_REF,
817 MTK_CLK_SGMII_CDR_FB,
818 MTK_CLK_SGMII2_TX_250M,
819 MTK_CLK_SGMII2_RX_250M,
820 MTK_CLK_SGMII2_CDR_REF,
821 MTK_CLK_SGMII2_CDR_FB,
822 MTK_CLK_SGMII_CK,
823 MTK_CLK_ETH2PLL,
824 MTK_CLK_WOCPU0,
825 MTK_CLK_WOCPU1,
826 MTK_CLK_MAX
827};
828
829#define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
830 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
831 BIT(MTK_CLK_TRGPLL))
832#define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
833 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
834 BIT(MTK_CLK_GP2) | \
835 BIT(MTK_CLK_SGMII_TX_250M) | \
836 BIT(MTK_CLK_SGMII_RX_250M) | \
837 BIT(MTK_CLK_SGMII_CDR_REF) | \
838 BIT(MTK_CLK_SGMII_CDR_FB) | \
839 BIT(MTK_CLK_SGMII_CK) | \
840 BIT(MTK_CLK_ETH2PLL))
841#define MT7621_CLKS_BITMAP (0)
842#define MT7628_CLKS_BITMAP (0)
843#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
844 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
845 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
846 BIT(MTK_CLK_SGMII_TX_250M) | \
847 BIT(MTK_CLK_SGMII_RX_250M) | \
848 BIT(MTK_CLK_SGMII_CDR_REF) | \
849 BIT(MTK_CLK_SGMII_CDR_FB) | \
850 BIT(MTK_CLK_SGMII2_TX_250M) | \
851 BIT(MTK_CLK_SGMII2_RX_250M) | \
852 BIT(MTK_CLK_SGMII2_CDR_REF) | \
853 BIT(MTK_CLK_SGMII2_CDR_FB) | \
854 BIT(MTK_CLK_SGMII_CK) | \
855 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
856
857#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
858 BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
859 BIT(MTK_CLK_SGMII_TX_250M) | \
860 BIT(MTK_CLK_SGMII_RX_250M) | \
861 BIT(MTK_CLK_SGMII_CDR_REF) | \
862 BIT(MTK_CLK_SGMII_CDR_FB) | \
863 BIT(MTK_CLK_SGMII2_TX_250M) | \
864 BIT(MTK_CLK_SGMII2_RX_250M) | \
865 BIT(MTK_CLK_SGMII2_CDR_REF) | \
866 BIT(MTK_CLK_SGMII2_CDR_FB))
867
developer255bba22021-07-27 15:16:33 +0800868#define MT7981_CLKS_BITMAP (MT7986_CLKS_BITMAP)
869
developerfd40db22021-04-29 10:08:25 +0800870enum mtk_dev_state {
871 MTK_HW_INIT,
872 MTK_RESETTING
873};
874
875/* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at
876 * by the TX descriptor s
877 * @skb: The SKB pointer of the packet being sent
878 * @dma_addr0: The base addr of the first segment
879 * @dma_len0: The length of the first segment
880 * @dma_addr1: The base addr of the second segment
881 * @dma_len1: The length of the second segment
882 */
883struct mtk_tx_buf {
884 struct sk_buff *skb;
885 u32 flags;
886 DEFINE_DMA_UNMAP_ADDR(dma_addr0);
887 DEFINE_DMA_UNMAP_LEN(dma_len0);
888 DEFINE_DMA_UNMAP_ADDR(dma_addr1);
889 DEFINE_DMA_UNMAP_LEN(dma_len1);
890};
891
892/* struct mtk_tx_ring - This struct holds info describing a TX ring
893 * @dma: The descriptor ring
894 * @buf: The memory pointed at by the ring
895 * @phys: The physical addr of tx_buf
896 * @next_free: Pointer to the next free descriptor
897 * @last_free: Pointer to the last free descriptor
developerc4671b22021-05-28 13:16:42 +0800898 * @last_free_ptr: Hardware pointer value of the last free descriptor
developerfd40db22021-04-29 10:08:25 +0800899 * @thresh: The threshold of minimum amount of free descriptors
900 * @free_count: QDMA uses a linked list. Track how many free descriptors
901 * are present
902 */
903struct mtk_tx_ring {
904 struct mtk_tx_dma *dma;
905 struct mtk_tx_buf *buf;
906 dma_addr_t phys;
907 struct mtk_tx_dma *next_free;
908 struct mtk_tx_dma *last_free;
developerc4671b22021-05-28 13:16:42 +0800909 u32 last_free_ptr;
developerfd40db22021-04-29 10:08:25 +0800910 u16 thresh;
911 atomic_t free_count;
912 int dma_size;
913 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */
914 dma_addr_t phys_pdma;
915 int cpu_idx;
916};
917
918/* PDMA rx ring mode */
919enum mtk_rx_flags {
920 MTK_RX_FLAGS_NORMAL = 0,
921 MTK_RX_FLAGS_HWLRO,
922 MTK_RX_FLAGS_QDMA,
923};
924
925/* struct mtk_rx_ring - This struct holds info describing a RX ring
926 * @dma: The descriptor ring
927 * @data: The memory pointed at by the ring
928 * @phys: The physical addr of rx_buf
929 * @frag_size: How big can each fragment be
930 * @buf_size: The size of each packet buffer
931 * @calc_idx: The current head of ring
developer77d03a72021-06-06 00:06:00 +0800932 * @ring_no: The index of ring
developerfd40db22021-04-29 10:08:25 +0800933 */
934struct mtk_rx_ring {
935 struct mtk_rx_dma *dma;
936 u8 **data;
937 dma_addr_t phys;
938 u16 frag_size;
939 u16 buf_size;
940 u16 dma_size;
941 bool calc_idx_update;
942 u16 calc_idx;
943 u32 crx_idx_reg;
developer77d03a72021-06-06 00:06:00 +0800944 u32 ring_no;
developerfd40db22021-04-29 10:08:25 +0800945};
946
developer18f46a82021-07-20 21:08:21 +0800947/* struct mtk_napi - This is the structure holding NAPI-related information,
948 * and a mtk_napi struct is binding to one interrupt group
949 * @napi: The NAPI struct
950 * @rx_ring: Pointer to the memory holding info about the RX ring
951 * @irq_grp_idx: The index indicates which interrupt group that this
952 * mtk_napi is binding to
953 */
954struct mtk_napi {
955 struct napi_struct napi;
956 struct mtk_eth *eth;
957 struct mtk_rx_ring *rx_ring;
958 u32 irq_grp_no;
959};
960
developerfd40db22021-04-29 10:08:25 +0800961enum mkt_eth_capabilities {
962 MTK_RGMII_BIT = 0,
963 MTK_TRGMII_BIT,
964 MTK_SGMII_BIT,
965 MTK_ESW_BIT,
966 MTK_GEPHY_BIT,
967 MTK_MUX_BIT,
968 MTK_INFRA_BIT,
969 MTK_SHARED_SGMII_BIT,
970 MTK_HWLRO_BIT,
developer18f46a82021-07-20 21:08:21 +0800971 MTK_RSS_BIT,
developerfd40db22021-04-29 10:08:25 +0800972 MTK_SHARED_INT_BIT,
973 MTK_TRGMII_MT7621_CLK_BIT,
974 MTK_QDMA_BIT,
developera2bdbd52021-05-31 19:10:17 +0800975 MTK_NETSYS_V2_BIT,
developerfd40db22021-04-29 10:08:25 +0800976 MTK_SOC_MT7628_BIT,
developer545abf02021-07-15 17:47:01 +0800977 MTK_RSTCTRL_PPE1_BIT,
developer255bba22021-07-27 15:16:33 +0800978 MTK_U3_COPHY_V2_BIT,
developerfd40db22021-04-29 10:08:25 +0800979
980 /* MUX BITS*/
981 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
982 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
983 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
984 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
985 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
986
987 /* PATH BITS */
988 MTK_ETH_PATH_GMAC1_RGMII_BIT,
989 MTK_ETH_PATH_GMAC1_TRGMII_BIT,
990 MTK_ETH_PATH_GMAC1_SGMII_BIT,
991 MTK_ETH_PATH_GMAC2_RGMII_BIT,
992 MTK_ETH_PATH_GMAC2_SGMII_BIT,
993 MTK_ETH_PATH_GMAC2_GEPHY_BIT,
994 MTK_ETH_PATH_GDM1_ESW_BIT,
995};
996
997/* Supported hardware group on SoCs */
998#define MTK_RGMII BIT(MTK_RGMII_BIT)
999#define MTK_TRGMII BIT(MTK_TRGMII_BIT)
1000#define MTK_SGMII BIT(MTK_SGMII_BIT)
1001#define MTK_ESW BIT(MTK_ESW_BIT)
1002#define MTK_GEPHY BIT(MTK_GEPHY_BIT)
1003#define MTK_MUX BIT(MTK_MUX_BIT)
1004#define MTK_INFRA BIT(MTK_INFRA_BIT)
1005#define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT)
1006#define MTK_HWLRO BIT(MTK_HWLRO_BIT)
developer18f46a82021-07-20 21:08:21 +08001007#define MTK_RSS BIT(MTK_RSS_BIT)
developerfd40db22021-04-29 10:08:25 +08001008#define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT)
1009#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
1010#define MTK_QDMA BIT(MTK_QDMA_BIT)
developera2bdbd52021-05-31 19:10:17 +08001011#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
developerfd40db22021-04-29 10:08:25 +08001012#define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
developer545abf02021-07-15 17:47:01 +08001013#define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT)
developer255bba22021-07-27 15:16:33 +08001014#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT)
developerfd40db22021-04-29 10:08:25 +08001015
1016#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
1017 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
1018#define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \
1019 BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
1020#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
1021 BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
1022#define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
1023 BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
1024#define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
1025 BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
1026
1027/* Supported path present on SoCs */
1028#define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT)
1029#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
1030#define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT)
1031#define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT)
1032#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
1033#define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
1034#define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT)
1035
1036#define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
1037#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
1038#define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII)
1039#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
1040#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
1041#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
1042#define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
1043
1044/* MUXes present on SoCs */
1045/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
1046#define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX)
1047
1048/* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */
1049#define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \
1050 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA)
1051
1052/* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
1053#define MTK_MUX_U3_GMAC2_TO_QPHY \
1054 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA)
1055
1056/* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */
1057#define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
1058 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
1059 MTK_SHARED_SGMII)
1060
1061/* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
1062#define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
1063 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
1064
1065#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
1066
1067#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
1068 MTK_GMAC2_RGMII | MTK_SHARED_INT | \
1069 MTK_TRGMII_MT7621_CLK | MTK_QDMA)
1070
1071#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
1072 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
1073 MTK_MUX_GDM1_TO_GMAC1_ESW | \
1074 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA)
1075
1076#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \
1077 MTK_QDMA)
1078
1079#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628)
1080
1081#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
1082 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
1083 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
1084 MTK_MUX_U3_GMAC2_TO_QPHY | \
1085 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
1086
developerfd40db22021-04-29 10:08:25 +08001087#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
1088 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
developer545abf02021-07-15 17:47:01 +08001089 MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
developerfd40db22021-04-29 10:08:25 +08001090
developer255bba22021-07-27 15:16:33 +08001091#define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
1092 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
1093 MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
1094 MTK_NETSYS_V2)
1095
developerfd40db22021-04-29 10:08:25 +08001096/* struct mtk_eth_data - This is the structure holding all differences
1097 * among various plaforms
1098 * @ana_rgc3: The offset for register ANA_RGC3 related to
1099 * sgmiisys syscon
1100 * @caps Flags shown the extra capability for the SoC
1101 * @hw_features Flags shown HW features
1102 * @required_clks Flags shown the bitmap for required clocks on
1103 * the target SoC
1104 * @required_pctl A bool value to show whether the SoC requires
1105 * the extra setup for those pins used by GMAC.
1106 */
1107struct mtk_soc_data {
1108 u32 ana_rgc3;
1109 u32 caps;
1110 u32 required_clks;
1111 bool required_pctl;
1112 netdev_features_t hw_features;
1113 bool has_sram;
1114};
1115
1116/* currently no SoC has more than 2 macs */
1117#define MTK_MAX_DEVS 2
1118
1119#define MTK_SGMII_PHYSPEED_AN BIT(31)
1120#define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0)
1121#define MTK_SGMII_PHYSPEED_1000 BIT(0)
1122#define MTK_SGMII_PHYSPEED_2500 BIT(1)
developerf8ac94a2021-07-29 16:40:01 +08001123#define MTK_SGMII_PN_SWAP BIT(16)
developerfd40db22021-04-29 10:08:25 +08001124#define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x))
1125
1126/* struct mtk_sgmii - This is the structure holding sgmii regmap and its
1127 * characteristics
1128 * @regmap: The register map pointing at the range used to setup
1129 * SGMII modes
1130 * @flags: The enum refers to which mode the sgmii wants to run on
1131 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
1132 */
1133
1134struct mtk_sgmii {
1135 struct regmap *regmap[MTK_MAX_DEVS];
1136 u32 flags[MTK_MAX_DEVS];
1137 u32 ana_rgc3;
1138};
1139
1140/* struct mtk_eth - This is the main datasructure for holding the state
1141 * of the driver
1142 * @dev: The device pointer
1143 * @base: The mapped register i/o base
1144 * @page_lock: Make sure that register operations are atomic
1145 * @tx_irq__lock: Make sure that IRQ register operations are atomic
1146 * @rx_irq__lock: Make sure that IRQ register operations are atomic
1147 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a
1148 * dummy for NAPI to work
1149 * @netdev: The netdev instances
1150 * @mac: Each netdev is linked to a physical MAC
1151 * @irq: The IRQ that we are using
1152 * @msg_enable: Ethtool msg level
1153 * @ethsys: The register map pointing at the range used to setup
1154 * MII modes
1155 * @infra: The register map pointing at the range used to setup
1156 * SGMII and GePHY path
1157 * @pctl: The register map pointing at the range used to setup
1158 * GMAC port drive/slew values
1159 * @dma_refcnt: track how many netdevs are using the DMA engine
1160 * @tx_ring: Pointer to the memory holding info about the TX ring
1161 * @rx_ring: Pointer to the memory holding info about the RX ring
1162 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring
1163 * @tx_napi: The TX NAPI struct
1164 * @rx_napi: The RX NAPI struct
1165 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring
1166 * @phy_scratch_ring: physical address of scratch_ring
1167 * @scratch_head: The scratch memory that scratch_ring points to.
1168 * @clks: clock array for all clocks required
1169 * @mii_bus: If there is a bus we need to create an instance for it
1170 * @pending_work: The workqueue used to reset the dma ring
1171 * @state: Initialization and runtime state of the device
1172 * @soc: Holding specific data among vaious SoCs
1173 */
1174
1175struct mtk_eth {
1176 struct device *dev;
1177 void __iomem *base;
1178 spinlock_t page_lock;
1179 spinlock_t tx_irq_lock;
1180 spinlock_t rx_irq_lock;
1181 struct net_device dummy_dev;
1182 struct net_device *netdev[MTK_MAX_DEVS];
1183 struct mtk_mac *mac[MTK_MAX_DEVS];
developer18f46a82021-07-20 21:08:21 +08001184 int irq[MTK_MAX_IRQ_NUM];
developerfd40db22021-04-29 10:08:25 +08001185 u32 msg_enable;
1186 unsigned long sysclk;
1187 struct regmap *ethsys;
1188 struct regmap *infra;
1189 struct mtk_sgmii *sgmii;
1190 struct regmap *pctl;
1191 bool hwlro;
1192 refcount_t dma_refcnt;
1193 struct mtk_tx_ring tx_ring;
1194 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM];
1195 struct mtk_rx_ring rx_ring_qdma;
1196 struct napi_struct tx_napi;
developer18f46a82021-07-20 21:08:21 +08001197 struct mtk_napi rx_napi[MTK_RX_NAPI_NUM];
developerfd40db22021-04-29 10:08:25 +08001198 struct mtk_tx_dma *scratch_ring;
1199 dma_addr_t phy_scratch_ring;
1200 void *scratch_head;
1201 struct clk *clks[MTK_CLK_MAX];
1202
1203 struct mii_bus *mii_bus;
1204 struct work_struct pending_work;
1205 unsigned long state;
1206
1207 const struct mtk_soc_data *soc;
1208
1209 u32 tx_int_mask_reg;
1210 u32 tx_int_status_reg;
1211 u32 rx_dma_l4_valid;
1212 int ip_align;
1213};
1214
1215/* struct mtk_mac - the structure that holds the info about the MACs of the
1216 * SoC
1217 * @id: The number of the MAC
1218 * @interface: Interface mode kept for detecting change in hw settings
1219 * @of_node: Our devicetree node
1220 * @hw: Backpointer to our main datastruture
1221 * @hw_stats: Packet statistics counter
1222 */
1223struct mtk_mac {
developerfb556ca2021-10-13 10:52:09 +08001224 unsigned int id;
developerfd40db22021-04-29 10:08:25 +08001225 phy_interface_t interface;
1226 unsigned int mode;
1227 int speed;
1228 struct device_node *of_node;
1229 struct phylink *phylink;
1230 struct phylink_config phylink_config;
1231 struct mtk_eth *hw;
1232 struct mtk_hw_stats *hw_stats;
1233 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
1234 int hwlro_ip_cnt;
1235};
1236
1237/* the struct describing the SoC. these are declared in the soc_xyz.c files */
1238extern const struct of_device_id of_mtk_match[];
developer77d03a72021-06-06 00:06:00 +08001239extern u32 mtk_hwlro_stats_ebl;
developerfd40db22021-04-29 10:08:25 +08001240
1241/* read the hardware status register */
1242void mtk_stats_update_mac(struct mtk_mac *mac);
1243
1244void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
1245u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
1246
1247int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
1248 u32 ana_rgc3);
1249int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id);
1250int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id,
1251 const struct phylink_link_state *state);
1252void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id);
1253
1254int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
1255int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
1256int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
1257
1258#endif /* MTK_ETH_H */