| commit | f8ac94ab9f2ff0854ac3b34aadccad516c2c4dea | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Thu Jul 29 16:40:01 2021 +0800 |
| committer | developer <developer@mediatek.com> | Fri Jul 30 14:10:58 2021 +0800 |
| tree | 5c0a844f2ad8ea78c79947e8039bae10b813d54e | |
| parent | 5f18e6ca5428bdd4f944a709e4be1311aa3e4aba [diff] [blame] |
[][Add sgmii pn_swap mode support for mt7981 eth] [Description] Add sgmii pn_swap mode support for mt7981 eth [Release-log] N/A Change-Id: Ie29910dff4272b562a2af9d62812cfddcc8a7c3c Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/4809853
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h index d39464d..a6995df 100755 --- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -690,6 +690,11 @@ #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 #define SGMII_PHYA_PWD BIT(4) +/* Register to QPHY wrapper control */ +#define SGMSYS_QPHY_WRAP_CTRL 0xec +#define SGMII_PN_SWAP_MASK GENMASK(1, 0) +#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1)) + /* Infrasys subsystem config registers */ #define INFRA_MISC2 0x70c #define CO_QPHY_SEL BIT(0) @@ -1110,6 +1115,7 @@ #define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0) #define MTK_SGMII_PHYSPEED_1000 BIT(0) #define MTK_SGMII_PHYSPEED_2500 BIT(1) +#define MTK_SGMII_PN_SWAP BIT(16) #define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x)) /* struct mtk_sgmii - This is the structure holding sgmii regmap and its