[][Add sgmii pn_swap mode support for mt7981 eth]
[Description]
Add sgmii pn_swap mode support for mt7981 eth
[Release-log]
N/A
Change-Id: Ie29910dff4272b562a2af9d62812cfddcc8a7c3c
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/4809853
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index d39464d..a6995df 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -690,6 +690,11 @@
#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
#define SGMII_PHYA_PWD BIT(4)
+/* Register to QPHY wrapper control */
+#define SGMSYS_QPHY_WRAP_CTRL 0xec
+#define SGMII_PN_SWAP_MASK GENMASK(1, 0)
+#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1))
+
/* Infrasys subsystem config registers */
#define INFRA_MISC2 0x70c
#define CO_QPHY_SEL BIT(0)
@@ -1110,6 +1115,7 @@
#define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0)
#define MTK_SGMII_PHYSPEED_1000 BIT(0)
#define MTK_SGMII_PHYSPEED_2500 BIT(1)
+#define MTK_SGMII_PN_SWAP BIT(16)
#define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x))
/* struct mtk_sgmii - This is the structure holding sgmii regmap and its
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c
index 4db27df..2785666 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c
@@ -28,6 +28,10 @@
ss->regmap[i] = syscon_node_to_regmap(np);
if (IS_ERR(ss->regmap[i]))
return PTR_ERR(ss->regmap[i]);
+
+ ss->flags[i] &= ~(MTK_SGMII_PN_SWAP);
+ if (of_property_read_bool(np, "pn_swap"))
+ ss->flags[i] |= MTK_SGMII_PN_SWAP;
}
return 0;
@@ -52,6 +56,10 @@
val |= SGMII_AN_RESTART;
regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
+ if(MTK_HAS_FLAGS(ss->flags[id],MTK_SGMII_PN_SWAP))
+ regmap_update_bits(ss->regmap[id], SGMSYS_QPHY_WRAP_CTRL,
+ SGMII_PN_SWAP_MASK, SGMII_PN_SWAP_TX_RX);
+
regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
val &= ~SGMII_PHYA_PWD;
regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
@@ -100,6 +108,9 @@
regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
+ if(MTK_HAS_FLAGS(ss->flags[id],MTK_SGMII_PN_SWAP))
+ regmap_update_bits(ss->regmap[id], SGMSYS_QPHY_WRAP_CTRL,
+ SGMII_PN_SWAP_MASK, SGMII_PN_SWAP_TX_RX);
/* Release PHYA power down state */
regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
val &= ~SGMII_PHYA_PWD;