| commit | 024387a2a963c9b0cd45631e4ee3cfca61841623 | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Wed Dec 07 22:18:27 2022 +0800 |
| committer | developer <developer@mediatek.com> | Thu Dec 08 19:05:33 2022 +0800 |
| tree | 4abce3197d926e59a1b303856dbb21869789f12e | |
| parent | 8b609e82a940f37cc5e226449e3f5ea92c0ec981 [diff] [blame] |
[][kernel][mt7988][eth][Add PHYA reset for HSGMII] [Description] Add PHYA reset for HSGMII. If without this patch, HSGMII might work abnormally which prevents GMAC from receiving packets. [Release-log] N/A Change-Id: I32e041a0a05dae77220469e3ee448cfad599bc7c Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6889368
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 45b2e24..2f54f96 100755 --- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -861,6 +861,16 @@ #define CO_QPHY_SEL BIT(0) #define GEPHY_MAC_SEL BIT(1) +/* Toprgu subsystem config registers */ +#define TOPRGU_SWSYSRST 0x18 +#define SWSYSRST_UNLOCK_KEY GENMASK(31, 24) +#define SWSYSRST_XFI_PLL_GRST BIT(16) +#define SWSYSRST_XFI_PEXPT1_GRST BIT(15) +#define SWSYSRST_XFI_PEXPT0_GRST BIT(14) +#define SWSYSRST_SGMII1_GRST BIT(2) +#define SWSYSRST_SGMII0_GRST BIT(1) +#define TOPRGU_SWSYSRST_EN 0xFC + /* Top misc registers */ #define TOP_MISC_NETSYS_PCS_MUX 0x84 #define NETSYS_PCS_MUX_MASK GENMASK(1, 0)