| commit | 2cdef09496e613942b800753e597e6ebb269749a | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Fri Apr 15 17:27:55 2022 +0800 |
| committer | developer <developer@mediatek.com> | Mon Apr 18 10:07:24 2022 +0800 |
| tree | f3f5848ae3efbd060165cfae7a30c09d0731a612 | |
| parent | 1a63ef9f85cc992b314927926e580191f8226f6f [diff] [blame] |
[][update CDM guard band follow DE suggestion]
[Description]
Change CDM guard band RSV_BUF from 0x40 to 0x 80
- default 0x40 may cause xDMA hang
[Release-log]
N/A
Change-Id: I35709661d4715141b153c693d6d834e52e39f5d6
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/5862368
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h index a31c4f6..4cd18bc 100755 --- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -364,7 +364,7 @@ #define MTK_CHK_DDONE_EN BIT(28) #define MTK_DMAD_WR_WDONE BIT(26) #define MTK_WCOMP_EN BIT(24) -#define MTK_RESV_BUF (0x40 << 16) +#define MTK_RESV_BUF (0x80 << 16) #define MTK_MUTLI_CNT (0x4 << 12) /* QDMA Reset Index Register */