| commit | 2b76a9d983820ef4cce97bdcadcfcc14c18efc7f | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Tue Sep 20 14:59:45 2022 +0800 |
| committer | developer <developer@mediatek.com> | Thu Sep 22 21:59:24 2022 +0800 |
| tree | a2cddbf3fa0f39c2b883ac5914cbc5990a2029f2 | |
| parent | 711759cdeb989e235c1dc17a56006d8b6028d056 [diff] [blame] |
[][kernel][common][eth][Fix HSGMII link down issue] [Description] Fix HSGMII link down issue. If without this patch, HSGMII may link down when PHY performs re-AN. [Release-log] N/A Change-Id: I40ad6e5d35b92e4e36689ab3db9e25b7695d2f43 Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6538088
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 54674ad..edaeceb 100755 --- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -720,6 +720,10 @@ #define SGMII_SEND_AN_ERROR_EN BIT(11) #define SGMII_IF_MODE_MASK GENMASK(5, 1) +/* Register to reset SGMII design */ +#define SGMII_RESERVED_0 0x34 +#define SGMII_SW_RESET BIT(0) + /* Register to set SGMII speed, ANA RG_ Control Signals III*/ #define SGMSYS_ANA_RG_CS3 0x2028 #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3))