| commit | f1816a93a143fb94cba51f8b35377d40cb9c811b | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Mon Nov 15 12:18:02 2021 +0800 |
| committer | developer <developer@mediatek.com> | Mon Nov 15 12:27:54 2021 +0800 |
| tree | a2e18d944b5e2efe3188acbb04949c3af13fcd33 | |
| parent | 63866c96d3a37ff880a7af1a3001f1f384ba2336 [diff] [blame] |
[][Fix mt7981 incorrect cophy CR setting for sgmii] [Description] Fix mt7981 incorrect cophy CR setting for sgmii [Release-log] N/A Change-Id: Ie1e5e39537c2bfd574e97075fa58192941c7db12 Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/5266089
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 2650c93..321a263 100755 --- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -708,7 +708,7 @@ /* Top misc registers */ #define USB_PHY_SWITCH_REG 0x218 #define QPHY_SEL_MASK GENMASK(1, 0) -#define SGMII_QPHY_SEL 0x10 +#define SGMII_QPHY_SEL 0x2 /*MDIO control*/ #define MII_MMD_ACC_CTL_REG 0x0d