[][Add NETSYS reset flow for Panther/Cheetah]
[Description]
Add NETSYS reset flow for Panther/Cheetah.
This patch includes below changes:
- FE warm reset
- FE cold reset
- HNAT warm reset
- FE/HNAT/JEDI/WARP reset notifier
- FE error interrupt ISR
- QDMA/WDMA/ADMA hang detector
[Usage]
- Command:
cat /proc/mtketh/reset_event
- Description:
Dump counters for all the reset reasons(TSO/RFIFO/FORCE...)
[Release-log]
N/A
Change-Id: I2b4d52ae3644ee4d7117f118422fffd1c29ec0a7
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/5829085
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 4cd18bc..41e8f30 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -56,13 +56,25 @@
#define MTK_HW_LRO_REPLACE_DELTA 1000
#define MTK_HW_LRO_SDL_REMAIN_ROOM 1522
+/* Frame Engine Global Configuration */
+#define MTK_FE_GLO_CFG 0x00
+#define MTK_FE_LINK_DOWN_P3 BIT(11)
+#define MTK_FE_LINK_DOWN_P4 BIT(12)
+
/* Frame Engine Global Reset Register */
#define MTK_RST_GL 0x04
#define RST_GL_PSE BIT(0)
/* Frame Engine Interrupt Status Register */
-#define MTK_INT_STATUS 0x08
-#define MTK_INT_STATUS2 0x28
+#define MTK_FE_INT_STATUS 0x08
+#define MTK_FE_INT_STATUS2 0x28
+#define MTK_FE_INT_ENABLE 0x0C
+#define MTK_FE_INT_FQ_EMPTY BIT(8)
+#define MTK_FE_INT_TSO_FAIL BIT(12)
+#define MTK_FE_INT_TSO_ILLEGAL BIT(13)
+#define MTK_FE_INT_TSO_ALIGN BIT(14)
+#define MTK_FE_INT_RFIFO_OV BIT(18)
+#define MTK_FE_INT_RFIFO_UF BIT(19)
#define MTK_GDM1_AF BIT(28)
#define MTK_GDM2_AF BIT(29)
@@ -133,9 +145,13 @@
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#define PDMA_BASE 0x6000
#define QDMA_BASE 0x4400
+#define WDMA_BASE(x) (0x4800 + ((x) * 0x400))
+#define PPE_BASE(x) (0x2200 + ((x) * 0x400))
#else
#define PDMA_BASE 0x0800
#define QDMA_BASE 0x1800
+#define WDMA_BASE(x) (0x2800 + ((x) * 0x400))
+#define PPE_BASE(x) (0xE00 + ((x) * 0x400))
#endif
/* PDMA RX Base Pointer Register */
#define MTK_PRX_BASE_PTR0 (PDMA_BASE + 0x100)
@@ -407,6 +423,9 @@
/* QDMA Interrupt Status Register */
#define MTK_QDMA_INT_MASK (QDMA_BASE + 0x21c)
+/* QDMA DMA FSM */
+#define MTK_QDMA_FSM (QDMA_BASE + 0x234)
+
/* QDMA Interrupt Mask Register */
#define MTK_QDMA_HRED2 (QDMA_BASE + 0x244)
@@ -416,6 +435,9 @@
/* QDMA TX Forward DMA Pointer Register */
#define MTK_QTX_DTX_PTR (QDMA_BASE +0x304)
+/* QDMA TX Forward DMA Counter */
+#define MTK_QDMA_FWD_CNT (QDMA_BASE + 0x308)
+
/* QDMA TX Release CPU Pointer Register */
#define MTK_QTX_CRX_PTR (QDMA_BASE +0x310)
@@ -434,6 +456,12 @@
/* QDMA FQ Free Page Buffer Length Register */
#define MTK_QDMA_FQ_BLEN (QDMA_BASE +0x32c)
+/* WDMA Registers */
+#define MTK_WDMA_DTX_PTR(x) (WDMA_BASE(x) + 0xC)
+#define MTK_WDMA_GLO_CFG(x) (WDMA_BASE(x) + 0x204)
+#define MTK_WDMA_TX_DBG_MON0(x) (WDMA_BASE(x) + 0x230)
+#define MTK_CDM_TXFIFO_RDY BIT(7)
+
/* GMA1 Received Good Byte Count Register */
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#define MTK_GDM1_TX_GBCNT 0x1C00
@@ -648,9 +676,14 @@
/* ethernet reset control register */
#define ETHSYS_RSTCTRL 0x34
#define RSTCTRL_FE BIT(6)
-#define RSTCTRL_PPE BIT(31)
-#define RSTCTRL_PPE1 BIT(30)
#define RSTCTRL_ETH BIT(23)
+#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#define RSTCTRL_PPE0 BIT(30)
+#define RSTCTRL_PPE1 BIT(31)
+#elif
+#define RSTCTRL_PPE0 BIT(31)
+#define RSTCTRL_PPE1 NULL
+#endif
/* ethernet reset check idle register */
#define ETHSYS_FE_RST_CHK_IDLE_EN 0x28
@@ -1097,7 +1130,7 @@
#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
- MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
+ MTK_NETSYS_V2)
#define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
@@ -1148,6 +1181,15 @@
u32 ana_rgc3;
};
+
+/* struct mtk_reset_event - This is the structure holding statistics counters
+ * for reset events
+ * @count: The counter is used to record the number of events
+ */
+struct mtk_reset_event {
+ u32 count[32];
+};
+
/* struct mtk_eth - This is the main datasructure for holding the state
* of the driver
* @dev: The device pointer
@@ -1207,6 +1249,7 @@
struct napi_struct tx_napi;
struct mtk_napi rx_napi[MTK_RX_NAPI_NUM];
struct mtk_tx_dma *scratch_ring;
+ struct mtk_reset_event reset_event;
dma_addr_t phy_scratch_ring;
void *scratch_head;
struct clk *clks[MTK_CLK_MAX];
@@ -1222,6 +1265,7 @@
u32 rx_dma_l4_valid;
int ip_align;
spinlock_t syscfg0_lock;
+ struct timer_list mtk_dma_monitor_timer;
};
/* struct mtk_mac - the structure that holds the info about the MACs of the
@@ -1255,6 +1299,7 @@
void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
+u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg);
int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
u32 ana_rgc3);
@@ -1266,5 +1311,7 @@
int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
+void mtk_gdm_config(struct mtk_eth *eth, u32 config);
+void ethsys_reset(struct mtk_eth *eth, u32 reset_bits);
#endif /* MTK_ETH_H */