| commit | 9e9fb4c010597f1d3d27889eedf2c2ad51236a73 | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Tue Nov 30 17:33:04 2021 +0800 |
| committer | developer <developer@mediatek.com> | Tue Nov 30 19:41:09 2021 +0800 |
| tree | 0607e76abf8d13cea1488ffabf66e4bdb1b05107 | |
| parent | e3c7cd1f5a06dcf0300197fd147c592baa487c71 [diff] [blame] |
[][Refactor mt7981 eth clk to real clk source from clk driver] [Description] Refactor mt7981 eth clk to real clk source from clk driver [Release-log] N/A Change-Id: I09cfe5db8b19cf7c074b72effdc2b584984e7307 Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/5325658
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 321a263..e09a798 100755 --- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -865,8 +865,17 @@ BIT(MTK_CLK_SGMII2_CDR_REF) | \ BIT(MTK_CLK_SGMII2_CDR_FB)) -#define MT7981_CLKS_BITMAP (MT7986_CLKS_BITMAP) +#define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ + BIT(MTK_CLK_WOCPU0) | \ + BIT(MTK_CLK_SGMII_TX_250M) | \ + BIT(MTK_CLK_SGMII_RX_250M) | \ + BIT(MTK_CLK_SGMII_CDR_REF) | \ + BIT(MTK_CLK_SGMII_CDR_FB) | \ + BIT(MTK_CLK_SGMII2_TX_250M) | \ + BIT(MTK_CLK_SGMII2_RX_250M) | \ + BIT(MTK_CLK_SGMII2_CDR_REF) | \ + BIT(MTK_CLK_SGMII2_CDR_FB)) enum mtk_dev_state { MTK_HW_INIT, MTK_RESETTING