[][Refactor mt7981 eth clk to real clk source from clk driver]
[Description]
Refactor mt7981 eth clk to real clk source from clk driver
[Release-log]
N/A
Change-Id: I09cfe5db8b19cf7c074b72effdc2b584984e7307
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/5325658
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clkitg.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clkitg.dtsi
index ecece3d..06ef41d 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clkitg.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clkitg.dtsi
@@ -128,11 +128,11 @@
<&topckgen CK_TOP_NET1_D5_D4>,
<&topckgen CK_TOP_NET1_D8_D2>,
<&topckgen CK_TOP_NET1_D8_D4>,
- <&topckgen CK_TOP_CB_NET2_800M>,
+ <&clk40m>,
<&topckgen CK_TOP_CB_NET2_D4>,
<&topckgen CK_TOP_NET2_D4_D2>,
<&topckgen CK_TOP_CB_WEDMCU_208M>,
- <&topckgen CK_TOP_CB_SGM_325M>,
+ <&clk40m>,
<&topckgen CK_TOP_CB_RTC_32K>,
<&topckgen CK_TOP_CB_RTC_32P7K>,
<&topckgen CK_TOP_NFI1X>,
@@ -176,11 +176,11 @@
<&topckgen CK_TOP_NETSYS_SEL>,
<&topckgen CK_TOP_NETSYS_500M_SEL>,
<&topckgen CK_TOP_NETSYS_MCU_SEL>,
- <&topckgen CK_TOP_NETSYS_2X_SEL>,
- <&topckgen CK_TOP_SGM_325M_SEL>,
+ <&clk40m>,
+ <&clk40m>,
<&topckgen CK_TOP_SGM_REG_SEL>,
<&topckgen CK_TOP_NETSYS_500M_SEL>,
- <&topckgen CK_TOP_NETSYS_2X_SEL>,
+ <&clk40m>,
<&topckgen CK_TOP_USB3_PHY_SEL>,
<&topckgen CK_TOP_F26M_SEL>,
<&topckgen CK_TOP_U2U3_SEL>,
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi
index 49add10..37bb424 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi
@@ -314,7 +314,7 @@
ethsys: syscon@15000000 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "mediatek,mt7986-ethsys",
+ compatible = "mediatek,mt7981-ethsys",
"syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
@@ -334,24 +334,27 @@
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>;
- clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
+ clocks = <ðsys CK_ETH_FE_EN>,
+ <ðsys CK_ETH_GP2_EN>,
+ <ðsys CK_ETH_GP1_EN>,
+ <ðsys CK_ETH_WOCPU0_EN>,
+ <&sgmiisys0 CK_SGM0_TX_EN>,
+ <&sgmiisys0 CK_SGM0_RX_EN>,
+ <&sgmiisys0 CK_SGM0_CK0_EN>,
+ <&sgmiisys0 CK_SGM0_CDR_CK0_EN>,
+ <&sgmiisys1 CK_SGM1_TX_EN>,
+ <&sgmiisys1 CK_SGM1_RX_EN>,
+ <&sgmiisys1 CK_SGM1_CK1_EN>,
+ <&sgmiisys1 CK_SGM1_CDR_CK1_EN>;
+ clock-names = "fe", "gp2", "gp1", "wocpu0",
"sgmii_tx250m", "sgmii_rx250m",
"sgmii_cdr_ref", "sgmii_cdr_fb",
"sgmii2_tx250m", "sgmii2_rx250m",
"sgmii2_cdr_ref", "sgmii2_cdr_fb";
+ assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>,
+ <&topckgen CK_TOP_SGM_325M_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>,
+ <&topckgen CK_TOP_CB_SGM_325M>;
mediatek,ethsys = <ðsys>;
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
mediatek,infracfg = <&topmisc>;
@@ -370,14 +373,14 @@
};
sgmiisys0: syscon@10060000 {
- compatible = "mediatek,mt7986-sgmiisys", "syscon";
+ compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
reg = <0 0x10060000 0 0x1000>;
pn_swap;
#clock-cells = <1>;
};
sgmiisys1: syscon@10070000 {
- compatible = "mediatek,mt7986-sgmiisys", "syscon";
+ compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
reg = <0 0x10070000 0 0x1000>;
#clock-cells = <1>;
};
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 321a263..e09a798 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -865,8 +865,17 @@
BIT(MTK_CLK_SGMII2_CDR_REF) | \
BIT(MTK_CLK_SGMII2_CDR_FB))
-#define MT7981_CLKS_BITMAP (MT7986_CLKS_BITMAP)
+#define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
+ BIT(MTK_CLK_WOCPU0) | \
+ BIT(MTK_CLK_SGMII_TX_250M) | \
+ BIT(MTK_CLK_SGMII_RX_250M) | \
+ BIT(MTK_CLK_SGMII_CDR_REF) | \
+ BIT(MTK_CLK_SGMII_CDR_FB) | \
+ BIT(MTK_CLK_SGMII2_TX_250M) | \
+ BIT(MTK_CLK_SGMII2_RX_250M) | \
+ BIT(MTK_CLK_SGMII2_CDR_REF) | \
+ BIT(MTK_CLK_SGMII2_CDR_FB))
enum mtk_dev_state {
MTK_HW_INIT,
MTK_RESETTING