[][Kernel][mt7988][eth][Add Ethernet clock config]
[Description]
Add Ethernet clock configurations which is suggested by
clock owner - Xiufeng.
If without this patch, some Ethernet/WED functions won't
work after removing mt7988-clkitg.dtsi.
[Release-log]
N/A
Change-Id: I835888ed0d6408d2dd7eb2c704ecc0d3c6f076a8
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6988778
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index dc02870..fe36102 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -1023,10 +1023,27 @@
MTK_CLK_ETH2PLL,
MTK_CLK_WOCPU0,
MTK_CLK_WOCPU1,
- MTK_CLK_USXGMII0_SEL,
- MTK_CLK_USXGMII1_SEL,
- MTK_CLK_SGM0_SEL,
- MTK_CLK_SGM1_SEL,
+ MTK_CLK_ETHWARP_WOCPU2,
+ MTK_CLK_ETHWARP_WOCPU1,
+ MTK_CLK_ETHWARP_WOCPU0,
+ MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
+ MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
+ MTK_CLK_TOP_SGM_0_SEL,
+ MTK_CLK_TOP_SGM_1_SEL,
+ MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
+ MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
+ MTK_CLK_TOP_ETH_GMII_SEL,
+ MTK_CLK_TOP_ETH_REFCK_50M_SEL,
+ MTK_CLK_TOP_ETH_SYS_200M_SEL,
+ MTK_CLK_TOP_ETH_SYS_SEL,
+ MTK_CLK_TOP_ETH_XGMII_SEL,
+ MTK_CLK_TOP_ETH_MII_SEL,
+ MTK_CLK_TOP_NETSYS_SEL,
+ MTK_CLK_TOP_NETSYS_500M_SEL,
+ MTK_CLK_TOP_NETSYS_PAO_2X_SEL,
+ MTK_CLK_TOP_NETSYS_SYNC_250M_SEL,
+ MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL,
+ MTK_CLK_TOP_NETSYS_WARP_SEL,
MTK_CLK_MAX
};
@@ -1090,10 +1107,27 @@
BIT(MTK_CLK_SGMII_RX_250M) | \
BIT(MTK_CLK_SGMII2_TX_250M) | \
BIT(MTK_CLK_SGMII2_RX_250M) | \
- BIT(MTK_CLK_USXGMII0_SEL) | \
- BIT(MTK_CLK_USXGMII1_SEL) | \
- BIT(MTK_CLK_SGM0_SEL) | \
- BIT(MTK_CLK_SGM1_SEL))
+ BIT(MTK_CLK_ETHWARP_WOCPU2) | \
+ BIT(MTK_CLK_ETHWARP_WOCPU1) | \
+ BIT(MTK_CLK_ETHWARP_WOCPU0) | \
+ BIT(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
+ BIT(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
+ BIT(MTK_CLK_TOP_SGM_0_SEL) | \
+ BIT(MTK_CLK_TOP_SGM_1_SEL) | \
+ BIT(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
+ BIT(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
+ BIT(MTK_CLK_TOP_ETH_GMII_SEL) | \
+ BIT(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
+ BIT(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
+ BIT(MTK_CLK_TOP_ETH_SYS_SEL) | \
+ BIT(MTK_CLK_TOP_ETH_XGMII_SEL) | \
+ BIT(MTK_CLK_TOP_ETH_MII_SEL) | \
+ BIT(MTK_CLK_TOP_NETSYS_SEL) | \
+ BIT(MTK_CLK_TOP_NETSYS_500M_SEL) | \
+ BIT(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \
+ BIT(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \
+ BIT(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \
+ BIT(MTK_CLK_TOP_NETSYS_WARP_SEL))
enum mtk_dev_state {
MTK_HW_INIT,
@@ -1452,7 +1486,7 @@
struct mtk_soc_data {
u32 ana_rgc3;
u64 caps;
- u32 required_clks;
+ u64 required_clks;
bool required_pctl;
netdev_features_t hw_features;
bool has_sram;