[][Kernel][mt7988][eth][Add clock enable flow for Ethernet/Thermal]
[Description]
Add clock enabling flow for Ethernet and Thermal drivers.
Meanwhile, "always on" clock is removed from clkitg.dtsi
If without this patch, Ethernet/Thermal driver can only
use dummy clock but not actual clock preparation flow.
[Release-log]
N/A
Change-Id: I3769beab4e3087fe83636bf370bea9d33868c5b6
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6801479
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index d1e1d65..1a11af6 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -980,6 +980,11 @@
MTK_CLK_GP0,
MTK_CLK_GP1,
MTK_CLK_GP2,
+ MTK_CLK_GP3,
+ MTK_CLK_XGP1,
+ MTK_CLK_XGP2,
+ MTK_CLK_XGP3,
+ MTK_CLK_CRYPTO,
MTK_CLK_FE,
MTK_CLK_TRGPLL,
MTK_CLK_SGMII_TX_250M,
@@ -994,6 +999,10 @@
MTK_CLK_ETH2PLL,
MTK_CLK_WOCPU0,
MTK_CLK_WOCPU1,
+ MTK_CLK_USXGMII0_SEL,
+ MTK_CLK_USXGMII1_SEL,
+ MTK_CLK_SGM0_SEL,
+ MTK_CLK_SGM1_SEL,
MTK_CLK_MAX
};
@@ -1048,16 +1057,19 @@
BIT(MTK_CLK_SGMII2_CDR_REF) | \
BIT(MTK_CLK_SGMII2_CDR_FB))
-#define MT7988_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
- BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
+#define MT7988_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_ESW) | \
+ BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
+ BIT(MTK_CLK_GP3) | BIT(MTK_CLK_XGP1) | \
+ BIT(MTK_CLK_XGP2) | BIT(MTK_CLK_XGP3) | \
+ BIT(MTK_CLK_CRYPTO) | \
BIT(MTK_CLK_SGMII_TX_250M) | \
BIT(MTK_CLK_SGMII_RX_250M) | \
- BIT(MTK_CLK_SGMII_CDR_REF) | \
- BIT(MTK_CLK_SGMII_CDR_FB) | \
BIT(MTK_CLK_SGMII2_TX_250M) | \
BIT(MTK_CLK_SGMII2_RX_250M) | \
- BIT(MTK_CLK_SGMII2_CDR_REF) | \
- BIT(MTK_CLK_SGMII2_CDR_FB))
+ BIT(MTK_CLK_USXGMII0_SEL) | \
+ BIT(MTK_CLK_USXGMII1_SEL) | \
+ BIT(MTK_CLK_SGM0_SEL) | \
+ BIT(MTK_CLK_SGM1_SEL))
enum mtk_dev_state {
MTK_HW_INIT,