[][Kernel][mt7988][eth][Add clock enable flow for Ethernet/Thermal]
[Description]
Add clock enabling flow for Ethernet and Thermal drivers.
Meanwhile, "always on" clock is removed from clkitg.dtsi
If without this patch, Ethernet/Thermal driver can only
use dummy clock but not actual clock preparation flow.
[Release-log]
N/A
Change-Id: I3769beab4e3087fe83636bf370bea9d33868c5b6
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6801479
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988-clkitg.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988-clkitg.dtsi
index 44809d9..c97cb24 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988-clkitg.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988-clkitg.dtsi
@@ -49,10 +49,10 @@
<&topckgen CK_TOP_NET1_D5_D4>,
<&topckgen CK_TOP_CB_NET1_D8>,
<&topckgen CK_TOP_NET1_D8_D2>,
- <&topckgen CK_TOP_NET1_D8_D4>,
+ <&system_clk>,
<&topckgen CK_TOP_NET1_D8_D8>,
<&topckgen CK_TOP_NET1_D8_D16>,
- <&topckgen CK_TOP_CB_NET2_800M>,
+ <&system_clk>,
<&topckgen CK_TOP_CB_NET2_D2>,
<&topckgen CK_TOP_CB_NET2_D4>,
<&topckgen CK_TOP_NET2_D4_D4>,
@@ -60,7 +60,7 @@
<&topckgen CK_TOP_CB_NET2_D6>,
<&topckgen CK_TOP_CB_NET2_D8>,
<&topckgen CK_TOP_CB_WEDMCU_208M>,
- <&topckgen CK_TOP_CB_SGM_325M>,
+ <&system_clk>,
<&topckgen CK_TOP_CB_NETSYS_850M>,
<&topckgen CK_TOP_CB_MSDC_400M>,
<&topckgen CK_TOP_CKSQ_40M_D2>,
@@ -96,8 +96,8 @@
<&system_clk>,
<&topckgen CK_TOP_NETSYS_SEL>,
<&topckgen CK_TOP_NETSYS_500M_SEL>,
- <&topckgen CK_TOP_NETSYS_2X_SEL>,
- <&topckgen CK_TOP_NETSYS_GSW_SEL>,
+ <&system_clk>,
+ <&system_clk>,
<&topckgen CK_TOP_ETH_GMII_SEL>,
<&topckgen CK_TOP_NETSYS_MCU_SEL>,
<&topckgen CK_TOP_NETSYS_PAO_2X_SEL>,
@@ -129,11 +129,11 @@
<&system_clk>,
<&topckgen CK_TOP_SSPXTP_SEL>,
<&topckgen CK_TOP_USB_PHY_SEL>,
- <&topckgen CK_TOP_USXGMII_SBUS_0_SEL>,
- <&topckgen CK_TOP_USXGMII_SBUS_1_SEL>,
- <&topckgen CK_TOP_SGM_0_SEL>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
<&topckgen CK_TOP_SGM_SBUS_0_SEL>,
- <&topckgen CK_TOP_SGM_1_SEL>,
+ <&system_clk>,
<&topckgen CK_TOP_SGM_SBUS_1_SEL>,
<&topckgen CK_TOP_XFI_PHY_0_XTAL_SEL>,
<&topckgen CK_TOP_XFI_PHY_1_XTAL_SEL>,
@@ -232,7 +232,7 @@
<&infracfg_ao CK_INFRA_66M_SEJ_BCK>,
<&infracfg_ao CK_INFRA_PRE_CK_SEJ_F13M>,
<&infracfg_ao CK_INFRA_66M_TRNG>,
- <&infracfg_ao CK_INFRA_26M_THERM_SYSTEM>,
+ <&system_clk>,
<&infracfg_ao CK_INFRA_I2C_BCK>,
<&infracfg_ao CK_INFRA_66M_UART0_PCK>,
<&infracfg_ao CK_INFRA_66M_UART1_PCK>,
@@ -312,22 +312,22 @@
<&system_clk>,
<&system_clk>,
<&system_clk>,
+ <&system_clk>,
- <ðsys CK_ETHDMA_XGP1_EN>,
- <ðsys CK_ETHDMA_XGP2_EN>,
- <ðsys CK_ETHDMA_XGP3_EN>,
- <ðsys CK_ETHDMA_FE_EN>,
- <ðsys CK_ETHDMA_GP2_EN>,
- <ðsys CK_ETHDMA_GP1_EN>,
- <ðsys CK_ETHDMA_GP3_EN>,
- <ðsys CK_ETHDMA_ESW_EN>,
- <ðsys CK_ETHDMA_CRYPT0_EN>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
<ðwarp CK_ETHWARP_WOCPU2_EN>,
<ðwarp CK_ETHWARP_WOCPU1_EN>,
<ðwarp CK_ETHWARP_WOCPU0_EN>,
- <&sgmiisys0 CK_SGM0_TX_EN>,
- <&sgmiisys0 CK_SGM0_RX_EN>,
- <&sgmiisys1 CK_SGM1_TX_EN>,
- <&sgmiisys1 CK_SGM1_RX_EN>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
<&system_clk>,
<&system_clk>;
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
index e097cda..28e702e 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
@@ -488,7 +488,7 @@
compatible = "mediatek,mt7988-lvts";
#thermal-sensor-cells = <1>;
reg = <0 0x1100a000 0 0x1000>;
- clocks = <&system_clk>;
+ clocks = <&infracfg_ao CK_INFRA_26M_THERM_SYSTEM>;
clock-names = "lvts_clk";
nvmem-cells = <&lvts_calibration>;
nvmem-cell-names = "e_data1";
@@ -742,24 +742,40 @@
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>;
- clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
- "sgmii_tx250m", "sgmii_rx250m",
- "sgmii_cdr_ref", "sgmii_cdr_fb",
- "sgmii2_tx250m", "sgmii2_rx250m",
- "sgmii2_cdr_ref", "sgmii2_cdr_fb";
+ clocks = <ðsys CK_ETHDMA_XGP1_EN>,
+ <ðsys CK_ETHDMA_XGP2_EN>,
+ <ðsys CK_ETHDMA_XGP3_EN>,
+ <ðsys CK_ETHDMA_FE_EN>,
+ <ðsys CK_ETHDMA_GP2_EN>,
+ <ðsys CK_ETHDMA_GP1_EN>,
+ <ðsys CK_ETHDMA_GP3_EN>,
+ <ðsys CK_ETHDMA_ESW_EN>,
+ <ðsys CK_ETHDMA_CRYPT0_EN>,
+ <&sgmiisys0 CK_SGM0_TX_EN>,
+ <&sgmiisys0 CK_SGM0_RX_EN>,
+ <&sgmiisys1 CK_SGM1_TX_EN>,
+ <&sgmiisys1 CK_SGM1_RX_EN>,
+ <&topckgen CK_TOP_USXGMII_SBUS_0_SEL>,
+ <&topckgen CK_TOP_USXGMII_SBUS_1_SEL>,
+ <&topckgen CK_TOP_SGM_0_SEL>,
+ <&topckgen CK_TOP_SGM_1_SEL>;
+ clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
+ "gp3", "esw", "crypto", "sgmii_tx250m",
+ "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
+ "usxgmii0_sel", "usxgmii1_sel",
+ "sgm0_sel", "sgm1_sel";
+ assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>,
+ <&topckgen CK_TOP_NETSYS_GSW_SEL>,
+ <&topckgen CK_TOP_USXGMII_SBUS_0_SEL>,
+ <&topckgen CK_TOP_USXGMII_SBUS_1_SEL>,
+ <&topckgen CK_TOP_SGM_0_SEL>,
+ <&topckgen CK_TOP_SGM_1_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>,
+ <&topckgen CK_TOP_CB_NET1_D4>,
+ <&topckgen CK_TOP_NET1_D8_D4>,
+ <&topckgen CK_TOP_NET1_D8_D4>,
+ <&topckgen CK_TOP_CB_SGM_325M>,
+ <&topckgen CK_TOP_CB_SGM_325M>;
mediatek,ethsys = <ðsys>;
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index bd2268e..d35dddb 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -67,10 +67,12 @@
};
static const char * const mtk_clks_source_name[] = {
- "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
+ "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "gp3",
+ "xgp1", "xgp2", "xgp3", "crypto", "fe", "trgpll",
"sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
"sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
"sgmii_ck", "eth2pll", "wocpu0","wocpu1",
+ "usxgmii0_sel", "usxgmii1_sel", "sgm0_sel", "sgm1_sel",
};
void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index d1e1d65..1a11af6 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -980,6 +980,11 @@
MTK_CLK_GP0,
MTK_CLK_GP1,
MTK_CLK_GP2,
+ MTK_CLK_GP3,
+ MTK_CLK_XGP1,
+ MTK_CLK_XGP2,
+ MTK_CLK_XGP3,
+ MTK_CLK_CRYPTO,
MTK_CLK_FE,
MTK_CLK_TRGPLL,
MTK_CLK_SGMII_TX_250M,
@@ -994,6 +999,10 @@
MTK_CLK_ETH2PLL,
MTK_CLK_WOCPU0,
MTK_CLK_WOCPU1,
+ MTK_CLK_USXGMII0_SEL,
+ MTK_CLK_USXGMII1_SEL,
+ MTK_CLK_SGM0_SEL,
+ MTK_CLK_SGM1_SEL,
MTK_CLK_MAX
};
@@ -1048,16 +1057,19 @@
BIT(MTK_CLK_SGMII2_CDR_REF) | \
BIT(MTK_CLK_SGMII2_CDR_FB))
-#define MT7988_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
- BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
+#define MT7988_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_ESW) | \
+ BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
+ BIT(MTK_CLK_GP3) | BIT(MTK_CLK_XGP1) | \
+ BIT(MTK_CLK_XGP2) | BIT(MTK_CLK_XGP3) | \
+ BIT(MTK_CLK_CRYPTO) | \
BIT(MTK_CLK_SGMII_TX_250M) | \
BIT(MTK_CLK_SGMII_RX_250M) | \
- BIT(MTK_CLK_SGMII_CDR_REF) | \
- BIT(MTK_CLK_SGMII_CDR_FB) | \
BIT(MTK_CLK_SGMII2_TX_250M) | \
BIT(MTK_CLK_SGMII2_RX_250M) | \
- BIT(MTK_CLK_SGMII2_CDR_REF) | \
- BIT(MTK_CLK_SGMII2_CDR_FB))
+ BIT(MTK_CLK_USXGMII0_SEL) | \
+ BIT(MTK_CLK_USXGMII1_SEL) | \
+ BIT(MTK_CLK_SGM0_SEL) | \
+ BIT(MTK_CLK_SGM1_SEL))
enum mtk_dev_state {
MTK_HW_INIT,