| commit | 599cda4358c7f99ac1dfcc0a247aee3c65e92f8f | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Tue May 24 15:13:31 2022 +0800 |
| committer | developer <developer@mediatek.com> | Thu Jun 02 18:28:58 2022 +0800 |
| tree | e225bd4e5f00bf866ad9296e50a2f4a1dd60d7a2 | |
| parent | a11349deec8f6ee560de181f2b852b4e90212618 [diff] [blame] |
[][Update Ethernet MDIO CL45 programming sequence] [Description] Change Ethernet MDIO CL45 programming sequence. Note: These patches porting from upstream Linux-5.18. [Release-log] N/A Change-Id: I1025a3f17caed2d69536dae03ded0743935be812 Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6023025
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 367f7f1..56db8c7 100755 --- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -570,8 +570,11 @@ #define MTK_PHY_IAC 0x10004 #define PHY_IAC_ACCESS BIT(31) #define PHY_IAC_READ BIT(19) +#define PHY_IAC_READ_C45 (3 << 18) +#define PHY_IAC_ADDR_C45 (0 << 18) #define PHY_IAC_WRITE BIT(18) #define PHY_IAC_START BIT(16) +#define PHY_IAC_START_C45 (0 << 16) #define PHY_IAC_ADDR_SHIFT 20 #define PHY_IAC_REG_SHIFT 25 #define PHY_IAC_TIMEOUT HZ