blob: b6380ffeb9f3b58ba7da3464fdad7700feb6ecee [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +08001/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7 */
8
9#ifndef MTK_ETH_H
10#define MTK_ETH_H
11
12#include <linux/dma-mapping.h>
13#include <linux/netdevice.h>
14#include <linux/of_net.h>
15#include <linux/u64_stats_sync.h>
16#include <linux/refcount.h>
17#include <linux/phylink.h>
18
19#define MTK_QDMA_PAGE_SIZE 2048
20#define MTK_MAX_RX_LENGTH 1536
21#define MTK_DMA_SIZE 2048
22#define MTK_NAPI_WEIGHT 256
23#define MTK_MAC_COUNT 2
24#define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
25#define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
26#define MTK_DMA_DUMMY_DESC 0xffffffff
27#define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \
28 NETIF_MSG_PROBE | \
29 NETIF_MSG_LINK | \
30 NETIF_MSG_TIMER | \
31 NETIF_MSG_IFDOWN | \
32 NETIF_MSG_IFUP | \
33 NETIF_MSG_RX_ERR | \
34 NETIF_MSG_TX_ERR)
35#define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \
36 NETIF_F_RXCSUM | \
37 NETIF_F_HW_VLAN_CTAG_TX | \
developerfd40db22021-04-29 10:08:25 +080038 NETIF_F_SG | NETIF_F_TSO | \
39 NETIF_F_TSO6 | \
40 NETIF_F_IPV6_CSUM)
41#define MTK_SET_FEATURES (NETIF_F_LRO | \
42 NETIF_F_HW_VLAN_CTAG_RX)
43#define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM)
44#define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
45
developerfd40db22021-04-29 10:08:25 +080046#define MTK_HW_LRO_DMA_SIZE 8
47
48#define MTK_MAX_LRO_RX_LENGTH (4096 * 3)
49#define MTK_MAX_LRO_IP_CNT 2
50#define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */
51#define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */
52#define MTK_HW_LRO_AGG_TIME 10 /* 200us */
53#define MTK_HW_LRO_AGE_TIME 50 /* 1ms */
54#define MTK_HW_LRO_MAX_AGG_CNT 64
55#define MTK_HW_LRO_BW_THRE 3000
56#define MTK_HW_LRO_REPLACE_DELTA 1000
57#define MTK_HW_LRO_SDL_REMAIN_ROOM 1522
58
developer8051e042022-04-08 13:26:36 +080059/* Frame Engine Global Configuration */
60#define MTK_FE_GLO_CFG 0x00
61#define MTK_FE_LINK_DOWN_P3 BIT(11)
62#define MTK_FE_LINK_DOWN_P4 BIT(12)
63
developerfd40db22021-04-29 10:08:25 +080064/* Frame Engine Global Reset Register */
65#define MTK_RST_GL 0x04
66#define RST_GL_PSE BIT(0)
67
68/* Frame Engine Interrupt Status Register */
developer8051e042022-04-08 13:26:36 +080069#define MTK_FE_INT_STATUS 0x08
70#define MTK_FE_INT_STATUS2 0x28
71#define MTK_FE_INT_ENABLE 0x0C
72#define MTK_FE_INT_FQ_EMPTY BIT(8)
73#define MTK_FE_INT_TSO_FAIL BIT(12)
74#define MTK_FE_INT_TSO_ILLEGAL BIT(13)
75#define MTK_FE_INT_TSO_ALIGN BIT(14)
76#define MTK_FE_INT_RFIFO_OV BIT(18)
77#define MTK_FE_INT_RFIFO_UF BIT(19)
developerfd40db22021-04-29 10:08:25 +080078#define MTK_GDM1_AF BIT(28)
79#define MTK_GDM2_AF BIT(29)
80
81/* PDMA HW LRO Alter Flow Timer Register */
82#define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
83
84/* Frame Engine Interrupt Grouping Register */
85#define MTK_FE_INT_GRP 0x20
86
developer77d03a72021-06-06 00:06:00 +080087/* Frame Engine LRO auto-learn table info */
88#define MTK_FE_ALT_CF8 0x300
89#define MTK_FE_ALT_SGL_CFC 0x304
90#define MTK_FE_ALT_SEQ_CFC 0x308
91
developerfd40db22021-04-29 10:08:25 +080092/* CDMP Ingress Control Register */
93#define MTK_CDMQ_IG_CTRL 0x1400
94#define MTK_CDMQ_STAG_EN BIT(0)
95
96/* CDMP Ingress Control Register */
97#define MTK_CDMP_IG_CTRL 0x400
98#define MTK_CDMP_STAG_EN BIT(0)
99
100/* CDMP Exgress Control Register */
101#define MTK_CDMP_EG_CTRL 0x404
102
103/* GDM Exgress Control Register */
104#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
105#define MTK_GDMA_SPECIAL_TAG BIT(24)
106#define MTK_GDMA_ICS_EN BIT(22)
107#define MTK_GDMA_TCS_EN BIT(21)
108#define MTK_GDMA_UCS_EN BIT(20)
109#define MTK_GDMA_TO_PDMA 0x0
110#define MTK_GDMA_DROP_ALL 0x7777
111
112/* Unicast Filter MAC Address Register - Low */
113#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
114
115/* Unicast Filter MAC Address Register - High */
116#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
117
118/* Internal SRAM offset */
119#define MTK_ETH_SRAM_OFFSET 0x40000
120
121/* FE global misc reg*/
122#define MTK_FE_GLO_MISC 0x124
123
developerfef9efd2021-06-16 18:28:09 +0800124/* PSE Free Queue Flow Control */
125#define PSE_FQFC_CFG1 0x100
126#define PSE_FQFC_CFG2 0x104
developer81bcad32021-07-15 14:14:38 +0800127#define PSE_DROP_CFG 0x108
developerfef9efd2021-06-16 18:28:09 +0800128
developerfd40db22021-04-29 10:08:25 +0800129/* PSE Input Queue Reservation Register*/
130#define PSE_IQ_REV(x) (0x140 + ((x - 1) * 0x4))
131
132/* PSE Output Queue Threshold Register*/
133#define PSE_OQ_TH(x) (0x160 + ((x - 1) * 0x4))
134
developerfef9efd2021-06-16 18:28:09 +0800135/* GDM and CDM Threshold */
136#define MTK_GDM2_THRES 0x1530
137#define MTK_CDMW0_THRES 0x164c
138#define MTK_CDMW1_THRES 0x1650
139#define MTK_CDME0_THRES 0x1654
140#define MTK_CDME1_THRES 0x1658
141#define MTK_CDMM_THRES 0x165c
142
developerfd40db22021-04-29 10:08:25 +0800143#define MTK_PDMA_V2 BIT(4)
developerfd40db22021-04-29 10:08:25 +0800144
developera2bdbd52021-05-31 19:10:17 +0800145#if defined(CONFIG_MEDIATEK_NETSYS_V2)
developerfd40db22021-04-29 10:08:25 +0800146#define PDMA_BASE 0x6000
developerfd40db22021-04-29 10:08:25 +0800147#define QDMA_BASE 0x4400
developer8051e042022-04-08 13:26:36 +0800148#define WDMA_BASE(x) (0x4800 + ((x) * 0x400))
149#define PPE_BASE(x) (0x2200 + ((x) * 0x400))
developerfd40db22021-04-29 10:08:25 +0800150#else
151#define PDMA_BASE 0x0800
152#define QDMA_BASE 0x1800
developer8051e042022-04-08 13:26:36 +0800153#define WDMA_BASE(x) (0x2800 + ((x) * 0x400))
154#define PPE_BASE(x) (0xE00 + ((x) * 0x400))
developerfd40db22021-04-29 10:08:25 +0800155#endif
156/* PDMA RX Base Pointer Register */
157#define MTK_PRX_BASE_PTR0 (PDMA_BASE + 0x100)
158#define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10))
159
160/* PDMA RX Maximum Count Register */
161#define MTK_PRX_MAX_CNT0 (MTK_PRX_BASE_PTR0 + 0x04)
162#define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10))
163
164/* PDMA RX CPU Pointer Register */
165#define MTK_PRX_CRX_IDX0 (MTK_PRX_BASE_PTR0 + 0x08)
166#define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10))
167
developer77f3fd42021-10-05 15:16:05 +0800168/* PDMA RX DMA Pointer Register */
169#define MTK_PRX_DRX_IDX0 (MTK_PRX_BASE_PTR0 + 0x0c)
170#define MTK_PRX_DRX_IDX_CFG(x) (MTK_PRX_DRX_IDX0 + (x * 0x10))
171
developerfd40db22021-04-29 10:08:25 +0800172/* PDMA HW LRO Control Registers */
developer77d03a72021-06-06 00:06:00 +0800173#define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n)))
174#if defined(CONFIG_MEDIATEK_NETSYS_V2)
175#define MTK_MAX_RX_RING_NUM (8)
176#define MTK_HW_LRO_RING_NUM (4)
177#define IS_HW_LRO_RING(ring_no) (((ring_no) > 3) && ((ring_no) < 8))
178#define MTK_PDMA_LRO_CTRL_DW0 (PDMA_BASE + 0x408)
179#define MTK_LRO_ALT_SCORE_DELTA (PDMA_BASE + 0x41c)
180#define MTK_LRO_RX_RING0_CTRL_DW1 (PDMA_BASE + 0x438)
181#define MTK_LRO_RX_RING0_CTRL_DW2 (PDMA_BASE + 0x43c)
182#define MTK_LRO_RX_RING0_CTRL_DW3 (PDMA_BASE + 0x440)
183#define MTK_L3_CKS_UPD_EN BIT(19)
184#define MTK_LRO_CRSN_BNW BIT(22)
185#define MTK_LRO_RING_RELINGUISH_REQ (0xf << 24)
186#define MTK_LRO_RING_RELINGUISH_DONE (0xf << 28)
187#else
188#define MTK_MAX_RX_RING_NUM (4)
189#define MTK_HW_LRO_RING_NUM (3)
190#define IS_HW_LRO_RING(ring_no) (((ring_no) > 0) && ((ring_no) < 4))
191#define MTK_PDMA_LRO_CTRL_DW0 (PDMA_BASE + 0x180)
192#define MTK_LRO_ALT_SCORE_DELTA (PDMA_BASE + 0x24c)
193#define MTK_LRO_RX_RING0_CTRL_DW1 (PDMA_BASE + 0x328)
194#define MTK_LRO_RX_RING0_CTRL_DW2 (PDMA_BASE + 0x32c)
195#define MTK_LRO_RX_RING0_CTRL_DW3 (PDMA_BASE + 0x330)
196#define MTK_LRO_CRSN_BNW BIT(6)
developerfd40db22021-04-29 10:08:25 +0800197#define MTK_L3_CKS_UPD_EN BIT(7)
developer77d03a72021-06-06 00:06:00 +0800198#define MTK_LRO_RING_RELINGUISH_REQ (0x7 << 26)
199#define MTK_LRO_RING_RELINGUISH_DONE (0x7 << 29)
200#endif
201
202#define IS_NORMAL_RING(ring_no) ((ring_no) == 0)
203#define MTK_LRO_EN BIT(0)
developer18f46a82021-07-20 21:08:21 +0800204#define MTK_NON_LRO_MULTI_EN BIT(2)
205#define MTK_LRO_DLY_INT_EN BIT(5)
developerfd40db22021-04-29 10:08:25 +0800206#define MTK_LRO_ALT_PKT_CNT_MODE BIT(21)
developer77d03a72021-06-06 00:06:00 +0800207#define MTK_LRO_L4_CTRL_PSH_EN BIT(23)
208#define MTK_CTRL_DW0_SDL_OFFSET (3)
209#define MTK_CTRL_DW0_SDL_MASK BITS(3, 18)
developerfd40db22021-04-29 10:08:25 +0800210
211#define MTK_PDMA_LRO_CTRL_DW1 (MTK_PDMA_LRO_CTRL_DW0 + 0x04)
212#define MTK_PDMA_LRO_CTRL_DW2 (MTK_PDMA_LRO_CTRL_DW0 + 0x08)
213#define MTK_PDMA_LRO_CTRL_DW3 (MTK_PDMA_LRO_CTRL_DW0 + 0x0c)
214#define MTK_ADMA_MODE BIT(15)
215#define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
216
developer18f46a82021-07-20 21:08:21 +0800217/* PDMA RSS Control Registers */
218#if defined(CONFIG_MEDIATEK_NETSYS_V2)
219#define MTK_PDMA_RSS_GLO_CFG (PDMA_BASE + 0x800)
220#define MTK_RX_NAPI_NUM (2)
221#define MTK_MAX_IRQ_NUM (4)
222#else
223#define MTK_PDMA_RSS_GLO_CFG 0x3000
224#define MTK_RX_NAPI_NUM (1)
225#define MTK_MAX_IRQ_NUM (3)
226#endif
227#define MTK_RSS_RING1 (1)
228#define MTK_RSS_EN BIT(0)
229#define MTK_RSS_CFG_REQ BIT(2)
230#define MTK_RSS_IPV6_STATIC_HASH (0x7 << 8)
231#define MTK_RSS_IPV4_STATIC_HASH (0x7 << 12)
232#define MTK_RSS_INDR_TABLE_DW0 (MTK_PDMA_RSS_GLO_CFG + 0x50)
233#define MTK_RSS_INDR_TABLE_DW1 (MTK_PDMA_RSS_GLO_CFG + 0x54)
234#define MTK_RSS_INDR_TABLE_DW2 (MTK_PDMA_RSS_GLO_CFG + 0x58)
235#define MTK_RSS_INDR_TABLE_DW3 (MTK_PDMA_RSS_GLO_CFG + 0x5C)
236#define MTK_RSS_INDR_TABLE_DW4 (MTK_PDMA_RSS_GLO_CFG + 0x60)
237#define MTK_RSS_INDR_TABLE_DW5 (MTK_PDMA_RSS_GLO_CFG + 0x64)
238#define MTK_RSS_INDR_TABLE_DW6 (MTK_PDMA_RSS_GLO_CFG + 0x68)
239#define MTK_RSS_INDR_TABLE_DW7 (MTK_PDMA_RSS_GLO_CFG + 0x6C)
240#define MTK_RSS_INDR_TABLE_SIZE4 0x44444444
241
developerfd40db22021-04-29 10:08:25 +0800242/* PDMA Global Configuration Register */
243#define MTK_PDMA_GLO_CFG (PDMA_BASE + 0x204)
developer77d03a72021-06-06 00:06:00 +0800244#define MTK_RX_DMA_LRO_EN BIT(8)
developerfd40db22021-04-29 10:08:25 +0800245#define MTK_MULTI_EN BIT(10)
246#define MTK_PDMA_SIZE_8DWORDS (1 << 4)
247
developer77d03a72021-06-06 00:06:00 +0800248/* PDMA Global Configuration Register */
249#define MTK_PDMA_RX_CFG (PDMA_BASE + 0x210)
250#define MTK_PDMA_LRO_SDL (0x3000)
251#define MTK_RX_CFG_SDL_OFFSET (16)
252
developerfd40db22021-04-29 10:08:25 +0800253/* PDMA Reset Index Register */
254#define MTK_PDMA_RST_IDX (PDMA_BASE + 0x208)
255#define MTK_PST_DRX_IDX0 BIT(16)
256#define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x))
257
258/* PDMA Delay Interrupt Register */
259#define MTK_PDMA_DELAY_INT (PDMA_BASE + 0x20c)
260#define MTK_PDMA_DELAY_RX_EN BIT(15)
261#define MTK_PDMA_DELAY_RX_PINT 4
262#define MTK_PDMA_DELAY_RX_PINT_SHIFT 8
263#define MTK_PDMA_DELAY_RX_PTIME 4
264#define MTK_PDMA_DELAY_RX_DELAY \
265 (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \
266 (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT))
267
268/* PDMA Interrupt Status Register */
269#define MTK_PDMA_INT_STATUS (PDMA_BASE + 0x220)
270
271/* PDMA Interrupt Mask Register */
272#define MTK_PDMA_INT_MASK (PDMA_BASE + 0x228)
273
developerfd40db22021-04-29 10:08:25 +0800274/* PDMA Interrupt grouping registers */
275#define MTK_PDMA_INT_GRP1 (PDMA_BASE + 0x250)
276#define MTK_PDMA_INT_GRP2 (PDMA_BASE + 0x254)
developer18f46a82021-07-20 21:08:21 +0800277#if defined(CONFIG_MEDIATEK_NETSYS_V2)
278#define MTK_PDMA_INT_GRP3 (PDMA_BASE + 0x258)
279#else
280#define MTK_PDMA_INT_GRP3 (PDMA_BASE + 0x22c)
281#endif
282#define MTK_LRO_RX1_DLY_INT 0xa70
283#define MTK_MAX_DELAY_INT 0x8f0f8f0f
developerfd40db22021-04-29 10:08:25 +0800284
285/* PDMA HW LRO IP Setting Registers */
developer77d03a72021-06-06 00:06:00 +0800286#if defined(CONFIG_MEDIATEK_NETSYS_V2)
287#define MTK_LRO_RX_RING0_DIP_DW0 (PDMA_BASE + 0x414)
288#else
developerfd40db22021-04-29 10:08:25 +0800289#define MTK_LRO_RX_RING0_DIP_DW0 (PDMA_BASE + 0x304)
developer77d03a72021-06-06 00:06:00 +0800290#endif
developerfd40db22021-04-29 10:08:25 +0800291#define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
292#define MTK_RING_MYIP_VLD BIT(9)
293
developer77d03a72021-06-06 00:06:00 +0800294/* PDMA HW LRO ALT Debug Registers */
295#define MTK_LRO_ALT_DBG (PDMA_BASE + 0x440)
296#define MTK_LRO_ALT_INDEX_OFFSET (8)
297
298/* PDMA HW LRO ALT Data Registers */
299#define MTK_LRO_ALT_DBG_DATA (PDMA_BASE + 0x444)
300
developerfd40db22021-04-29 10:08:25 +0800301/* PDMA HW LRO Ring Control Registers */
developerfd40db22021-04-29 10:08:25 +0800302#define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
303#define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
304#define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
305#define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
306#define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
developer18f46a82021-07-20 21:08:21 +0800307#define MTK_RING_PSE_MODE (1 << 6)
developerfd40db22021-04-29 10:08:25 +0800308#define MTK_RING_AUTO_LERAN_MODE (3 << 6)
309#define MTK_RING_VLD BIT(8)
310#define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
311#define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
312#define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
313
developer77d03a72021-06-06 00:06:00 +0800314/* LRO_RX_RING_CTRL_DW masks */
315#define MTK_LRO_RING_AGG_TIME_MASK BITS(10, 25)
316#define MTK_LRO_RING_AGG_CNT_L_MASK BITS(26, 31)
317#define MTK_LRO_RING_AGG_CNT_H_MASK BITS(0, 1)
318#define MTK_LRO_RING_AGE_TIME_L_MASK BITS(22, 31)
319#define MTK_LRO_RING_AGE_TIME_H_MASK BITS(0, 5)
320
321/* LRO_RX_RING_CTRL_DW0 offsets */
322#define MTK_RX_IPV6_FORCE_OFFSET (0)
323#define MTK_RX_IPV4_FORCE_OFFSET (1)
324
325/* LRO_RX_RING_CTRL_DW1 offsets */
326#define MTK_LRO_RING_AGE_TIME_L_OFFSET (22)
327
328/* LRO_RX_RING_CTRL_DW2 offsets */
329#define MTK_LRO_RING_AGE_TIME_H_OFFSET (0)
330#define MTK_RX_MODE_OFFSET (6)
331#define MTK_RX_PORT_VALID_OFFSET (8)
332#define MTK_RX_MYIP_VALID_OFFSET (9)
333#define MTK_LRO_RING_AGG_TIME_OFFSET (10)
334#define MTK_LRO_RING_AGG_CNT_L_OFFSET (26)
335
336/* LRO_RX_RING_CTRL_DW3 offsets */
337#define MTK_LRO_RING_AGG_CNT_H_OFFSET (0)
338
339/* LRO_RX_RING_STP_DTP_DW offsets */
340#define MTK_RX_TCP_DEST_PORT_OFFSET (0)
341#define MTK_RX_TCP_SRC_PORT_OFFSET (16)
342
developerfd40db22021-04-29 10:08:25 +0800343/* QDMA TX Queue Configuration Registers */
344#define MTK_QTX_CFG(x) (QDMA_BASE + (x * 0x10))
345#define QDMA_RES_THRES 4
346
347/* QDMA TX Queue Scheduler Registers */
348#define MTK_QTX_SCH(x) (QDMA_BASE + 4 + (x * 0x10))
349
350/* QDMA RX Base Pointer Register */
351#define MTK_QRX_BASE_PTR0 (QDMA_BASE + 0x100)
352#define MTK_QRX_BASE_PTR_CFG(x) (MTK_QRX_BASE_PTR0 + ((x) * 0x10))
353
354/* QDMA RX Maximum Count Register */
355#define MTK_QRX_MAX_CNT0 (QDMA_BASE + 0x104)
356#define MTK_QRX_MAX_CNT_CFG(x) (MTK_QRX_MAX_CNT0 + ((x) * 0x10))
357
358/* QDMA RX CPU Pointer Register */
359#define MTK_QRX_CRX_IDX0 (QDMA_BASE + 0x108)
360#define MTK_QRX_CRX_IDX_CFG(x) (MTK_QRX_CRX_IDX0 + ((x) * 0x10))
361
362/* QDMA RX DMA Pointer Register */
363#define MTK_QRX_DRX_IDX0 (QDMA_BASE + 0x10c)
364
365/* QDMA Global Configuration Register */
366#define MTK_QDMA_GLO_CFG (QDMA_BASE + 0x204)
367#define MTK_RX_2B_OFFSET BIT(31)
developer58ab5842022-06-01 15:10:25 +0800368#define MTK_PKT_RX_WDONE BIT(27)
developerfd40db22021-04-29 10:08:25 +0800369#define MTK_RX_BT_32DWORDS (3 << 11)
370#define MTK_NDP_CO_PRO BIT(10)
371#define MTK_TX_WB_DDONE BIT(6)
372#define MTK_DMA_SIZE_16DWORDS (2 << 4)
373#define MTK_DMA_SIZE_32DWORDS (3 << 4)
374#define MTK_RX_DMA_BUSY BIT(3)
375#define MTK_TX_DMA_BUSY BIT(1)
376#define MTK_RX_DMA_EN BIT(2)
377#define MTK_TX_DMA_EN BIT(0)
378#define MTK_DMA_BUSY_TIMEOUT HZ
379
380/* QDMA V2 Global Configuration Register */
381#define MTK_CHK_DDONE_EN BIT(28)
382#define MTK_DMAD_WR_WDONE BIT(26)
383#define MTK_WCOMP_EN BIT(24)
developer2cdef092022-04-15 17:27:55 +0800384#define MTK_RESV_BUF (0x80 << 16)
developerfd40db22021-04-29 10:08:25 +0800385#define MTK_MUTLI_CNT (0x4 << 12)
developer19d84562022-04-21 17:01:06 +0800386#define MTK_RESV_BUF_MASK (0xff << 16)
developerfd40db22021-04-29 10:08:25 +0800387
388/* QDMA Reset Index Register */
389#define MTK_QDMA_RST_IDX (QDMA_BASE + 0x208)
390
391/* QDMA Delay Interrupt Register */
392#define MTK_QDMA_DELAY_INT (QDMA_BASE + 0x20c)
393
394/* QDMA Flow Control Register */
395#define MTK_QDMA_FC_THRES (QDMA_BASE + 0x210)
396#define FC_THRES_DROP_MODE BIT(20)
397#define FC_THRES_DROP_EN (7 << 16)
398#define FC_THRES_MIN 0x4444
399
400/* QDMA Interrupt Status Register */
401#define MTK_QDMA_INT_STATUS (QDMA_BASE + 0x218)
developera2bdbd52021-05-31 19:10:17 +0800402#if defined(CONFIG_MEDIATEK_NETSYS_V2)
developer18f46a82021-07-20 21:08:21 +0800403#define MTK_RX_DONE_INT(ring_no) \
404 ((ring_no)? BIT(16 + (ring_no)) : BIT(14))
developerfd40db22021-04-29 10:08:25 +0800405#else
developer18f46a82021-07-20 21:08:21 +0800406#define MTK_RX_DONE_INT(ring_no) \
407 ((ring_no)? BIT(24 + (ring_no)) : BIT(30))
developerfd40db22021-04-29 10:08:25 +0800408#endif
409#define MTK_RX_DONE_INT3 BIT(19)
410#define MTK_RX_DONE_INT2 BIT(18)
411#define MTK_RX_DONE_INT1 BIT(17)
412#define MTK_RX_DONE_INT0 BIT(16)
413#define MTK_TX_DONE_INT3 BIT(3)
414#define MTK_TX_DONE_INT2 BIT(2)
415#define MTK_TX_DONE_INT1 BIT(1)
416#define MTK_TX_DONE_INT0 BIT(0)
developerfd40db22021-04-29 10:08:25 +0800417#define MTK_TX_DONE_DLY BIT(28)
418#define MTK_TX_DONE_INT MTK_TX_DONE_DLY
419
420/* QDMA Interrupt grouping registers */
421#define MTK_QDMA_INT_GRP1 (QDMA_BASE + 0x220)
422#define MTK_QDMA_INT_GRP2 (QDMA_BASE + 0x224)
423#define MTK_RLS_DONE_INT BIT(0)
424
425/* QDMA Interrupt Status Register */
426#define MTK_QDMA_INT_MASK (QDMA_BASE + 0x21c)
427
developer8051e042022-04-08 13:26:36 +0800428/* QDMA DMA FSM */
429#define MTK_QDMA_FSM (QDMA_BASE + 0x234)
430
developerfd40db22021-04-29 10:08:25 +0800431/* QDMA Interrupt Mask Register */
432#define MTK_QDMA_HRED2 (QDMA_BASE + 0x244)
433
434/* QDMA TX Forward CPU Pointer Register */
435#define MTK_QTX_CTX_PTR (QDMA_BASE +0x300)
436
437/* QDMA TX Forward DMA Pointer Register */
438#define MTK_QTX_DTX_PTR (QDMA_BASE +0x304)
439
developer8051e042022-04-08 13:26:36 +0800440/* QDMA TX Forward DMA Counter */
441#define MTK_QDMA_FWD_CNT (QDMA_BASE + 0x308)
442
developerfd40db22021-04-29 10:08:25 +0800443/* QDMA TX Release CPU Pointer Register */
444#define MTK_QTX_CRX_PTR (QDMA_BASE +0x310)
445
446/* QDMA TX Release DMA Pointer Register */
447#define MTK_QTX_DRX_PTR (QDMA_BASE +0x314)
448
449/* QDMA FQ Head Pointer Register */
450#define MTK_QDMA_FQ_HEAD (QDMA_BASE +0x320)
451
452/* QDMA FQ Head Pointer Register */
453#define MTK_QDMA_FQ_TAIL (QDMA_BASE +0x324)
454
455/* QDMA FQ Free Page Counter Register */
456#define MTK_QDMA_FQ_CNT (QDMA_BASE +0x328)
457
458/* QDMA FQ Free Page Buffer Length Register */
459#define MTK_QDMA_FQ_BLEN (QDMA_BASE +0x32c)
460
developer8051e042022-04-08 13:26:36 +0800461/* WDMA Registers */
462#define MTK_WDMA_DTX_PTR(x) (WDMA_BASE(x) + 0xC)
463#define MTK_WDMA_GLO_CFG(x) (WDMA_BASE(x) + 0x204)
464#define MTK_WDMA_TX_DBG_MON0(x) (WDMA_BASE(x) + 0x230)
465#define MTK_CDM_TXFIFO_RDY BIT(7)
466
developerfd40db22021-04-29 10:08:25 +0800467/* GMA1 Received Good Byte Count Register */
468#if defined(CONFIG_MEDIATEK_NETSYS_V2)
469#define MTK_GDM1_TX_GBCNT 0x1C00
470#else
471#define MTK_GDM1_TX_GBCNT 0x2400
472#endif
473#define MTK_STAT_OFFSET 0x40
474
475/* QDMA TX NUM */
476#define MTK_QDMA_TX_NUM 16
477#define MTK_QDMA_TX_MASK ((MTK_QDMA_TX_NUM) - 1)
478#define QID_LOW_BITS(x) ((x) & 0xf)
479#define QID_HIGH_BITS(x) ((((x) >> 4) & 0x3) << 20)
480#define QID_BITS_V2(x) (((x) & 0x3f) << 16)
481
developerdc0d45f2021-12-27 13:01:22 +0800482#define MTK_QDMA_GMAC2_QID 8
483
developerfd40db22021-04-29 10:08:25 +0800484/* QDMA V2 descriptor txd6 */
485#define TX_DMA_INS_VLAN_V2 BIT(16)
486
487/* QDMA V2 descriptor txd5 */
488#define TX_DMA_CHKSUM_V2 (0x7 << 28)
489#define TX_DMA_TSO_V2 BIT(31)
490
491/* QDMA V2 descriptor txd4 */
492#define TX_DMA_FPORT_SHIFT_V2 8
493#define TX_DMA_FPORT_MASK_V2 0xf
494#define TX_DMA_SWC_V2 BIT(30)
495
496#if defined(CONFIG_MEDIATEK_NETSYS_V2)
497#define MTK_TX_DMA_BUF_LEN 0xffff
498#define MTK_TX_DMA_BUF_SHIFT 8
499#else
500#define MTK_TX_DMA_BUF_LEN 0x3fff
501#define MTK_TX_DMA_BUF_SHIFT 16
502#endif
503
developera2bdbd52021-05-31 19:10:17 +0800504#if defined(CONFIG_MEDIATEK_NETSYS_V2)
developerfd40db22021-04-29 10:08:25 +0800505#define MTK_RX_DMA_BUF_LEN 0xffff
506#define MTK_RX_DMA_BUF_SHIFT 8
507#define RX_DMA_SPORT_SHIFT 26
508#define RX_DMA_SPORT_MASK 0xf
509#else
510#define MTK_RX_DMA_BUF_LEN 0x3fff
511#define MTK_RX_DMA_BUF_SHIFT 16
512#define RX_DMA_SPORT_SHIFT 19
513#define RX_DMA_SPORT_MASK 0x7
514#endif
515
516/* QDMA descriptor txd4 */
517#define TX_DMA_CHKSUM (0x7 << 29)
518#define TX_DMA_TSO BIT(28)
519#define TX_DMA_FPORT_SHIFT 25
520#define TX_DMA_FPORT_MASK 0x7
521#define TX_DMA_INS_VLAN BIT(16)
522
523/* QDMA descriptor txd3 */
524#define TX_DMA_OWNER_CPU BIT(31)
525#define TX_DMA_LS0 BIT(30)
526#define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << MTK_TX_DMA_BUF_SHIFT)
527#define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN)
528#define TX_DMA_SWC BIT(14)
529#define TX_DMA_SDL(_x) (TX_DMA_PLEN0(_x))
530
531/* PDMA on MT7628 */
532#define TX_DMA_DONE BIT(31)
533#define TX_DMA_LS1 BIT(14)
534#define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
535
536/* QDMA descriptor rxd2 */
537#define RX_DMA_DONE BIT(31)
538#define RX_DMA_LSO BIT(30)
539#define RX_DMA_PLEN0(_x) (((_x) & MTK_RX_DMA_BUF_LEN) << MTK_RX_DMA_BUF_SHIFT)
540#define RX_DMA_GET_PLEN0(_x) (((_x) >> MTK_RX_DMA_BUF_SHIFT) & MTK_RX_DMA_BUF_LEN)
developer77d03a72021-06-06 00:06:00 +0800541#define RX_DMA_GET_AGG_CNT(_x) (((_x) >> 2) & 0xff)
542#define RX_DMA_GET_REV(_x) (((_x) >> 10) & 0x1f)
developerfd40db22021-04-29 10:08:25 +0800543#define RX_DMA_VTAG BIT(15)
544
545/* QDMA descriptor rxd3 */
546#define RX_DMA_VID(_x) ((_x) & VLAN_VID_MASK)
547#define RX_DMA_TCI(_x) ((_x) & (VLAN_PRIO_MASK | VLAN_VID_MASK))
548#define RX_DMA_VPID(_x) (((_x) >> 16) & 0xffff)
549
550/* QDMA descriptor rxd4 */
551#define RX_DMA_L4_VALID BIT(24)
552#define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
553#define RX_DMA_SPECIAL_TAG BIT(22) /* switch header in packet */
554
555#define RX_DMA_GET_SPORT(_x) (((_x) >> RX_DMA_SPORT_SHIFT) & RX_DMA_SPORT_MASK)
556
557/* PDMA V2 descriptor rxd3 */
558#define RX_DMA_VTAG_V2 BIT(0)
559#define RX_DMA_L4_VALID_V2 BIT(2)
560
561/* PDMA V2 descriptor rxd4 */
562#define RX_DMA_VID_V2(_x) RX_DMA_VID(_x)
developer255bba22021-07-27 15:16:33 +0800563#define RX_DMA_TCI_V2(_x) RX_DMA_TCI(_x)
564#define RX_DMA_VPID_V2(_x) RX_DMA_VPID(_x)
developerfd40db22021-04-29 10:08:25 +0800565
developer77d03a72021-06-06 00:06:00 +0800566/* PDMA V2 descriptor rxd6 */
567#define RX_DMA_GET_FLUSH_RSN_V2(_x) ((_x) & 0x7)
568#define RX_DMA_GET_AGG_CNT_V2(_x) (((_x) >> 16) & 0xff)
569
developerfd40db22021-04-29 10:08:25 +0800570/* PHY Indirect Access Control registers */
571#define MTK_PHY_IAC 0x10004
572#define PHY_IAC_ACCESS BIT(31)
573#define PHY_IAC_READ BIT(19)
developer599cda42022-05-24 15:13:31 +0800574#define PHY_IAC_READ_C45 (3 << 18)
575#define PHY_IAC_ADDR_C45 (0 << 18)
developerfd40db22021-04-29 10:08:25 +0800576#define PHY_IAC_WRITE BIT(18)
577#define PHY_IAC_START BIT(16)
developer599cda42022-05-24 15:13:31 +0800578#define PHY_IAC_START_C45 (0 << 16)
developerfd40db22021-04-29 10:08:25 +0800579#define PHY_IAC_ADDR_SHIFT 20
580#define PHY_IAC_REG_SHIFT 25
581#define PHY_IAC_TIMEOUT HZ
582
583#define MTK_MAC_MISC 0x1000c
584#define MTK_MUX_TO_ESW BIT(0)
585
586/* Mac control registers */
587#define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
588#define MAC_MCR_MAX_RX_1536 BIT(24)
589#define MAC_MCR_IPG_CFG (BIT(18) | BIT(16))
590#define MAC_MCR_FORCE_MODE BIT(15)
591#define MAC_MCR_TX_EN BIT(14)
592#define MAC_MCR_RX_EN BIT(13)
593#define MAC_MCR_BACKOFF_EN BIT(9)
594#define MAC_MCR_BACKPR_EN BIT(8)
595#define MAC_MCR_FORCE_RX_FC BIT(5)
596#define MAC_MCR_FORCE_TX_FC BIT(4)
597#define MAC_MCR_SPEED_1000 BIT(3)
598#define MAC_MCR_SPEED_100 BIT(2)
599#define MAC_MCR_FORCE_DPX BIT(1)
600#define MAC_MCR_FORCE_LINK BIT(0)
601#define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE)
602
603/* Mac status registers */
604#define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
605#define MAC_MSR_EEE1G BIT(7)
606#define MAC_MSR_EEE100M BIT(6)
607#define MAC_MSR_RX_FC BIT(5)
608#define MAC_MSR_TX_FC BIT(4)
609#define MAC_MSR_SPEED_1000 BIT(3)
610#define MAC_MSR_SPEED_100 BIT(2)
611#define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)
612#define MAC_MSR_DPX BIT(1)
613#define MAC_MSR_LINK BIT(0)
614
615/* TRGMII RXC control register */
616#define TRGMII_RCK_CTRL 0x10300
617#define DQSI0(x) ((x << 0) & GENMASK(6, 0))
618#define DQSI1(x) ((x << 8) & GENMASK(14, 8))
619#define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
620#define RXC_RST BIT(31)
621#define RXC_DQSISEL BIT(30)
622#define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
623#define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2)
624
625#define NUM_TRGMII_CTRL 5
626
627/* TRGMII RXC control register */
628#define TRGMII_TCK_CTRL 0x10340
629#define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
630#define TXC_INV BIT(30)
631#define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2)
632#define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2))
633
634/* TRGMII TX Drive Strength */
635#define TRGMII_TD_ODT(i) (0x10354 + 8 * (i))
636#define TD_DM_DRVP(x) ((x) & 0xf)
637#define TD_DM_DRVN(x) (((x) & 0xf) << 4)
638
639/* TRGMII Interface mode register */
640#define INTF_MODE 0x10390
641#define TRGMII_INTF_DIS BIT(0)
642#define TRGMII_MODE BIT(1)
643#define TRGMII_CENTRAL_ALIGNED BIT(2)
644#define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
645#define INTF_MODE_RGMII_10_100 0
646
647/* GPIO port control registers for GMAC 2*/
648#define GPIO_OD33_CTRL8 0x4c0
649#define GPIO_BIAS_CTRL 0xed0
650#define GPIO_DRV_SEL10 0xf00
651
652/* ethernet subsystem chip id register */
653#define ETHSYS_CHIPID0_3 0x0
654#define ETHSYS_CHIPID4_7 0x4
655#define MT7623_ETH 7623
656#define MT7622_ETH 7622
657#define MT7621_ETH 7621
658
659/* ethernet system control register */
660#define ETHSYS_SYSCFG 0x10
661#define SYSCFG_DRAM_TYPE_DDR2 BIT(4)
662
663/* ethernet subsystem config register */
664#define ETHSYS_SYSCFG0 0x14
665#define SYSCFG0_GE_MASK 0x3
666#define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2)))
667#define SYSCFG0_SGMII_MASK GENMASK(9, 8)
668#define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK)
669#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
670#define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
671#define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
672
673
674/* ethernet subsystem clock register */
675#define ETHSYS_CLKCFG0 0x2c
676#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
677#define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6))
678#define ETHSYS_TRGMII_MT7621_APLL BIT(6)
679#define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5)
680
681/* ethernet reset control register */
developer545abf02021-07-15 17:47:01 +0800682#define ETHSYS_RSTCTRL 0x34
683#define RSTCTRL_FE BIT(6)
developer545abf02021-07-15 17:47:01 +0800684#define RSTCTRL_ETH BIT(23)
developer8051e042022-04-08 13:26:36 +0800685#if defined(CONFIG_MEDIATEK_NETSYS_V2)
686#define RSTCTRL_PPE0 BIT(30)
687#define RSTCTRL_PPE1 BIT(31)
developera5eb8d62022-04-22 15:42:20 +0800688#else
developer8051e042022-04-08 13:26:36 +0800689#define RSTCTRL_PPE0 BIT(31)
developera5eb8d62022-04-22 15:42:20 +0800690#define RSTCTRL_PPE1 0
developer8051e042022-04-08 13:26:36 +0800691#endif
developer545abf02021-07-15 17:47:01 +0800692
693/* ethernet reset check idle register */
694#define ETHSYS_FE_RST_CHK_IDLE_EN 0x28
695
developerfd40db22021-04-29 10:08:25 +0800696
697/* SGMII subsystem config registers */
698/* Register to auto-negotiation restart */
699#define SGMSYS_PCS_CONTROL_1 0x0
700#define SGMII_AN_RESTART BIT(9)
701#define SGMII_ISOLATE BIT(10)
702#define SGMII_AN_ENABLE BIT(12)
703#define SGMII_LINK_STATYS BIT(18)
704#define SGMII_AN_ABILITY BIT(19)
705#define SGMII_AN_COMPLETE BIT(21)
706#define SGMII_PCS_FAULT BIT(23)
707#define SGMII_AN_EXPANSION_CLR BIT(30)
708
709/* Register to programmable link timer, the unit in 2 * 8ns */
710#define SGMSYS_PCS_LINK_TIMER 0x18
711#define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0))
712
713/* Register to control remote fault */
714#define SGMSYS_SGMII_MODE 0x20
715#define SGMII_IF_MODE_BIT0 BIT(0)
716#define SGMII_SPEED_DUPLEX_AN BIT(1)
717#define SGMII_SPEED_10 0x0
718#define SGMII_SPEED_100 BIT(2)
719#define SGMII_SPEED_1000 BIT(3)
720#define SGMII_DUPLEX_FULL BIT(4)
721#define SGMII_IF_MODE_BIT5 BIT(5)
722#define SGMII_REMOTE_FAULT_DIS BIT(8)
723#define SGMII_CODE_SYNC_SET_VAL BIT(9)
724#define SGMII_CODE_SYNC_SET_EN BIT(10)
725#define SGMII_SEND_AN_ERROR_EN BIT(11)
726#define SGMII_IF_MODE_MASK GENMASK(5, 1)
727
728/* Register to set SGMII speed, ANA RG_ Control Signals III*/
729#define SGMSYS_ANA_RG_CS3 0x2028
730#define RG_PHY_SPEED_MASK (BIT(2) | BIT(3))
731#define RG_PHY_SPEED_1_25G 0x0
732#define RG_PHY_SPEED_3_125G BIT(2)
733
734/* Register to power up QPHY */
735#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
736#define SGMII_PHYA_PWD BIT(4)
737
developerf8ac94a2021-07-29 16:40:01 +0800738/* Register to QPHY wrapper control */
739#define SGMSYS_QPHY_WRAP_CTRL 0xec
740#define SGMII_PN_SWAP_MASK GENMASK(1, 0)
741#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1))
742
developerfd40db22021-04-29 10:08:25 +0800743/* Infrasys subsystem config registers */
744#define INFRA_MISC2 0x70c
745#define CO_QPHY_SEL BIT(0)
746#define GEPHY_MAC_SEL BIT(1)
747
developer255bba22021-07-27 15:16:33 +0800748/* Top misc registers */
749#define USB_PHY_SWITCH_REG 0x218
750#define QPHY_SEL_MASK GENMASK(1, 0)
developerf1816a92021-11-15 12:18:02 +0800751#define SGMII_QPHY_SEL 0x2
developer255bba22021-07-27 15:16:33 +0800752
developerfd40db22021-04-29 10:08:25 +0800753/*MDIO control*/
754#define MII_MMD_ACC_CTL_REG 0x0d
755#define MII_MMD_ADDR_DATA_REG 0x0e
756#define MMD_OP_MODE_DATA BIT(14)
757
758/* MT7628/88 specific stuff */
759#define MT7628_PDMA_OFFSET 0x0800
760#define MT7628_SDM_OFFSET 0x0c00
761
762#define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00)
763#define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04)
764#define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08)
765#define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c)
766#define MT7628_PST_DTX_IDX0 BIT(0)
767
768#define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c)
769#define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10)
770
771struct mtk_rx_dma {
772 unsigned int rxd1;
773 unsigned int rxd2;
774 unsigned int rxd3;
775 unsigned int rxd4;
developera2bdbd52021-05-31 19:10:17 +0800776#if defined(CONFIG_MEDIATEK_NETSYS_V2)
developerfd40db22021-04-29 10:08:25 +0800777 unsigned int rxd5;
778 unsigned int rxd6;
779 unsigned int rxd7;
780 unsigned int rxd8;
781#endif
782} __packed __aligned(4);
783
784struct mtk_tx_dma {
785 unsigned int txd1;
786 unsigned int txd2;
787 unsigned int txd3;
788 unsigned int txd4;
789#if defined(CONFIG_MEDIATEK_NETSYS_V2)
790 unsigned int txd5;
791 unsigned int txd6;
792 unsigned int txd7;
793 unsigned int txd8;
794#endif
795} __packed __aligned(4);
796
797struct mtk_eth;
798struct mtk_mac;
799
800/* struct mtk_hw_stats - the structure that holds the traffic statistics.
801 * @stats_lock: make sure that stats operations are atomic
802 * @reg_offset: the status register offset of the SoC
803 * @syncp: the refcount
804 *
805 * All of the supported SoCs have hardware counters for traffic statistics.
806 * Whenever the status IRQ triggers we can read the latest stats from these
807 * counters and store them in this struct.
808 */
809struct mtk_hw_stats {
810 u64 tx_bytes;
811 u64 tx_packets;
812 u64 tx_skip;
813 u64 tx_collisions;
814 u64 rx_bytes;
815 u64 rx_packets;
816 u64 rx_overflow;
817 u64 rx_fcs_errors;
818 u64 rx_short_errors;
819 u64 rx_long_errors;
820 u64 rx_checksum_errors;
821 u64 rx_flow_control_packets;
822
823 spinlock_t stats_lock;
824 u32 reg_offset;
825 struct u64_stats_sync syncp;
826};
827
828enum mtk_tx_flags {
829 /* PDMA descriptor can point at 1-2 segments. This enum allows us to
830 * track how memory was allocated so that it can be freed properly.
831 */
832 MTK_TX_FLAGS_SINGLE0 = 0x01,
833 MTK_TX_FLAGS_PAGE0 = 0x02,
834
835 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted
836 * SKB out instead of looking up through hardware TX descriptor.
837 */
838 MTK_TX_FLAGS_FPORT0 = 0x04,
839 MTK_TX_FLAGS_FPORT1 = 0x08,
840};
841
842/* This enum allows us to identify how the clock is defined on the array of the
843 * clock in the order
844 */
845enum mtk_clks_map {
846 MTK_CLK_ETHIF,
847 MTK_CLK_SGMIITOP,
848 MTK_CLK_ESW,
849 MTK_CLK_GP0,
850 MTK_CLK_GP1,
851 MTK_CLK_GP2,
852 MTK_CLK_FE,
853 MTK_CLK_TRGPLL,
854 MTK_CLK_SGMII_TX_250M,
855 MTK_CLK_SGMII_RX_250M,
856 MTK_CLK_SGMII_CDR_REF,
857 MTK_CLK_SGMII_CDR_FB,
858 MTK_CLK_SGMII2_TX_250M,
859 MTK_CLK_SGMII2_RX_250M,
860 MTK_CLK_SGMII2_CDR_REF,
861 MTK_CLK_SGMII2_CDR_FB,
862 MTK_CLK_SGMII_CK,
863 MTK_CLK_ETH2PLL,
864 MTK_CLK_WOCPU0,
865 MTK_CLK_WOCPU1,
866 MTK_CLK_MAX
867};
868
869#define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
870 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
871 BIT(MTK_CLK_TRGPLL))
872#define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
873 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
874 BIT(MTK_CLK_GP2) | \
875 BIT(MTK_CLK_SGMII_TX_250M) | \
876 BIT(MTK_CLK_SGMII_RX_250M) | \
877 BIT(MTK_CLK_SGMII_CDR_REF) | \
878 BIT(MTK_CLK_SGMII_CDR_FB) | \
879 BIT(MTK_CLK_SGMII_CK) | \
880 BIT(MTK_CLK_ETH2PLL))
881#define MT7621_CLKS_BITMAP (0)
882#define MT7628_CLKS_BITMAP (0)
883#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
884 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
885 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
886 BIT(MTK_CLK_SGMII_TX_250M) | \
887 BIT(MTK_CLK_SGMII_RX_250M) | \
888 BIT(MTK_CLK_SGMII_CDR_REF) | \
889 BIT(MTK_CLK_SGMII_CDR_FB) | \
890 BIT(MTK_CLK_SGMII2_TX_250M) | \
891 BIT(MTK_CLK_SGMII2_RX_250M) | \
892 BIT(MTK_CLK_SGMII2_CDR_REF) | \
893 BIT(MTK_CLK_SGMII2_CDR_FB) | \
894 BIT(MTK_CLK_SGMII_CK) | \
895 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
896
897#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
898 BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
899 BIT(MTK_CLK_SGMII_TX_250M) | \
900 BIT(MTK_CLK_SGMII_RX_250M) | \
901 BIT(MTK_CLK_SGMII_CDR_REF) | \
902 BIT(MTK_CLK_SGMII_CDR_FB) | \
903 BIT(MTK_CLK_SGMII2_TX_250M) | \
904 BIT(MTK_CLK_SGMII2_RX_250M) | \
905 BIT(MTK_CLK_SGMII2_CDR_REF) | \
906 BIT(MTK_CLK_SGMII2_CDR_FB))
907
developer255bba22021-07-27 15:16:33 +0800908
developer9e9fb4c2021-11-30 17:33:04 +0800909#define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
910 BIT(MTK_CLK_WOCPU0) | \
911 BIT(MTK_CLK_SGMII_TX_250M) | \
912 BIT(MTK_CLK_SGMII_RX_250M) | \
913 BIT(MTK_CLK_SGMII_CDR_REF) | \
914 BIT(MTK_CLK_SGMII_CDR_FB) | \
915 BIT(MTK_CLK_SGMII2_TX_250M) | \
916 BIT(MTK_CLK_SGMII2_RX_250M) | \
917 BIT(MTK_CLK_SGMII2_CDR_REF) | \
918 BIT(MTK_CLK_SGMII2_CDR_FB))
developerfd40db22021-04-29 10:08:25 +0800919enum mtk_dev_state {
920 MTK_HW_INIT,
921 MTK_RESETTING
922};
923
924/* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at
925 * by the TX descriptor s
926 * @skb: The SKB pointer of the packet being sent
927 * @dma_addr0: The base addr of the first segment
928 * @dma_len0: The length of the first segment
929 * @dma_addr1: The base addr of the second segment
930 * @dma_len1: The length of the second segment
931 */
932struct mtk_tx_buf {
933 struct sk_buff *skb;
934 u32 flags;
935 DEFINE_DMA_UNMAP_ADDR(dma_addr0);
936 DEFINE_DMA_UNMAP_LEN(dma_len0);
937 DEFINE_DMA_UNMAP_ADDR(dma_addr1);
938 DEFINE_DMA_UNMAP_LEN(dma_len1);
939};
940
941/* struct mtk_tx_ring - This struct holds info describing a TX ring
942 * @dma: The descriptor ring
943 * @buf: The memory pointed at by the ring
944 * @phys: The physical addr of tx_buf
945 * @next_free: Pointer to the next free descriptor
946 * @last_free: Pointer to the last free descriptor
developerc4671b22021-05-28 13:16:42 +0800947 * @last_free_ptr: Hardware pointer value of the last free descriptor
developerfd40db22021-04-29 10:08:25 +0800948 * @thresh: The threshold of minimum amount of free descriptors
949 * @free_count: QDMA uses a linked list. Track how many free descriptors
950 * are present
951 */
952struct mtk_tx_ring {
953 struct mtk_tx_dma *dma;
954 struct mtk_tx_buf *buf;
955 dma_addr_t phys;
956 struct mtk_tx_dma *next_free;
957 struct mtk_tx_dma *last_free;
developerc4671b22021-05-28 13:16:42 +0800958 u32 last_free_ptr;
developerfd40db22021-04-29 10:08:25 +0800959 u16 thresh;
960 atomic_t free_count;
961 int dma_size;
962 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */
963 dma_addr_t phys_pdma;
964 int cpu_idx;
965};
966
967/* PDMA rx ring mode */
968enum mtk_rx_flags {
969 MTK_RX_FLAGS_NORMAL = 0,
970 MTK_RX_FLAGS_HWLRO,
971 MTK_RX_FLAGS_QDMA,
972};
973
974/* struct mtk_rx_ring - This struct holds info describing a RX ring
975 * @dma: The descriptor ring
976 * @data: The memory pointed at by the ring
977 * @phys: The physical addr of rx_buf
978 * @frag_size: How big can each fragment be
979 * @buf_size: The size of each packet buffer
980 * @calc_idx: The current head of ring
developer77d03a72021-06-06 00:06:00 +0800981 * @ring_no: The index of ring
developerfd40db22021-04-29 10:08:25 +0800982 */
983struct mtk_rx_ring {
984 struct mtk_rx_dma *dma;
985 u8 **data;
986 dma_addr_t phys;
987 u16 frag_size;
988 u16 buf_size;
989 u16 dma_size;
990 bool calc_idx_update;
991 u16 calc_idx;
992 u32 crx_idx_reg;
developer77d03a72021-06-06 00:06:00 +0800993 u32 ring_no;
developerfd40db22021-04-29 10:08:25 +0800994};
995
developer18f46a82021-07-20 21:08:21 +0800996/* struct mtk_napi - This is the structure holding NAPI-related information,
997 * and a mtk_napi struct is binding to one interrupt group
998 * @napi: The NAPI struct
999 * @rx_ring: Pointer to the memory holding info about the RX ring
1000 * @irq_grp_idx: The index indicates which interrupt group that this
1001 * mtk_napi is binding to
1002 */
1003struct mtk_napi {
1004 struct napi_struct napi;
1005 struct mtk_eth *eth;
1006 struct mtk_rx_ring *rx_ring;
1007 u32 irq_grp_no;
1008};
1009
developerfd40db22021-04-29 10:08:25 +08001010enum mkt_eth_capabilities {
1011 MTK_RGMII_BIT = 0,
1012 MTK_TRGMII_BIT,
1013 MTK_SGMII_BIT,
1014 MTK_ESW_BIT,
1015 MTK_GEPHY_BIT,
1016 MTK_MUX_BIT,
1017 MTK_INFRA_BIT,
1018 MTK_SHARED_SGMII_BIT,
1019 MTK_HWLRO_BIT,
developer18f46a82021-07-20 21:08:21 +08001020 MTK_RSS_BIT,
developerfd40db22021-04-29 10:08:25 +08001021 MTK_SHARED_INT_BIT,
1022 MTK_TRGMII_MT7621_CLK_BIT,
1023 MTK_QDMA_BIT,
developera2bdbd52021-05-31 19:10:17 +08001024 MTK_NETSYS_V2_BIT,
developerfd40db22021-04-29 10:08:25 +08001025 MTK_SOC_MT7628_BIT,
developer545abf02021-07-15 17:47:01 +08001026 MTK_RSTCTRL_PPE1_BIT,
developer255bba22021-07-27 15:16:33 +08001027 MTK_U3_COPHY_V2_BIT,
developerfd40db22021-04-29 10:08:25 +08001028
1029 /* MUX BITS*/
1030 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
1031 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
1032 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
1033 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
1034 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
1035
1036 /* PATH BITS */
1037 MTK_ETH_PATH_GMAC1_RGMII_BIT,
1038 MTK_ETH_PATH_GMAC1_TRGMII_BIT,
1039 MTK_ETH_PATH_GMAC1_SGMII_BIT,
1040 MTK_ETH_PATH_GMAC2_RGMII_BIT,
1041 MTK_ETH_PATH_GMAC2_SGMII_BIT,
1042 MTK_ETH_PATH_GMAC2_GEPHY_BIT,
1043 MTK_ETH_PATH_GDM1_ESW_BIT,
1044};
1045
1046/* Supported hardware group on SoCs */
1047#define MTK_RGMII BIT(MTK_RGMII_BIT)
1048#define MTK_TRGMII BIT(MTK_TRGMII_BIT)
1049#define MTK_SGMII BIT(MTK_SGMII_BIT)
1050#define MTK_ESW BIT(MTK_ESW_BIT)
1051#define MTK_GEPHY BIT(MTK_GEPHY_BIT)
1052#define MTK_MUX BIT(MTK_MUX_BIT)
1053#define MTK_INFRA BIT(MTK_INFRA_BIT)
1054#define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT)
1055#define MTK_HWLRO BIT(MTK_HWLRO_BIT)
developer18f46a82021-07-20 21:08:21 +08001056#define MTK_RSS BIT(MTK_RSS_BIT)
developerfd40db22021-04-29 10:08:25 +08001057#define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT)
1058#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
1059#define MTK_QDMA BIT(MTK_QDMA_BIT)
developera2bdbd52021-05-31 19:10:17 +08001060#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
developerfd40db22021-04-29 10:08:25 +08001061#define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
developer545abf02021-07-15 17:47:01 +08001062#define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT)
developer255bba22021-07-27 15:16:33 +08001063#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT)
developerfd40db22021-04-29 10:08:25 +08001064
1065#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
1066 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
1067#define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \
1068 BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
1069#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
1070 BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
1071#define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
1072 BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
1073#define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
1074 BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
1075
1076/* Supported path present on SoCs */
1077#define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT)
1078#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
1079#define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT)
1080#define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT)
1081#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
1082#define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
1083#define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT)
1084
1085#define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
1086#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
1087#define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII)
1088#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
1089#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
1090#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
1091#define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
1092
1093/* MUXes present on SoCs */
1094/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
1095#define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX)
1096
1097/* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */
1098#define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \
1099 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA)
1100
1101/* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
1102#define MTK_MUX_U3_GMAC2_TO_QPHY \
1103 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA)
1104
1105/* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */
1106#define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
1107 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
1108 MTK_SHARED_SGMII)
1109
1110/* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
1111#define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
1112 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
1113
1114#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
1115
1116#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
1117 MTK_GMAC2_RGMII | MTK_SHARED_INT | \
1118 MTK_TRGMII_MT7621_CLK | MTK_QDMA)
1119
1120#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
1121 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
1122 MTK_MUX_GDM1_TO_GMAC1_ESW | \
1123 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA)
1124
1125#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \
1126 MTK_QDMA)
1127
1128#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628)
1129
1130#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
1131 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
1132 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
1133 MTK_MUX_U3_GMAC2_TO_QPHY | \
1134 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
1135
developerfd40db22021-04-29 10:08:25 +08001136#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
1137 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
developer8051e042022-04-08 13:26:36 +08001138 MTK_NETSYS_V2)
developerfd40db22021-04-29 10:08:25 +08001139
developer255bba22021-07-27 15:16:33 +08001140#define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
1141 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
1142 MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
1143 MTK_NETSYS_V2)
1144
developerfd40db22021-04-29 10:08:25 +08001145/* struct mtk_eth_data - This is the structure holding all differences
1146 * among various plaforms
1147 * @ana_rgc3: The offset for register ANA_RGC3 related to
1148 * sgmiisys syscon
1149 * @caps Flags shown the extra capability for the SoC
1150 * @hw_features Flags shown HW features
1151 * @required_clks Flags shown the bitmap for required clocks on
1152 * the target SoC
1153 * @required_pctl A bool value to show whether the SoC requires
1154 * the extra setup for those pins used by GMAC.
1155 */
1156struct mtk_soc_data {
1157 u32 ana_rgc3;
1158 u32 caps;
1159 u32 required_clks;
1160 bool required_pctl;
1161 netdev_features_t hw_features;
1162 bool has_sram;
1163};
1164
1165/* currently no SoC has more than 2 macs */
1166#define MTK_MAX_DEVS 2
1167
1168#define MTK_SGMII_PHYSPEED_AN BIT(31)
1169#define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0)
1170#define MTK_SGMII_PHYSPEED_1000 BIT(0)
1171#define MTK_SGMII_PHYSPEED_2500 BIT(1)
developerf8ac94a2021-07-29 16:40:01 +08001172#define MTK_SGMII_PN_SWAP BIT(16)
developerfd40db22021-04-29 10:08:25 +08001173#define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x))
1174
1175/* struct mtk_sgmii - This is the structure holding sgmii regmap and its
1176 * characteristics
1177 * @regmap: The register map pointing at the range used to setup
1178 * SGMII modes
1179 * @flags: The enum refers to which mode the sgmii wants to run on
1180 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
1181 */
1182
1183struct mtk_sgmii {
1184 struct regmap *regmap[MTK_MAX_DEVS];
1185 u32 flags[MTK_MAX_DEVS];
1186 u32 ana_rgc3;
1187};
1188
developer8051e042022-04-08 13:26:36 +08001189
1190/* struct mtk_reset_event - This is the structure holding statistics counters
1191 * for reset events
1192 * @count: The counter is used to record the number of events
1193 */
1194struct mtk_reset_event {
1195 u32 count[32];
1196};
1197
developerfd40db22021-04-29 10:08:25 +08001198/* struct mtk_eth - This is the main datasructure for holding the state
1199 * of the driver
1200 * @dev: The device pointer
1201 * @base: The mapped register i/o base
1202 * @page_lock: Make sure that register operations are atomic
1203 * @tx_irq__lock: Make sure that IRQ register operations are atomic
1204 * @rx_irq__lock: Make sure that IRQ register operations are atomic
1205 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a
1206 * dummy for NAPI to work
1207 * @netdev: The netdev instances
1208 * @mac: Each netdev is linked to a physical MAC
1209 * @irq: The IRQ that we are using
1210 * @msg_enable: Ethtool msg level
1211 * @ethsys: The register map pointing at the range used to setup
1212 * MII modes
1213 * @infra: The register map pointing at the range used to setup
1214 * SGMII and GePHY path
1215 * @pctl: The register map pointing at the range used to setup
1216 * GMAC port drive/slew values
1217 * @dma_refcnt: track how many netdevs are using the DMA engine
1218 * @tx_ring: Pointer to the memory holding info about the TX ring
1219 * @rx_ring: Pointer to the memory holding info about the RX ring
1220 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring
1221 * @tx_napi: The TX NAPI struct
1222 * @rx_napi: The RX NAPI struct
1223 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring
1224 * @phy_scratch_ring: physical address of scratch_ring
1225 * @scratch_head: The scratch memory that scratch_ring points to.
1226 * @clks: clock array for all clocks required
1227 * @mii_bus: If there is a bus we need to create an instance for it
1228 * @pending_work: The workqueue used to reset the dma ring
1229 * @state: Initialization and runtime state of the device
1230 * @soc: Holding specific data among vaious SoCs
1231 */
1232
1233struct mtk_eth {
1234 struct device *dev;
1235 void __iomem *base;
1236 spinlock_t page_lock;
1237 spinlock_t tx_irq_lock;
1238 spinlock_t rx_irq_lock;
1239 struct net_device dummy_dev;
1240 struct net_device *netdev[MTK_MAX_DEVS];
1241 struct mtk_mac *mac[MTK_MAX_DEVS];
developer18f46a82021-07-20 21:08:21 +08001242 int irq[MTK_MAX_IRQ_NUM];
developerfd40db22021-04-29 10:08:25 +08001243 u32 msg_enable;
1244 unsigned long sysclk;
1245 struct regmap *ethsys;
1246 struct regmap *infra;
1247 struct mtk_sgmii *sgmii;
1248 struct regmap *pctl;
1249 bool hwlro;
1250 refcount_t dma_refcnt;
1251 struct mtk_tx_ring tx_ring;
1252 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM];
1253 struct mtk_rx_ring rx_ring_qdma;
1254 struct napi_struct tx_napi;
developer18f46a82021-07-20 21:08:21 +08001255 struct mtk_napi rx_napi[MTK_RX_NAPI_NUM];
developerfd40db22021-04-29 10:08:25 +08001256 struct mtk_tx_dma *scratch_ring;
developer8051e042022-04-08 13:26:36 +08001257 struct mtk_reset_event reset_event;
developerfd40db22021-04-29 10:08:25 +08001258 dma_addr_t phy_scratch_ring;
1259 void *scratch_head;
1260 struct clk *clks[MTK_CLK_MAX];
1261
1262 struct mii_bus *mii_bus;
1263 struct work_struct pending_work;
1264 unsigned long state;
1265
1266 const struct mtk_soc_data *soc;
1267
1268 u32 tx_int_mask_reg;
1269 u32 tx_int_status_reg;
1270 u32 rx_dma_l4_valid;
1271 int ip_align;
developerd82e8372022-02-09 15:00:09 +08001272 spinlock_t syscfg0_lock;
developer8051e042022-04-08 13:26:36 +08001273 struct timer_list mtk_dma_monitor_timer;
developerfd40db22021-04-29 10:08:25 +08001274};
1275
1276/* struct mtk_mac - the structure that holds the info about the MACs of the
1277 * SoC
1278 * @id: The number of the MAC
1279 * @interface: Interface mode kept for detecting change in hw settings
1280 * @of_node: Our devicetree node
1281 * @hw: Backpointer to our main datastruture
1282 * @hw_stats: Packet statistics counter
1283 */
1284struct mtk_mac {
developerfb556ca2021-10-13 10:52:09 +08001285 unsigned int id;
developerfd40db22021-04-29 10:08:25 +08001286 phy_interface_t interface;
1287 unsigned int mode;
1288 int speed;
1289 struct device_node *of_node;
1290 struct phylink *phylink;
1291 struct phylink_config phylink_config;
1292 struct mtk_eth *hw;
1293 struct mtk_hw_stats *hw_stats;
1294 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
1295 int hwlro_ip_cnt;
1296};
1297
1298/* the struct describing the SoC. these are declared in the soc_xyz.c files */
1299extern const struct of_device_id of_mtk_match[];
developer77d03a72021-06-06 00:06:00 +08001300extern u32 mtk_hwlro_stats_ebl;
developerfd40db22021-04-29 10:08:25 +08001301
1302/* read the hardware status register */
1303void mtk_stats_update_mac(struct mtk_mac *mac);
1304
1305void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
1306u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
developer8051e042022-04-08 13:26:36 +08001307u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg);
developerfd40db22021-04-29 10:08:25 +08001308
1309int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
1310 u32 ana_rgc3);
developerd8b55b62021-10-13 17:09:12 +08001311int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, unsigned int id);
1312int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, unsigned int id,
developerfd40db22021-04-29 10:08:25 +08001313 const struct phylink_link_state *state);
1314void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id);
1315
1316int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
1317int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
1318int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
developer8051e042022-04-08 13:26:36 +08001319void mtk_gdm_config(struct mtk_eth *eth, u32 config);
1320void ethsys_reset(struct mtk_eth *eth, u32 reset_bits);
developerfd40db22021-04-29 10:08:25 +08001321
1322#endif /* MTK_ETH_H */