[][[Jaguar][Eagle] reset recovery]
[Description]
Add ETH Reset for device recovery when detected erro
[Release-log]
-- sync panther-cheetah eth reset
-- refine error detect func
-- refine pending work flow
Change-Id: Ibac85bcca21f711586d9b9af246da1c789062425
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6969361
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index b617c13..dc02870 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -494,11 +494,18 @@
#define MTK_QDMA_FQ_BLEN (QDMA_BASE +0x32c)
/* WDMA Registers */
+#define MTK_WDMA_CTX_PTR(x) (WDMA_BASE(x) + 0x8)
#define MTK_WDMA_DTX_PTR(x) (WDMA_BASE(x) + 0xC)
#define MTK_WDMA_GLO_CFG(x) (WDMA_BASE(x) + 0x204)
#define MTK_WDMA_TX_DBG_MON0(x) (WDMA_BASE(x) + 0x230)
+#define MTK_WDMA_RX_DBG_MON1(x) (WDMA_BASE(x) + 0x3c4)
+#define MTK_WDMA_CRX_PTR(x) (WDMA_BASE(x) + 0x108)
+#define MTK_WDMA_DRX_PTR(x) (WDMA_BASE(x) + 0x10C)
#define MTK_CDM_TXFIFO_RDY BIT(7)
+/*TDMA Register*/
+#define MTK_TDMA_GLO_CFG (0x6204)
+
/* GMA1 Received Good Byte Count Register */
#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
#define MTK_GDM1_TX_GBCNT 0x1C00
@@ -754,9 +761,16 @@
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#define RSTCTRL_PPE0 BIT(30)
#define RSTCTRL_PPE1 BIT(31)
+#elif defined(CONFIG_MEDIATEK_NETSYS_V3)
+#define RSTCTRL_PPE0 BIT(29)
+#define RSTCTRL_PPE1 BIT(30)
+#define RSTCTRL_PPE2 BIT(31)
+#define RSTCTRL_WDMA0 BIT(24)
+#define RSTCTRL_WDMA1 BIT(25)
+#define RSTCTRL_WDMA2 BIT(26)
#else
#define RSTCTRL_PPE0 BIT(31)
-#define RSTCTRL_PPE1 0
+#define RSTCTRL_PPE1 0
#endif
/* ethernet reset check idle register */
@@ -1241,6 +1255,7 @@
MTK_NETSYS_V3_BIT,
MTK_SOC_MT7628_BIT,
MTK_RSTCTRL_PPE1_BIT,
+ MTK_RSTCTRL_PPE2_BIT,
MTK_U3_COPHY_V2_BIT,
MTK_8GB_ADDRESSING_BIT,
@@ -1290,6 +1305,7 @@
#define MTK_NETSYS_V3 BIT_ULL(MTK_NETSYS_V3_BIT)
#define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT)
#define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
+#define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
#define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT)
#define MTK_8GB_ADDRESSING BIT_ULL(MTK_8GB_ADDRESSING_BIT)
@@ -1401,7 +1417,7 @@
#define MT7988_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC3_SGMII | \
MTK_MUX_GMAC123_TO_GEPHY_SGMII | MTK_QDMA | \
- MTK_NETSYS_V3 | MTK_RSTCTRL_PPE1 | \
+ MTK_NETSYS_V3 | MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | \
MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII | \
MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII | \
MTK_GMAC2_XGMII | MTK_MUX_GMAC2_TO_XGMII | MTK_RSS)