blob: 2242ed9184b689b132cf8be000480454cafa7f5f [file] [log] [blame]
Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stuebnerfc367852019-07-16 22:18:21 +02003config ROCKCHIP_PX30
4 bool "Support Rockchip PX30"
5 select ARM64
Quentin Schulz1e9fc7b2024-05-24 11:23:33 +02006 imply OF_UPSTREAM
Heiko Stuebnerfc367852019-07-16 22:18:21 +02007 select SUPPORT_SPL
8 select SUPPORT_TPL
9 select SPL
10 select TPL
11 select TPL_TINY_FRAMEWORK if TPL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020012 select TPL_NEEDS_SEPARATE_STACK if TPL
13 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -060014 select SPL_SERIAL
15 select TPL_SERIAL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020016 select DEBUG_UART_BOARD_INIT
17 imply ROCKCHIP_COMMON_BOARD
18 imply SPL_ROCKCHIP_COMMON_BOARD
Quentin Schulz99496082024-06-14 13:04:55 +020019 imply ARMV8_CRYPTO
20 imply ARMV8_SET_SMPEN
Heiko Stuebnerfc367852019-07-16 22:18:21 +020021 help
22 The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
23 including NEON and GPU, Mali-400 graphics, several DDR3 options
24 and video codec support. Peripherals include Gigabit Ethernet,
25 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
26
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020027config ROCKCHIP_RK3036
28 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053029 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +080030 select SUPPORT_SPL
31 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +080032 imply USB_FUNCTION_ROCKUSB
33 imply CMD_ROCKUSB
Kever Yang427cb672019-07-22 20:02:04 +080034 imply ROCKCHIP_COMMON_BOARD
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020035 help
36 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
37 including NEON and GPU, Mali-400 graphics, several DDR3 options
38 and video codec support. Peripherals include Gigabit Ethernet,
39 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
40
Johan Jonkera289fc72022-04-16 17:09:47 +020041config ROCKCHIP_RK3066
42 bool "Support Rockchip RK3066"
43 select CPU_V7A
44 select SPL_BOARD_INIT if SPL
45 select SUPPORT_SPL
46 select SUPPORT_TPL
47 select SPL
48 select TPL
49 select TPL_ROCKCHIP_BACK_TO_BROM
50 select TPL_ROCKCHIP_EARLYRETURN_TO_BROM
51 imply ROCKCHIP_COMMON_BOARD
52 imply SPL_ROCKCHIP_COMMON_BOARD
53 imply SPL_SERIAL
54 imply TPL_ROCKCHIP_COMMON_BOARD
55 imply TPL_SERIAL
56 help
57 The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
58 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
59 video interfaces, several memory options and video codec support.
60 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
61 UART, SPI, I2C and PWMs.
62
Kever Yangaa827752017-11-28 16:04:16 +080063config ROCKCHIP_RK3128
64 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053065 select CPU_V7A
Kever Yang96362722019-07-22 20:02:05 +080066 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa827752017-11-28 16:04:16 +080067 help
68 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
69 including NEON and GPU, Mali-400 graphics, several DDR3 options
70 and video codec support. Peripherals include Gigabit Ethernet,
71 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
72
Heiko Stübneref6db5e2017-02-18 19:46:36 +010073config ROCKCHIP_RK3188
74 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053075 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080076 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010077 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010078 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020079 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020080 select SPL_REGMAP
81 select SPL_SYSCON
82 select SPL_RAM
Simon Glass284cb9c2021-07-10 21:14:31 -060083 select SPL_DRIVERS_MISC
Philipp Tomsich16c689c2017-10-10 16:21:15 +020084 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangbd8532e2019-07-22 19:59:15 +080085 select SPL_ROCKCHIP_BACK_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020086 select BOARD_LATE_INIT
Kever Yangbfd3f872019-07-22 20:02:09 +080087 imply ROCKCHIP_COMMON_BOARD
Kever Yang3bd90402019-07-22 19:59:18 +080088 imply SPL_ROCKCHIP_COMMON_BOARD
Heiko Stübneref6db5e2017-02-18 19:46:36 +010089 help
90 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
91 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
92 video interfaces, several memory options and video codec support.
93 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
94 UART, SPI, I2C and PWMs.
95
Kever Yang57d4dbf2017-06-23 17:17:52 +080096config ROCKCHIP_RK322X
97 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053098 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080099 select SUPPORT_SPL
Kever Yangaff40c62019-04-02 20:41:24 +0800100 select SUPPORT_TPL
Kever Yang57d4dbf2017-06-23 17:17:52 +0800101 select SPL
Kever Yangaff40c62019-04-02 20:41:24 +0800102 select SPL_DM
103 select SPL_OF_LIBFDT
104 select TPL
105 select TPL_DM
106 select TPL_OF_LIBFDT
Kever Yangaff40c62019-04-02 20:41:24 +0800107 select TPL_NEEDS_SEPARATE_STACK if TPL
Simon Glass284cb9c2021-07-10 21:14:31 -0600108 select SPL_DRIVERS_MISC
Kever Yang0b517732019-07-22 20:02:07 +0800109 imply ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600110 imply SPL_SERIAL
Kever Yangd877fd22019-07-22 19:59:20 +0800111 imply SPL_ROCKCHIP_COMMON_BOARD
Alex Bee4fe31122023-07-18 16:57:13 +0200112 select SPL_OPTEE_IMAGE if SPL_FIT
Simon Glassf4d60392021-08-08 12:20:12 -0600113 imply TPL_SERIAL
Kever Yang466f3fd2019-07-09 22:05:56 +0800114 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +0800115 select TPL_LIBCOMMON_SUPPORT
116 select TPL_LIBGENERIC_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +0800117 help
118 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
119 including NEON and GPU, Mali-400 graphics, several DDR3 options
120 and video codec support. Peripherals include Gigabit Ethernet,
121 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
122
Simon Glass2cffe662015-08-30 16:55:38 -0600123config ROCKCHIP_RK3288
124 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530125 select CPU_V7A
John Keepingd5cb7712023-02-23 19:28:51 +0000126 select OF_SYSTEM_SETUP
Tom Rinie1e85442021-08-27 21:18:30 -0400127 select SKIP_LOWLEVEL_INIT_ONLY
Kever Yang0d3d7832016-07-19 21:16:59 +0800128 select SUPPORT_SPL
129 select SPL
Kever Yangf7c0a332019-07-02 11:43:05 +0800130 select SUPPORT_TPL
Johan Jonker9a26fb12023-12-27 13:06:47 +0100131 select FDT_64BIT
Jagan Teki7b7cc952020-01-23 19:42:19 +0530132 imply PRE_CONSOLE_BUFFER
Kever Yangba875012019-07-22 20:02:15 +0800133 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa67deb2019-07-22 19:59:27 +0800134 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +0800135 imply TPL_CLK
136 imply TPL_DM
Simon Glass284cb9c2021-07-10 21:14:31 -0600137 imply TPL_DRIVERS_MISC
Kever Yangf7c0a332019-07-02 11:43:05 +0800138 imply TPL_LIBCOMMON_SUPPORT
139 imply TPL_LIBGENERIC_SUPPORT
Kever Yangb36e7092019-07-02 11:43:06 +0800140 imply TPL_NEEDS_SEPARATE_STACK
Kever Yangf7c0a332019-07-02 11:43:05 +0800141 imply TPL_OF_CONTROL
142 imply TPL_OF_PLATDATA
143 imply TPL_RAM
144 imply TPL_REGMAP
Kever Yange32f38e2019-07-09 22:05:57 +0800145 imply TPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600146 imply TPL_SERIAL
Kever Yangf7c0a332019-07-02 11:43:05 +0800147 imply TPL_SYSCON
Eddie Caib3501fe2017-12-15 08:17:13 +0800148 imply USB_FUNCTION_ROCKUSB
149 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -0600150 help
151 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
152 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
153 video interfaces supporting HDMI and eDP, several DDR3 options
154 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +0100155 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -0600156
Andy Yanb5e16302019-11-14 11:21:12 +0800157config ROCKCHIP_RK3308
158 bool "Support Rockchip RK3308"
159 select ARM64
Andy Yanb5e16302019-11-14 11:21:12 +0800160 select SUPPORT_SPL
161 select SUPPORT_TPL
162 select SPL
163 select SPL_ATF
164 select SPL_ATF_NO_PLATFORM_PARAM
165 select SPL_LOAD_FIT
Jonas Karlmana2caa162024-04-08 18:14:00 +0000166 imply ARMV8_CRYPTO
167 imply ARMV8_SET_SMPEN
Jonas Karlmanfbced692024-04-08 18:14:02 +0000168 imply DM_RNG
Jonas Karlmana2caa162024-04-08 18:14:00 +0000169 imply LEGACY_IMAGE_FORMAT
Jonas Karlman1cf34dd2024-04-08 18:14:01 +0000170 imply MISC
171 imply MISC_INIT_R
Jonas Karlman0cab3c52024-05-04 19:42:53 +0000172 imply OF_UPSTREAM
Jonas Karlmanfbced692024-04-08 18:14:02 +0000173 imply RNG_ROCKCHIP
Andy Yanb5e16302019-11-14 11:21:12 +0800174 imply ROCKCHIP_COMMON_BOARD
Jonas Karlman1cf34dd2024-04-08 18:14:01 +0000175 imply ROCKCHIP_OTP
Andy Yanb5e16302019-11-14 11:21:12 +0800176 imply SPL_CLK
Jonas Karlmana499c982024-04-08 18:14:03 +0000177 imply SPL_DM_SEQ_ALIAS
Jonas Karlmana2caa162024-04-08 18:14:00 +0000178 imply SPL_FIT_SIGNATURE
Jonas Karlmana499c982024-04-08 18:14:03 +0000179 imply SPL_PINCTRL
Andy Yanb5e16302019-11-14 11:21:12 +0800180 imply SPL_RAM
Jonas Karlman16b0f902024-04-08 18:13:59 +0000181 imply SPL_REGMAP
182 imply SPL_ROCKCHIP_COMMON_BOARD
Andy Yanb5e16302019-11-14 11:21:12 +0800183 imply SPL_SEPARATE_BSS
Jonas Karlman16b0f902024-04-08 18:13:59 +0000184 imply SPL_SERIAL
185 imply SPL_SYSCON
Andy Yanb5e16302019-11-14 11:21:12 +0800186 help
187 The Rockchip RK3308 is a ARM-based Soc which embedded with quad
188 Cortex-A35 and highly integrated audio interfaces.
189
Kever Yangec02b3c2017-02-23 15:37:51 +0800190config ROCKCHIP_RK3328
191 bool "Support Rockchip RK3328"
192 select ARM64
Kever Yang07be6692019-06-09 00:27:15 +0300193 select SUPPORT_SPL
194 select SPL
Kever Yang69871852019-08-02 10:40:01 +0300195 select SUPPORT_TPL
196 select TPL
Kever Yang69871852019-08-02 10:40:01 +0300197 select TPL_NEEDS_SEPARATE_STACK if TPL
Jonas Karlman1b3d9dd2024-04-21 20:09:02 +0000198 imply ARMV8_CRYPTO
199 imply ARMV8_SET_SMPEN
Jonas Karlman86d4ebb2024-04-21 20:09:01 +0000200 imply MISC
201 imply MISC_INIT_R
Jonas Karlman1b3d9dd2024-04-21 20:09:02 +0000202 imply OF_LIVE
Jonas Karlmaned6f48e2024-05-04 19:42:55 +0000203 imply OF_UPSTREAM
Jagan Tekifb71c882024-01-17 13:21:52 +0530204 imply PRE_CONSOLE_BUFFER
Kever Yang205e2cc2019-07-22 20:02:16 +0800205 imply ROCKCHIP_COMMON_BOARD
Jonas Karlman86d4ebb2024-04-21 20:09:01 +0000206 imply ROCKCHIP_EFUSE
YouMin Chenb9f7df32019-11-15 11:04:44 +0800207 imply ROCKCHIP_SDRAM_COMMON
Kever Yangbb4c3252019-07-22 19:59:32 +0800208 imply SPL_ROCKCHIP_COMMON_BOARD
Jonas Karlman86d4ebb2024-04-21 20:09:01 +0000209 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600210 imply SPL_SERIAL
211 imply TPL_SERIAL
Kever Yangec02b3c2017-02-23 15:37:51 +0800212 help
213 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
214 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
215 video interfaces supporting HDMI and eDP, several DDR3 options
216 and video codec support. Peripherals include Gigabit Ethernet,
217 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
218
Andreas Färber9e3ad682017-05-15 17:51:18 +0800219config ROCKCHIP_RK3368
220 bool "Support Rockchip RK3368"
221 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200222 select SUPPORT_SPL
223 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200224 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang35b401e2019-07-22 20:02:17 +0800225 imply ROCKCHIP_COMMON_BOARD
Kever Yang8bf7ed42019-07-22 19:59:34 +0800226 imply SPL_ROCKCHIP_COMMON_BOARD
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200227 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600228 imply SPL_SERIAL
229 imply TPL_SERIAL
Kever Yang48831b22019-07-09 22:05:58 +0800230 imply TPL_ROCKCHIP_COMMON_BOARD
Andreas Färber9e3ad682017-05-15 17:51:18 +0800231 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200232 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
233 into a big and little cluster with 4 cores each) Cortex-A53 including
234 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
235 (for the little cluster), PowerVR G6110 based graphics, one video
236 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
237 video codec support.
238
239 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
240 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800241
Kever Yang0d3d7832016-07-19 21:16:59 +0800242config ROCKCHIP_RK3399
243 bool "Support Rockchip RK3399"
244 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800245 select SUPPORT_SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800246 select SUPPORT_TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800247 select SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530248 select SPL_ATF
Jagan Tekice063b92019-06-21 00:25:03 +0530249 select SPL_BOARD_INIT if SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530250 select SPL_LOAD_FIT
251 select SPL_CLK if SPL
252 select SPL_PINCTRL if SPL
253 select SPL_RAM if SPL
254 select SPL_REGMAP if SPL
255 select SPL_SYSCON if SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800256 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800257 select SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600258 select SPL_SERIAL
Jagan Tekicd433892019-05-08 11:11:43 +0530259 select CLK
260 select FIT
261 select PINCTRL
262 select RAM
263 select REGMAP
264 select SYSCON
265 select DM_PMIC
266 select DM_REGULATOR_FIXED
Andy Yan70378cb2017-10-11 15:00:16 +0800267 select BOARD_LATE_INIT
Jonas Karlman8b663722024-04-30 15:30:13 +0000268 imply ARMV8_CRYPTO
269 imply ARMV8_SET_SMPEN
Jonas Karlmana6389252024-04-30 15:30:12 +0000270 imply BOOTSTD_FULL
271 imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
Jonas Karlman0ad89712024-04-30 15:30:14 +0000272 imply DM_RNG
Jonas Karlman8b663722024-04-30 15:30:13 +0000273 imply LEGACY_IMAGE_FORMAT
Jonas Karlmana6389252024-04-30 15:30:12 +0000274 imply MISC
275 imply MISC_INIT_R
Jonas Karlman7f22b182024-04-30 15:30:16 +0000276 imply OF_LIBFDT_OVERLAY
Jonas Karlman8b663722024-04-30 15:30:13 +0000277 imply OF_LIVE
Jonas Karlman219b41a2024-05-04 19:42:57 +0000278 imply OF_UPSTREAM
Sughosh Ganuc1b8e8b2022-11-10 14:49:15 +0530279 imply PARTITION_TYPE_GUID
Jonas Karlman8660d332024-04-30 15:30:15 +0000280 imply PHY_GIGE if GMAC_ROCKCHIP
Jagan Teki9249d5c2020-04-02 17:11:23 +0530281 imply PRE_CONSOLE_BUFFER
Jonas Karlman0ad89712024-04-30 15:30:14 +0000282 imply RNG_ROCKCHIP
Kever Yang9554a4e2019-07-22 20:02:19 +0800283 imply ROCKCHIP_COMMON_BOARD
Jonas Karlmana6389252024-04-30 15:30:12 +0000284 imply ROCKCHIP_EFUSE
YouMin Chen23ae72e2019-11-15 11:04:45 +0800285 imply ROCKCHIP_SDRAM_COMMON
Jonas Karlman20e63412024-04-30 15:30:25 +0000286 imply SPL_DM_SEQ_ALIAS
Jonas Karlman8b663722024-04-30 15:30:13 +0000287 imply SPL_FIT_SIGNATURE
Kever Yangff9afe42019-07-22 19:59:42 +0800288 imply SPL_ROCKCHIP_COMMON_BOARD
Jonas Karlmana6389252024-04-30 15:30:12 +0000289 imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
290 imply TPL_CLK
291 imply TPL_DM
Kever Yangfca798d2018-11-09 11:18:15 +0800292 imply TPL_LIBCOMMON_SUPPORT
293 imply TPL_LIBGENERIC_SUPPORT
Kever Yangfca798d2018-11-09 11:18:15 +0800294 imply TPL_OF_CONTROL
Jonas Karlmana6389252024-04-30 15:30:12 +0000295 imply TPL_RAM
Kever Yangfca798d2018-11-09 11:18:15 +0800296 imply TPL_REGMAP
Jonas Karlmana6389252024-04-30 15:30:12 +0000297 imply TPL_ROCKCHIP_COMMON_BOARD
298 imply TPL_SERIAL
299 imply TPL_SYS_MALLOC_SIMPLE
Kever Yangfca798d2018-11-09 11:18:15 +0800300 imply TPL_SYSCON
Kever Yangfca798d2018-11-09 11:18:15 +0800301 imply TPL_TINY_MEMSET
Kever Yang0d3d7832016-07-19 21:16:59 +0800302 help
303 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
304 and quad-core Cortex-A53.
305 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
306 video interfaces supporting HDMI and eDP, several DDR3 options
307 and video codec support. Peripherals include Gigabit Ethernet,
308 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
309
Joseph Chen72cd8792021-06-02 15:58:25 +0800310config ROCKCHIP_RK3568
311 bool "Support Rockchip RK3568"
312 select ARM64
Nico Cheng00ceeb02021-10-26 10:42:19 +0800313 select SUPPORT_SPL
314 select SPL
Joseph Chen72cd8792021-06-02 15:58:25 +0800315 select CLK
316 select PINCTRL
317 select RAM
318 select REGMAP
319 select SYSCON
320 select BOARD_LATE_INIT
Manoj Saib34b19c2023-02-17 17:28:44 +0530321 select DM_REGULATOR_FIXED
Jagan Tekice0bbac2023-02-17 17:28:34 +0530322 select DM_RESET
Jonas Karlmanc1bb7122024-04-22 06:28:47 +0000323 imply BOOTSTD_FULL
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000324 imply DM_RNG
Jonas Karlmanbe56bb52023-02-22 22:44:41 +0000325 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000326 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000327 imply OF_LIBFDT_OVERLAY
Jonas Karlman737739e2024-05-04 19:43:00 +0000328 imply OF_UPSTREAM
Jonas Karlmane8b5bae2024-04-22 06:28:46 +0000329 imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000330 imply RNG_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000331 imply ROCKCHIP_COMMON_BOARD
332 imply ROCKCHIP_OTP
333 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000334 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Joseph Chen72cd8792021-06-02 15:58:25 +0800335 help
336 The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
337 including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
338 two video interfaces supporting HDMI and eDP, several DDR3 options
339 and video codec support. Peripherals include Gigabit Ethernet,
340 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
341
Jagan Teki8967dea2023-01-30 20:27:45 +0530342config ROCKCHIP_RK3588
343 bool "Support Rockchip RK3588"
344 select ARM64
345 select SUPPORT_SPL
346 select SPL
347 select CLK
348 select PINCTRL
349 select RAM
350 select REGMAP
351 select SYSCON
352 select BOARD_LATE_INIT
Jonas Karlman9bfd6512023-05-17 18:26:37 +0000353 select DM_REGULATOR_FIXED
354 select DM_RESET
Jonas Karlman0eb24592024-04-22 06:28:44 +0000355 imply BOOTSTD_FULL
356 imply CLK_SCMI
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000357 imply DM_RNG
Jonas Karlmaneeb19172023-02-22 22:44:41 +0000358 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000359 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000360 imply OF_LIBFDT_OVERLAY
Jonas Karlman45be8102024-05-04 19:43:07 +0000361 imply OF_UPSTREAM
Jonas Karlmane8b5bae2024-04-22 06:28:46 +0000362 imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000363 imply RNG_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000364 imply ROCKCHIP_COMMON_BOARD
365 imply ROCKCHIP_OTP
Jonas Karlmanfc805c22023-04-17 19:07:21 +0000366 imply SCMI_FIRMWARE
Jonas Karlman0eb24592024-04-22 06:28:44 +0000367 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
368 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Jagan Teki8967dea2023-01-30 20:27:45 +0530369 help
370 The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
371 quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
372 HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1,
373 SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet,
374 SDIO3.0 I2C, UART, SPI, GPIO and PWM.
375
Andy Yan2d982da2017-06-01 18:00:55 +0800376config ROCKCHIP_RV1108
377 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530378 select CPU_V7A
Kever Yanga2b336e2019-07-22 20:02:21 +0800379 imply ROCKCHIP_COMMON_BOARD
Fabio Estevam09df3632024-04-24 11:18:41 -0300380 imply OF_UPSTREAM
Andy Yan2d982da2017-06-01 18:00:55 +0800381 help
382 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
383 and a DSP.
384
Jagan Teki249a2382022-12-14 23:21:05 +0530385config ROCKCHIP_RV1126
386 bool "Support Rockchip RV1126"
387 select CPU_V7A
388 select SKIP_LOWLEVEL_INIT_ONLY
389 select TPL
390 select SUPPORT_TPL
391 select TPL_NEEDS_SEPARATE_STACK
392 select TPL_ROCKCHIP_BACK_TO_BROM
393 select SPL
394 select SUPPORT_SPL
395 select SPL_STACK_R
396 select CLK
397 select FIT
398 select PINCTRL
399 select RAM
400 select ROCKCHIP_SDRAM_COMMON
401 select REGMAP
402 select SYSCON
403 select DM_PMIC
404 select DM_REGULATOR_FIXED
405 select DM_RESET
406 select REGULATOR_RK8XX
407 select PMIC_RK8XX
408 select BOARD_LATE_INIT
409 imply ROCKCHIP_COMMON_BOARD
Tim Lunnd0812b22024-01-24 14:26:01 +1100410 select SPL_OPTEE_IMAGE if SPL_FIT
Jagan Tekid679f622023-07-29 19:11:42 +0530411 imply OF_LIBFDT_OVERLAY
Tim Lunncbfee492023-10-31 13:07:15 +1100412 imply ROCKCHIP_OTP
413 imply MISC_INIT_R
Jagan Teki249a2382022-12-14 23:21:05 +0530414 imply TPL_DM
415 imply TPL_LIBCOMMON_SUPPORT
416 imply TPL_LIBGENERIC_SUPPORT
417 imply TPL_OF_CONTROL
418 imply TPL_OF_PLATDATA
419 imply TPL_RAM
420 imply TPL_ROCKCHIP_COMMON_BOARD
421 imply TPL_SERIAL
422 imply SPL_CLK
423 imply SPL_DM
424 imply SPL_DRIVERS_MISC
425 imply SPL_LIBCOMMON_SUPPORT
426 imply SPL_LIBGENERIC_SUPPORT
427 imply SPL_OF_CONTROL
428 imply SPL_RAM
429 imply SPL_REGMAP
430 imply SPL_ROCKCHIP_COMMON_BOARD
431 imply SPL_SERIAL
432 imply SPL_SYSCON
Anand Moon00c92fe2024-05-14 09:35:22 +0530433 imply OF_UPSTREAM
Jagan Teki249a2382022-12-14 23:21:05 +0530434
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200435config ROCKCHIP_USB_UART
436 bool "Route uart output to usb pins"
437 help
438 Rockchip SoCs have the ability to route the signals of the debug
439 uart through the d+ and d- pins of a specific usb phy to enable
440 some form of closed-case debugging. With this option supported
441 SoCs will enable this routing as a debug measure.
442
Philipp Tomsich798370f2017-06-29 11:21:15 +0200443config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800444 bool "SPL returns to bootrom"
445 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100446 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800447 select SPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200448 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800449 help
450 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
451 SPL will return to the boot rom, which will then load the U-Boot
452 binary to keep going on.
453
Philipp Tomsich798370f2017-06-29 11:21:15 +0200454config TPL_ROCKCHIP_BACK_TO_BROM
455 bool "TPL returns to bootrom"
Kever Yangfca798d2018-11-09 11:18:15 +0800456 default y
Johan Jonkera768ff52023-10-27 20:35:37 +0200457 select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066
Kever Yangbd8532e2019-07-22 19:59:15 +0800458 select TPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200459 depends on TPL
460 help
461 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
462 SPL will return to the boot rom, which will then load the U-Boot
463 binary to keep going on.
464
Kever Yangbb337732019-07-22 20:02:01 +0800465config ROCKCHIP_COMMON_BOARD
466 bool "Rockchip common board file"
467 help
468 Rockchip SoCs have similar boot process, Common board file is mainly
469 in charge of common process of board_init() and board_late_init() for
470 U-Boot proper.
471
Kever Yang1d7cc72a2019-07-22 19:59:12 +0800472config SPL_ROCKCHIP_COMMON_BOARD
473 bool "Rockchip SPL common board file"
474 depends on SPL
475 help
476 Rockchip SoCs have similar boot process, SPL is mainly in charge of
477 load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
478 no TPL for the board.
479
Kever Yang34ead0f2019-07-09 22:05:55 +0800480config TPL_ROCKCHIP_COMMON_BOARD
Thomas Hebbcfbebf82019-12-20 18:05:22 -0800481 bool "Rockchip TPL common board file"
Kever Yang34ead0f2019-07-09 22:05:55 +0800482 depends on TPL
483 help
484 Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
485 init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
486 common board is a basic TPL board init which can be shared for most
Thomas Hebbfd37f242019-11-13 18:18:03 -0800487 of SoCs to avoid copy-paste for different SoCs.
Kever Yang34ead0f2019-07-09 22:05:55 +0800488
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000489config ROCKCHIP_EXTERNAL_TPL
490 bool "Use external TPL binary"
Massimo Pegorer8c20dfa2023-09-09 11:33:24 +0200491 default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000492 help
493 Some Rockchip SoCs require an external TPL to initialize DRAM.
494 Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
495 include the external TPL in the image built by binman.
496
Andy Yan70378cb2017-10-11 15:00:16 +0800497config ROCKCHIP_BOOT_MODE_REG
498 hex "Rockchip boot mode flag register address"
Andy Yan70378cb2017-10-11 15:00:16 +0800499 help
Kever Yang9fbe17c2019-03-28 11:01:23 +0800500 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yan70378cb2017-10-11 15:00:16 +0800501 according to the value from this register.
502
Chris Morgan7c9de742022-05-27 13:18:20 -0500503config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON
504 bool "Disable device boot on power plug-in"
505 depends on PMIC_RK8XX
Chris Morgan7c9de742022-05-27 13:18:20 -0500506 ---help---
507 Say Y here to prevent the device from booting up because of a plug-in
508 event. When set, the device will boot briefly to determine why it was
509 powered on, and if it was determined because of a plug-in event
510 instead of a button press event it will shut back off.
511
Johan Jonkerf6fc8952022-04-09 18:55:02 +0200512config ROCKCHIP_STIMER
513 bool "Rockchip STIMER support"
514 default y
515 help
516 Enable Rockchip STIMER support.
517
518config ROCKCHIP_STIMER_BASE
519 hex
520 depends on ROCKCHIP_STIMER
521
Kever Yange484f772017-04-20 17:03:46 +0800522config ROCKCHIP_SPL_RESERVE_IRAM
523 hex "Size of IRAM reserved in SPL"
Tom Rinif18679c2023-08-02 11:09:43 -0400524 default 0x0
Kever Yange484f772017-04-20 17:03:46 +0800525 help
526 SPL may need reserve memory for firmware loaded by SPL, whose load
527 address is in IRAM and may overlay with SPL text area if not
528 reserved.
529
Heiko Stübner355a8802017-02-18 19:46:25 +0100530config ROCKCHIP_BROM_HELPER
531 bool
532
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200533config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
534 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
535 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
536 help
537 Some Rockchip BROM variants (e.g. on the RK3188) load the
538 first stage in segments and enter multiple times. E.g. on
539 the RK3188, the first 1KB of the first stage are loaded
540 first and entered; after returning to the BROM, the
541 remainder of the first stage is loaded, but the BROM
542 re-enters at the same address/to the same code as previously.
543
544 This enables support code in the BOOT0 hook for the SPL stage
545 to allow multiple entries.
546
Quentin Schulz95b568f2024-03-11 13:01:54 +0100547config ROCKCHIP_DISABLE_FORCE_JTAG
548 bool "Disable force_jtag feature"
549 default y
550 depends on SPL
551 help
552 Rockchip SoCs can automatically switch between jtag and sdmmc based
553 on the following rules:
554 - all the SDMMC pins including SDMMC_DET set as SDMMC function in
555 GRF,
556 - force_jtag bit in GRF is 1,
557 - SDMMC_DET is low (no card detected),
558
559 Some HW design may not route the SD card card detect to SDMMC_DET
560 pin, thus breaking the SD card support in some cases because JTAG
561 would be auto-enabled by mistake.
562
563 Also, enabling JTAG at runtime may be an undesired feature, e.g.
564 because it could be a security vulnerability.
565
566 This disables force_jtag feature, which you may want for debugging
567 purposes.
568
569 If unsure, say Y.
570
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200571config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
572 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
573 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
574 help
575 Some Rockchip BROM variants (e.g. on the RK3188) load the
576 first stage in segments and enter multiple times. E.g. on
577 the RK3188, the first 1KB of the first stage are loaded
578 first and entered; after returning to the BROM, the
579 remainder of the first stage is loaded, but the BROM
580 re-enters at the same address/to the same code as previously.
581
582 This enables support code in the BOOT0 hook for the TPL stage
583 to allow multiple entries.
584
Simon Glassb58bfe02021-08-08 12:20:09 -0600585config SPL_MMC
Philipp Tomsich798370f2017-06-29 11:21:15 +0200586 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400587
Simon Glass88315f72020-07-19 13:55:57 -0600588config ROCKCHIP_SPI_IMAGE
589 bool "Build a SPI image for rockchip"
Simon Glass88315f72020-07-19 13:55:57 -0600590 help
591 Some Rockchip SoCs support booting from SPI flash. Enable this
Quentin Schulz12df9cf2022-09-02 15:10:54 +0200592 option to produce a SPI-flash image containing U-Boot. The image
593 is built by binman. U-Boot sits near the start of the image.
Simon Glass88315f72020-07-19 13:55:57 -0600594
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300595config LNX_KRNL_IMG_TEXT_OFFSET_BASE
Simon Glass72cc5382022-10-20 18:22:39 -0600596 default TEXT_BASE
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300597
Jonas Karlmane4453632024-03-02 19:16:11 +0000598config ROCKCHIP_COMMON_STACK_ADDR
599 bool
600 depends on SPL_SHARES_INIT_SP_ADDR
601 select HAS_CUSTOM_SYS_INIT_SP_ADDR
602 imply SPL_LIBCOMMON_SUPPORT if SPL
603 imply SPL_LIBGENERIC_SUPPORT if SPL
604 imply SPL_ROCKCHIP_COMMON_BOARD if SPL
605 imply SPL_SYS_MALLOC_F if SPL
606 imply SPL_SYS_MALLOC_SIMPLE if SPL
607 imply TPL_LIBCOMMON_SUPPORT if TPL
608 imply TPL_LIBGENERIC_SUPPORT if TPL
609 imply TPL_ROCKCHIP_COMMON_BOARD if TPL
610 imply TPL_SYS_MALLOC_F if TPL
611 imply TPL_SYS_MALLOC_SIMPLE if TPL
612
Quentin Schulzfb2d1ec2024-04-25 12:46:25 +0200613config NR_DRAM_BANKS
614 default 10 if ROCKCHIP_EXTERNAL_TPL
615
Heiko Stuebnerfc367852019-07-16 22:18:21 +0200616source "arch/arm/mach-rockchip/px30/Kconfig"
huang lin1115b642015-11-17 14:20:27 +0800617source "arch/arm/mach-rockchip/rk3036/Kconfig"
Johan Jonkera289fc72022-04-16 17:09:47 +0200618source "arch/arm/mach-rockchip/rk3066/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800619source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100620source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800621source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200622source "arch/arm/mach-rockchip/rk3288/Kconfig"
Andy Yanb5e16302019-11-14 11:21:12 +0800623source "arch/arm/mach-rockchip/rk3308/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800624source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800625source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800626source "arch/arm/mach-rockchip/rk3399/Kconfig"
Joseph Chen16899892021-06-02 16:13:46 +0800627source "arch/arm/mach-rockchip/rk3568/Kconfig"
Jagan Teki8967dea2023-01-30 20:27:45 +0530628source "arch/arm/mach-rockchip/rk3588/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800629source "arch/arm/mach-rockchip/rv1108/Kconfig"
Jagan Teki249a2382022-12-14 23:21:05 +0530630source "arch/arm/mach-rockchip/rv1126/Kconfig"
Jonas Karlmane4453632024-03-02 19:16:11 +0000631
632if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR
633
634config CUSTOM_SYS_INIT_SP_ADDR
635 default 0x3f00000
636
637config SYS_MALLOC_F_LEN
638 default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
639
640config SPL_SYS_MALLOC_F_LEN
641 default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
642
643config TPL_SYS_MALLOC_F_LEN
644 default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
645
646config TEXT_BASE
647 default 0x00200000 if ARM64
648
649config SPL_TEXT_BASE
650 default 0x0 if ARM64
651
652config SPL_HAS_BSS_LINKER_SECTION
653 default y if ARM64
654
655config SPL_BSS_START_ADDR
656 default 0x3f80000
657
658config SPL_BSS_MAX_SIZE
659 default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000
660
661config SPL_STACK_R
662 default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
663
664config SPL_STACK_R_ADDR
665 default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
666
667config SPL_STACK_R_MALLOC_SIMPLE_LEN
668 default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000
669
670endif
Simon Glass2cffe662015-08-30 16:55:38 -0600671endif