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Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stuebnerfc367852019-07-16 22:18:21 +02003config ROCKCHIP_PX30
4 bool "Support Rockchip PX30"
5 select ARM64
6 select SUPPORT_SPL
7 select SUPPORT_TPL
8 select SPL
9 select TPL
10 select TPL_TINY_FRAMEWORK if TPL
11 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
12 select TPL_NEEDS_SEPARATE_STACK if TPL
13 imply SPL_SEPARATE_BSS
14 select SPL_SERIAL_SUPPORT
15 select TPL_SERIAL_SUPPORT
16 select DEBUG_UART_BOARD_INIT
17 imply ROCKCHIP_COMMON_BOARD
18 imply SPL_ROCKCHIP_COMMON_BOARD
19 help
20 The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
22 and video codec support. Peripherals include Gigabit Ethernet,
23 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
24
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020025config ROCKCHIP_RK3036
26 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053027 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +080028 select SUPPORT_SPL
29 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +080030 imply USB_FUNCTION_ROCKUSB
31 imply CMD_ROCKUSB
Kever Yang427cb672019-07-22 20:02:04 +080032 imply ROCKCHIP_COMMON_BOARD
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020033 help
34 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
35 including NEON and GPU, Mali-400 graphics, several DDR3 options
36 and video codec support. Peripherals include Gigabit Ethernet,
37 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
38
Kever Yangaa827752017-11-28 16:04:16 +080039config ROCKCHIP_RK3128
40 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053041 select CPU_V7A
Kever Yang96362722019-07-22 20:02:05 +080042 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa827752017-11-28 16:04:16 +080043 help
44 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
45 including NEON and GPU, Mali-400 graphics, several DDR3 options
46 and video codec support. Peripherals include Gigabit Ethernet,
47 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
48
Heiko Stübneref6db5e2017-02-18 19:46:36 +010049config ROCKCHIP_RK3188
50 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053051 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080052 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010053 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010054 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020055 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020056 select SPL_REGMAP
57 select SPL_SYSCON
58 select SPL_RAM
59 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich16c689c2017-10-10 16:21:15 +020060 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangbd8532e2019-07-22 19:59:15 +080061 select SPL_ROCKCHIP_BACK_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020062 select BOARD_LATE_INIT
Kever Yangbfd3f872019-07-22 20:02:09 +080063 imply ROCKCHIP_COMMON_BOARD
Kever Yang3bd90402019-07-22 19:59:18 +080064 imply SPL_ROCKCHIP_COMMON_BOARD
Heiko Stübneref6db5e2017-02-18 19:46:36 +010065 help
66 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
67 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
68 video interfaces, several memory options and video codec support.
69 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
70 UART, SPI, I2C and PWMs.
71
Kever Yang57d4dbf2017-06-23 17:17:52 +080072config ROCKCHIP_RK322X
73 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053074 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080075 select SUPPORT_SPL
Kever Yangaff40c62019-04-02 20:41:24 +080076 select SUPPORT_TPL
Kever Yang57d4dbf2017-06-23 17:17:52 +080077 select SPL
Kever Yangaff40c62019-04-02 20:41:24 +080078 select SPL_DM
79 select SPL_OF_LIBFDT
80 select TPL
81 select TPL_DM
82 select TPL_OF_LIBFDT
83 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
84 select TPL_NEEDS_SEPARATE_STACK if TPL
85 select SPL_DRIVERS_MISC_SUPPORT
Kever Yang0b517732019-07-22 20:02:07 +080086 imply ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +080087 imply SPL_SERIAL_SUPPORT
Kever Yangd877fd22019-07-22 19:59:20 +080088 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +080089 imply TPL_SERIAL_SUPPORT
Kever Yang466f3fd2019-07-09 22:05:56 +080090 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +080091 select TPL_LIBCOMMON_SUPPORT
92 select TPL_LIBGENERIC_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +080093 help
94 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
95 including NEON and GPU, Mali-400 graphics, several DDR3 options
96 and video codec support. Peripherals include Gigabit Ethernet,
97 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
98
Simon Glass2cffe662015-08-30 16:55:38 -060099config ROCKCHIP_RK3288
100 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530101 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +0800102 select SUPPORT_SPL
103 select SPL
Kever Yangf7c0a332019-07-02 11:43:05 +0800104 select SUPPORT_TPL
Kever Yangba875012019-07-22 20:02:15 +0800105 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa67deb2019-07-22 19:59:27 +0800106 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +0800107 imply TPL_CLK
108 imply TPL_DM
109 imply TPL_DRIVERS_MISC_SUPPORT
110 imply TPL_LIBCOMMON_SUPPORT
111 imply TPL_LIBGENERIC_SUPPORT
112 imply TPL_NEEDS_SEPARATE_TEXT_BASE
Kever Yangb36e7092019-07-02 11:43:06 +0800113 imply TPL_NEEDS_SEPARATE_STACK
Kever Yangf7c0a332019-07-02 11:43:05 +0800114 imply TPL_OF_CONTROL
115 imply TPL_OF_PLATDATA
116 imply TPL_RAM
117 imply TPL_REGMAP
Kever Yange32f38e2019-07-09 22:05:57 +0800118 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +0800119 imply TPL_SERIAL_SUPPORT
120 imply TPL_SYSCON
Eddie Caib3501fe2017-12-15 08:17:13 +0800121 imply USB_FUNCTION_ROCKUSB
122 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -0600123 help
124 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
125 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
126 video interfaces supporting HDMI and eDP, several DDR3 options
127 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +0100128 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -0600129
Kever Yangec02b3c2017-02-23 15:37:51 +0800130config ROCKCHIP_RK3328
131 bool "Support Rockchip RK3328"
132 select ARM64
Kever Yang07be6692019-06-09 00:27:15 +0300133 select SUPPORT_SPL
134 select SPL
Kever Yang69871852019-08-02 10:40:01 +0300135 select SUPPORT_TPL
136 select TPL
137 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
138 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang205e2cc2019-07-22 20:02:16 +0800139 imply ROCKCHIP_COMMON_BOARD
YouMin Chenb9f7df32019-11-15 11:04:44 +0800140 imply ROCKCHIP_SDRAM_COMMON
Kever Yangbb4c3252019-07-22 19:59:32 +0800141 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yang07be6692019-06-09 00:27:15 +0300142 imply SPL_SERIAL_SUPPORT
Kever Yang69871852019-08-02 10:40:01 +0300143 imply TPL_SERIAL_SUPPORT
Kever Yang07be6692019-06-09 00:27:15 +0300144 imply SPL_SEPARATE_BSS
145 select ENABLE_ARM_SOC_BOOT0_HOOK
146 select DEBUG_UART_BOARD_INIT
147 select SYS_NS16550
Kever Yangec02b3c2017-02-23 15:37:51 +0800148 help
149 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
150 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
151 video interfaces supporting HDMI and eDP, several DDR3 options
152 and video codec support. Peripherals include Gigabit Ethernet,
153 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
154
Andreas Färber9e3ad682017-05-15 17:51:18 +0800155config ROCKCHIP_RK3368
156 bool "Support Rockchip RK3368"
157 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200158 select SUPPORT_SPL
159 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200160 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
161 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang35b401e2019-07-22 20:02:17 +0800162 imply ROCKCHIP_COMMON_BOARD
Kever Yang8bf7ed42019-07-22 19:59:34 +0800163 imply SPL_ROCKCHIP_COMMON_BOARD
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200164 imply SPL_SEPARATE_BSS
165 imply SPL_SERIAL_SUPPORT
166 imply TPL_SERIAL_SUPPORT
Kever Yang48831b22019-07-09 22:05:58 +0800167 imply TPL_ROCKCHIP_COMMON_BOARD
Andreas Färber9e3ad682017-05-15 17:51:18 +0800168 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200169 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
170 into a big and little cluster with 4 cores each) Cortex-A53 including
171 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
172 (for the little cluster), PowerVR G6110 based graphics, one video
173 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
174 video codec support.
175
176 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
177 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800178
Kever Yang0d3d7832016-07-19 21:16:59 +0800179config ROCKCHIP_RK3399
180 bool "Support Rockchip RK3399"
181 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800182 select SUPPORT_SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800183 select SUPPORT_TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800184 select SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530185 select SPL_ATF
186 select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Jagan Tekice063b92019-06-21 00:25:03 +0530187 select SPL_BOARD_INIT if SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530188 select SPL_LOAD_FIT
189 select SPL_CLK if SPL
190 select SPL_PINCTRL if SPL
191 select SPL_RAM if SPL
192 select SPL_REGMAP if SPL
193 select SPL_SYSCON if SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800194 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
195 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800196 select SPL_SEPARATE_BSS
Philipp Tomsichd17d8cf2017-07-26 12:29:01 +0200197 select SPL_SERIAL_SUPPORT
198 select SPL_DRIVERS_MISC_SUPPORT
Jagan Tekicd433892019-05-08 11:11:43 +0530199 select CLK
200 select FIT
201 select PINCTRL
202 select RAM
203 select REGMAP
204 select SYSCON
205 select DM_PMIC
206 select DM_REGULATOR_FIXED
Andy Yan70378cb2017-10-11 15:00:16 +0800207 select BOARD_LATE_INIT
Kever Yang9554a4e2019-07-22 20:02:19 +0800208 imply ROCKCHIP_COMMON_BOARD
YouMin Chen23ae72e2019-11-15 11:04:45 +0800209 imply ROCKCHIP_SDRAM_COMMON
Kever Yangff9afe42019-07-22 19:59:42 +0800210 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangfca798d2018-11-09 11:18:15 +0800211 imply TPL_SERIAL_SUPPORT
212 imply TPL_LIBCOMMON_SUPPORT
213 imply TPL_LIBGENERIC_SUPPORT
214 imply TPL_SYS_MALLOC_SIMPLE
Kever Yangfca798d2018-11-09 11:18:15 +0800215 imply TPL_DRIVERS_MISC_SUPPORT
216 imply TPL_OF_CONTROL
217 imply TPL_DM
218 imply TPL_REGMAP
219 imply TPL_SYSCON
220 imply TPL_RAM
221 imply TPL_CLK
222 imply TPL_TINY_MEMSET
Kever Yang3cfbb942019-07-09 22:06:01 +0800223 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yang0d3d7832016-07-19 21:16:59 +0800224 help
225 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
226 and quad-core Cortex-A53.
227 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
228 video interfaces supporting HDMI and eDP, several DDR3 options
229 and video codec support. Peripherals include Gigabit Ethernet,
230 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
231
Andy Yan2d982da2017-06-01 18:00:55 +0800232config ROCKCHIP_RV1108
233 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530234 select CPU_V7A
Kever Yanga2b336e2019-07-22 20:02:21 +0800235 imply ROCKCHIP_COMMON_BOARD
Andy Yan2d982da2017-06-01 18:00:55 +0800236 help
237 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
238 and a DSP.
239
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200240config ROCKCHIP_USB_UART
241 bool "Route uart output to usb pins"
242 help
243 Rockchip SoCs have the ability to route the signals of the debug
244 uart through the d+ and d- pins of a specific usb phy to enable
245 some form of closed-case debugging. With this option supported
246 SoCs will enable this routing as a debug measure.
247
Philipp Tomsich798370f2017-06-29 11:21:15 +0200248config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800249 bool "SPL returns to bootrom"
250 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100251 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800252 select SPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200253 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800254 help
255 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
256 SPL will return to the boot rom, which will then load the U-Boot
257 binary to keep going on.
258
Philipp Tomsich798370f2017-06-29 11:21:15 +0200259config TPL_ROCKCHIP_BACK_TO_BROM
260 bool "TPL returns to bootrom"
Kever Yangfca798d2018-11-09 11:18:15 +0800261 default y
Philipp Tomsich798370f2017-06-29 11:21:15 +0200262 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800263 select TPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200264 depends on TPL
265 help
266 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
267 SPL will return to the boot rom, which will then load the U-Boot
268 binary to keep going on.
269
Kever Yangbb337732019-07-22 20:02:01 +0800270config ROCKCHIP_COMMON_BOARD
271 bool "Rockchip common board file"
272 help
273 Rockchip SoCs have similar boot process, Common board file is mainly
274 in charge of common process of board_init() and board_late_init() for
275 U-Boot proper.
276
Kever Yang1d7cc72a2019-07-22 19:59:12 +0800277config SPL_ROCKCHIP_COMMON_BOARD
278 bool "Rockchip SPL common board file"
279 depends on SPL
280 help
281 Rockchip SoCs have similar boot process, SPL is mainly in charge of
282 load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
283 no TPL for the board.
284
Kever Yang34ead0f2019-07-09 22:05:55 +0800285config TPL_ROCKCHIP_COMMON_BOARD
286 bool ""
287 depends on TPL
288 help
289 Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
290 init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
291 common board is a basic TPL board init which can be shared for most
292 of SoCs to avoid copy-pase for different SoCs.
293
Andy Yan70378cb2017-10-11 15:00:16 +0800294config ROCKCHIP_BOOT_MODE_REG
295 hex "Rockchip boot mode flag register address"
Andy Yan70378cb2017-10-11 15:00:16 +0800296 help
Kever Yang9fbe17c2019-03-28 11:01:23 +0800297 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yan70378cb2017-10-11 15:00:16 +0800298 according to the value from this register.
299
Kever Yange484f772017-04-20 17:03:46 +0800300config ROCKCHIP_SPL_RESERVE_IRAM
301 hex "Size of IRAM reserved in SPL"
Kever Yang60a50072017-12-18 15:13:19 +0800302 default 0
Kever Yange484f772017-04-20 17:03:46 +0800303 help
304 SPL may need reserve memory for firmware loaded by SPL, whose load
305 address is in IRAM and may overlay with SPL text area if not
306 reserved.
307
Heiko Stübner355a8802017-02-18 19:46:25 +0100308config ROCKCHIP_BROM_HELPER
309 bool
310
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200311config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
312 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
313 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
314 help
315 Some Rockchip BROM variants (e.g. on the RK3188) load the
316 first stage in segments and enter multiple times. E.g. on
317 the RK3188, the first 1KB of the first stage are loaded
318 first and entered; after returning to the BROM, the
319 remainder of the first stage is loaded, but the BROM
320 re-enters at the same address/to the same code as previously.
321
322 This enables support code in the BOOT0 hook for the SPL stage
323 to allow multiple entries.
324
325config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
326 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
327 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
328 help
329 Some Rockchip BROM variants (e.g. on the RK3188) load the
330 first stage in segments and enter multiple times. E.g. on
331 the RK3188, the first 1KB of the first stage are loaded
332 first and entered; after returning to the BROM, the
333 remainder of the first stage is loaded, but the BROM
334 re-enters at the same address/to the same code as previously.
335
336 This enables support code in the BOOT0 hook for the TPL stage
337 to allow multiple entries.
338
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400339config SPL_MMC_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200340 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400341
Heiko Stuebnerfc367852019-07-16 22:18:21 +0200342source "arch/arm/mach-rockchip/px30/Kconfig"
huang lin1115b642015-11-17 14:20:27 +0800343source "arch/arm/mach-rockchip/rk3036/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800344source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100345source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800346source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200347source "arch/arm/mach-rockchip/rk3288/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800348source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800349source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800350source "arch/arm/mach-rockchip/rk3399/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800351source "arch/arm/mach-rockchip/rv1108/Kconfig"
Simon Glass2cffe662015-08-30 16:55:38 -0600352endif