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Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stübner5c91e2b2016-07-16 00:17:15 +02003config ROCKCHIP_RK3036
4 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +05305 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +08006 select SUPPORT_SPL
7 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +08008 imply USB_FUNCTION_ROCKUSB
9 imply CMD_ROCKUSB
Kever Yang427cb672019-07-22 20:02:04 +080010 imply ROCKCHIP_COMMON_BOARD
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020011 help
12 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
13 including NEON and GPU, Mali-400 graphics, several DDR3 options
14 and video codec support. Peripherals include Gigabit Ethernet,
15 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
16
Kever Yangaa827752017-11-28 16:04:16 +080017config ROCKCHIP_RK3128
18 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053019 select CPU_V7A
Kever Yang96362722019-07-22 20:02:05 +080020 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa827752017-11-28 16:04:16 +080021 help
22 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
23 including NEON and GPU, Mali-400 graphics, several DDR3 options
24 and video codec support. Peripherals include Gigabit Ethernet,
25 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
26
Heiko Stübneref6db5e2017-02-18 19:46:36 +010027config ROCKCHIP_RK3188
28 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053029 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080030 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010031 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010032 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020033 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020034 select SPL_REGMAP
35 select SPL_SYSCON
36 select SPL_RAM
37 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich16c689c2017-10-10 16:21:15 +020038 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangbd8532e2019-07-22 19:59:15 +080039 select SPL_ROCKCHIP_BACK_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020040 select BOARD_LATE_INIT
Kever Yangbfd3f872019-07-22 20:02:09 +080041 imply ROCKCHIP_COMMON_BOARD
Kever Yang3bd90402019-07-22 19:59:18 +080042 imply SPL_ROCKCHIP_COMMON_BOARD
Heiko Stübneref6db5e2017-02-18 19:46:36 +010043 help
44 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
45 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
46 video interfaces, several memory options and video codec support.
47 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
48 UART, SPI, I2C and PWMs.
49
Kever Yang57d4dbf2017-06-23 17:17:52 +080050config ROCKCHIP_RK322X
51 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053052 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080053 select SUPPORT_SPL
Kever Yangaff40c62019-04-02 20:41:24 +080054 select SUPPORT_TPL
Kever Yang57d4dbf2017-06-23 17:17:52 +080055 select SPL
Kever Yangaff40c62019-04-02 20:41:24 +080056 select SPL_DM
57 select SPL_OF_LIBFDT
58 select TPL
59 select TPL_DM
60 select TPL_OF_LIBFDT
61 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
62 select TPL_NEEDS_SEPARATE_STACK if TPL
63 select SPL_DRIVERS_MISC_SUPPORT
Kever Yang0b517732019-07-22 20:02:07 +080064 imply ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +080065 imply SPL_SERIAL_SUPPORT
Kever Yangd877fd22019-07-22 19:59:20 +080066 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +080067 imply TPL_SERIAL_SUPPORT
Kever Yang466f3fd2019-07-09 22:05:56 +080068 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +080069 select TPL_LIBCOMMON_SUPPORT
70 select TPL_LIBGENERIC_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +080071 help
72 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
73 including NEON and GPU, Mali-400 graphics, several DDR3 options
74 and video codec support. Peripherals include Gigabit Ethernet,
75 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
76
Simon Glass2cffe662015-08-30 16:55:38 -060077config ROCKCHIP_RK3288
78 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053079 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +080080 select SUPPORT_SPL
81 select SPL
Kever Yangf7c0a332019-07-02 11:43:05 +080082 select SUPPORT_TPL
Kever Yangaa67deb2019-07-22 19:59:27 +080083 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +080084 imply TPL_CLK
85 imply TPL_DM
86 imply TPL_DRIVERS_MISC_SUPPORT
87 imply TPL_LIBCOMMON_SUPPORT
88 imply TPL_LIBGENERIC_SUPPORT
89 imply TPL_NEEDS_SEPARATE_TEXT_BASE
Kever Yangb36e7092019-07-02 11:43:06 +080090 imply TPL_NEEDS_SEPARATE_STACK
Kever Yangf7c0a332019-07-02 11:43:05 +080091 imply TPL_OF_CONTROL
92 imply TPL_OF_PLATDATA
93 imply TPL_RAM
94 imply TPL_REGMAP
Kever Yange32f38e2019-07-09 22:05:57 +080095 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +080096 imply TPL_SERIAL_SUPPORT
97 imply TPL_SYSCON
Eddie Caib3501fe2017-12-15 08:17:13 +080098 imply USB_FUNCTION_ROCKUSB
99 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -0600100 help
101 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
102 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
103 video interfaces supporting HDMI and eDP, several DDR3 options
104 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +0100105 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -0600106
Kever Yangec02b3c2017-02-23 15:37:51 +0800107config ROCKCHIP_RK3328
108 bool "Support Rockchip RK3328"
109 select ARM64
Kever Yang07be6692019-06-09 00:27:15 +0300110 select SUPPORT_SPL
111 select SPL
Kever Yangbb4c3252019-07-22 19:59:32 +0800112 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yang07be6692019-06-09 00:27:15 +0300113 imply SPL_SERIAL_SUPPORT
114 imply SPL_SEPARATE_BSS
115 select ENABLE_ARM_SOC_BOOT0_HOOK
116 select DEBUG_UART_BOARD_INIT
117 select SYS_NS16550
Kever Yangec02b3c2017-02-23 15:37:51 +0800118 help
119 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
120 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
121 video interfaces supporting HDMI and eDP, several DDR3 options
122 and video codec support. Peripherals include Gigabit Ethernet,
123 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
124
Andreas Färber9e3ad682017-05-15 17:51:18 +0800125config ROCKCHIP_RK3368
126 bool "Support Rockchip RK3368"
127 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200128 select SUPPORT_SPL
129 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200130 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
131 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang8bf7ed42019-07-22 19:59:34 +0800132 imply SPL_ROCKCHIP_COMMON_BOARD
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200133 imply SPL_SEPARATE_BSS
134 imply SPL_SERIAL_SUPPORT
135 imply TPL_SERIAL_SUPPORT
Kever Yang48831b22019-07-09 22:05:58 +0800136 imply TPL_ROCKCHIP_COMMON_BOARD
Andreas Färber9e3ad682017-05-15 17:51:18 +0800137 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200138 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
139 into a big and little cluster with 4 cores each) Cortex-A53 including
140 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
141 (for the little cluster), PowerVR G6110 based graphics, one video
142 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
143 video codec support.
144
145 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
146 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800147
Kever Yang0d3d7832016-07-19 21:16:59 +0800148config ROCKCHIP_RK3399
149 bool "Support Rockchip RK3399"
150 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800151 select SUPPORT_SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800152 select SUPPORT_TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800153 select SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530154 select SPL_ATF
155 select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Jagan Tekice063b92019-06-21 00:25:03 +0530156 select SPL_BOARD_INIT if SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530157 select SPL_LOAD_FIT
158 select SPL_CLK if SPL
159 select SPL_PINCTRL if SPL
160 select SPL_RAM if SPL
161 select SPL_REGMAP if SPL
162 select SPL_SYSCON if SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800163 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
164 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800165 select SPL_SEPARATE_BSS
Philipp Tomsichd17d8cf2017-07-26 12:29:01 +0200166 select SPL_SERIAL_SUPPORT
167 select SPL_DRIVERS_MISC_SUPPORT
Jagan Tekicd433892019-05-08 11:11:43 +0530168 select CLK
169 select FIT
170 select PINCTRL
171 select RAM
172 select REGMAP
173 select SYSCON
174 select DM_PMIC
175 select DM_REGULATOR_FIXED
Andy Yan70378cb2017-10-11 15:00:16 +0800176 select BOARD_LATE_INIT
Kever Yangff9afe42019-07-22 19:59:42 +0800177 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangfca798d2018-11-09 11:18:15 +0800178 imply TPL_SERIAL_SUPPORT
179 imply TPL_LIBCOMMON_SUPPORT
180 imply TPL_LIBGENERIC_SUPPORT
181 imply TPL_SYS_MALLOC_SIMPLE
Kever Yangfca798d2018-11-09 11:18:15 +0800182 imply TPL_DRIVERS_MISC_SUPPORT
183 imply TPL_OF_CONTROL
184 imply TPL_DM
185 imply TPL_REGMAP
186 imply TPL_SYSCON
187 imply TPL_RAM
188 imply TPL_CLK
189 imply TPL_TINY_MEMSET
Kever Yang3cfbb942019-07-09 22:06:01 +0800190 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yang0d3d7832016-07-19 21:16:59 +0800191 help
192 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
193 and quad-core Cortex-A53.
194 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
195 video interfaces supporting HDMI and eDP, several DDR3 options
196 and video codec support. Peripherals include Gigabit Ethernet,
197 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
198
Andy Yan2d982da2017-06-01 18:00:55 +0800199config ROCKCHIP_RV1108
200 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530201 select CPU_V7A
Andy Yan2d982da2017-06-01 18:00:55 +0800202 help
203 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
204 and a DSP.
205
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200206config ROCKCHIP_USB_UART
207 bool "Route uart output to usb pins"
208 help
209 Rockchip SoCs have the ability to route the signals of the debug
210 uart through the d+ and d- pins of a specific usb phy to enable
211 some form of closed-case debugging. With this option supported
212 SoCs will enable this routing as a debug measure.
213
Philipp Tomsich798370f2017-06-29 11:21:15 +0200214config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800215 bool "SPL returns to bootrom"
216 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100217 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800218 select SPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200219 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800220 help
221 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
222 SPL will return to the boot rom, which will then load the U-Boot
223 binary to keep going on.
224
Philipp Tomsich798370f2017-06-29 11:21:15 +0200225config TPL_ROCKCHIP_BACK_TO_BROM
226 bool "TPL returns to bootrom"
Kever Yangfca798d2018-11-09 11:18:15 +0800227 default y
Philipp Tomsich798370f2017-06-29 11:21:15 +0200228 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800229 select TPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200230 depends on TPL
231 help
232 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
233 SPL will return to the boot rom, which will then load the U-Boot
234 binary to keep going on.
235
Kever Yangbb337732019-07-22 20:02:01 +0800236config ROCKCHIP_COMMON_BOARD
237 bool "Rockchip common board file"
238 help
239 Rockchip SoCs have similar boot process, Common board file is mainly
240 in charge of common process of board_init() and board_late_init() for
241 U-Boot proper.
242
Kever Yang1d7cc72a2019-07-22 19:59:12 +0800243config SPL_ROCKCHIP_COMMON_BOARD
244 bool "Rockchip SPL common board file"
245 depends on SPL
246 help
247 Rockchip SoCs have similar boot process, SPL is mainly in charge of
248 load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
249 no TPL for the board.
250
Kever Yang34ead0f2019-07-09 22:05:55 +0800251config TPL_ROCKCHIP_COMMON_BOARD
252 bool ""
253 depends on TPL
254 help
255 Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
256 init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
257 common board is a basic TPL board init which can be shared for most
258 of SoCs to avoid copy-pase for different SoCs.
259
Andy Yan70378cb2017-10-11 15:00:16 +0800260config ROCKCHIP_BOOT_MODE_REG
261 hex "Rockchip boot mode flag register address"
Andy Yan70378cb2017-10-11 15:00:16 +0800262 help
Kever Yang9fbe17c2019-03-28 11:01:23 +0800263 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yan70378cb2017-10-11 15:00:16 +0800264 according to the value from this register.
265
Kever Yange484f772017-04-20 17:03:46 +0800266config ROCKCHIP_SPL_RESERVE_IRAM
267 hex "Size of IRAM reserved in SPL"
Kever Yang60a50072017-12-18 15:13:19 +0800268 default 0
Kever Yange484f772017-04-20 17:03:46 +0800269 help
270 SPL may need reserve memory for firmware loaded by SPL, whose load
271 address is in IRAM and may overlay with SPL text area if not
272 reserved.
273
Heiko Stübner355a8802017-02-18 19:46:25 +0100274config ROCKCHIP_BROM_HELPER
275 bool
276
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200277config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
278 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
279 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
280 help
281 Some Rockchip BROM variants (e.g. on the RK3188) load the
282 first stage in segments and enter multiple times. E.g. on
283 the RK3188, the first 1KB of the first stage are loaded
284 first and entered; after returning to the BROM, the
285 remainder of the first stage is loaded, but the BROM
286 re-enters at the same address/to the same code as previously.
287
288 This enables support code in the BOOT0 hook for the SPL stage
289 to allow multiple entries.
290
291config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
292 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
293 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
294 help
295 Some Rockchip BROM variants (e.g. on the RK3188) load the
296 first stage in segments and enter multiple times. E.g. on
297 the RK3188, the first 1KB of the first stage are loaded
298 first and entered; after returning to the BROM, the
299 remainder of the first stage is loaded, but the BROM
300 re-enters at the same address/to the same code as previously.
301
302 This enables support code in the BOOT0 hook for the TPL stage
303 to allow multiple entries.
304
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400305config SPL_MMC_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200306 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400307
huang lin1115b642015-11-17 14:20:27 +0800308source "arch/arm/mach-rockchip/rk3036/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800309source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100310source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800311source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200312source "arch/arm/mach-rockchip/rk3288/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800313source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800314source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800315source "arch/arm/mach-rockchip/rk3399/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800316source "arch/arm/mach-rockchip/rv1108/Kconfig"
Simon Glass2cffe662015-08-30 16:55:38 -0600317endif