Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 1 | if ARCH_ROCKCHIP |
| 2 | |
Heiko Stübner | 5c91e2b | 2016-07-16 00:17:15 +0200 | [diff] [blame] | 3 | config ROCKCHIP_RK3036 |
| 4 | bool "Support Rockchip RK3036" |
| 5 | select CPU_V7 |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 6 | select SUPPORT_SPL |
| 7 | select SPL |
Heiko Stübner | 5c91e2b | 2016-07-16 00:17:15 +0200 | [diff] [blame] | 8 | help |
| 9 | The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 |
| 10 | including NEON and GPU, Mali-400 graphics, several DDR3 options |
| 11 | and video codec support. Peripherals include Gigabit Ethernet, |
| 12 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. |
| 13 | |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 14 | config ROCKCHIP_RK3188 |
| 15 | bool "Support Rockchip RK3188" |
| 16 | select CPU_V7 |
Ley Foon Tan | 48fcc4a | 2017-05-03 17:13:32 +0800 | [diff] [blame] | 17 | select SPL_BOARD_INIT if SPL |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 18 | select SUPPORT_SPL |
| 19 | select SUPPORT_TPL |
| 20 | select SPL |
Philipp Tomsich | 16c689c | 2017-10-10 16:21:15 +0200 | [diff] [blame^] | 21 | select SPL_ROCKCHIP_EARLYRETURN_TO_BROM |
Heiko Stübner | 015f69a | 2017-04-06 00:19:36 +0200 | [diff] [blame] | 22 | select BOARD_LATE_INIT |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 23 | select ROCKCHIP_BROM_HELPER |
| 24 | help |
| 25 | The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9 |
| 26 | including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two |
| 27 | video interfaces, several memory options and video codec support. |
| 28 | Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, |
| 29 | UART, SPI, I2C and PWMs. |
| 30 | |
Kever Yang | 57d4dbf | 2017-06-23 17:17:52 +0800 | [diff] [blame] | 31 | config ROCKCHIP_RK322X |
| 32 | bool "Support Rockchip RK3228/RK3229" |
| 33 | select CPU_V7 |
| 34 | select SUPPORT_SPL |
| 35 | select SPL |
| 36 | select ROCKCHIP_BROM_HELPER |
| 37 | select DEBUG_UART_BOARD_INIT |
| 38 | help |
| 39 | The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7 |
| 40 | including NEON and GPU, Mali-400 graphics, several DDR3 options |
| 41 | and video codec support. Peripherals include Gigabit Ethernet, |
| 42 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. |
| 43 | |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 44 | config ROCKCHIP_RK3288 |
| 45 | bool "Support Rockchip RK3288" |
Andreas Färber | 6c42703 | 2016-07-14 05:09:26 +0200 | [diff] [blame] | 46 | select CPU_V7 |
Ley Foon Tan | 48fcc4a | 2017-05-03 17:13:32 +0800 | [diff] [blame] | 47 | select SPL_BOARD_INIT if SPL |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 48 | select SUPPORT_SPL |
| 49 | select SPL |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 50 | help |
| 51 | The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 |
| 52 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two |
| 53 | video interfaces supporting HDMI and eDP, several DDR3 options |
| 54 | and video codec support. Peripherals include Gigabit Ethernet, |
Andreas Färber | 531e8e0 | 2016-11-02 18:03:01 +0100 | [diff] [blame] | 55 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 56 | |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 57 | config ROCKCHIP_RK3328 |
| 58 | bool "Support Rockchip RK3328" |
| 59 | select ARM64 |
| 60 | help |
| 61 | The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. |
| 62 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two |
| 63 | video interfaces supporting HDMI and eDP, several DDR3 options |
| 64 | and video codec support. Peripherals include Gigabit Ethernet, |
| 65 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
| 66 | |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 67 | config ROCKCHIP_RK3368 |
| 68 | bool "Support Rockchip RK3368" |
| 69 | select ARM64 |
Philipp Tomsich | 84af43e | 2017-06-11 23:46:25 +0200 | [diff] [blame] | 70 | select SUPPORT_SPL |
| 71 | select SUPPORT_TPL |
Philipp Tomsich | 01b219e | 2017-07-28 20:03:07 +0200 | [diff] [blame] | 72 | select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL |
| 73 | select TPL_NEEDS_SEPARATE_STACK if TPL |
Philipp Tomsich | 84af43e | 2017-06-11 23:46:25 +0200 | [diff] [blame] | 74 | imply SPL_SEPARATE_BSS |
| 75 | imply SPL_SERIAL_SUPPORT |
| 76 | imply TPL_SERIAL_SUPPORT |
Philipp Tomsich | 84af43e | 2017-06-11 23:46:25 +0200 | [diff] [blame] | 77 | select DEBUG_UART_BOARD_INIT |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 78 | select SYS_NS16550 |
| 79 | help |
Philipp Tomsich | 9f3deaf | 2017-06-10 00:47:53 +0200 | [diff] [blame] | 80 | The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised |
| 81 | into a big and little cluster with 4 cores each) Cortex-A53 including |
| 82 | AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache |
| 83 | (for the little cluster), PowerVR G6110 based graphics, one video |
| 84 | output processor supporting LVDS/HDMI/eDP, several DDR3 options and |
| 85 | video codec support. |
| 86 | |
| 87 | On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, |
| 88 | I2S, UARTs, SPI, I2C and PWMs. |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 89 | |
Philipp Tomsich | cbacb40 | 2017-08-02 21:26:18 +0200 | [diff] [blame] | 90 | if ROCKCHIP_RK3368 |
| 91 | |
| 92 | config TPL_LDSCRIPT |
| 93 | default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds" |
| 94 | |
Philipp Tomsich | 7d1319b | 2017-07-28 20:20:41 +0200 | [diff] [blame] | 95 | config TPL_TEXT_BASE |
| 96 | default 0xff8c1000 |
| 97 | |
| 98 | config TPL_MAX_SIZE |
| 99 | default 28672 |
| 100 | |
| 101 | config TPL_STACK |
| 102 | default 0xff8cffff |
| 103 | |
Philipp Tomsich | cbacb40 | 2017-08-02 21:26:18 +0200 | [diff] [blame] | 104 | endif |
| 105 | |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 106 | config ROCKCHIP_RK3399 |
| 107 | bool "Support Rockchip RK3399" |
| 108 | select ARM64 |
Kever Yang | 16efdfd | 2017-02-22 16:56:38 +0800 | [diff] [blame] | 109 | select SUPPORT_SPL |
| 110 | select SPL |
| 111 | select SPL_SEPARATE_BSS |
Philipp Tomsich | d17d8cf | 2017-07-26 12:29:01 +0200 | [diff] [blame] | 112 | select SPL_SERIAL_SUPPORT |
| 113 | select SPL_DRIVERS_MISC_SUPPORT |
Philipp Tomsich | 41029e6 | 2017-04-01 12:59:25 +0200 | [diff] [blame] | 114 | select DEBUG_UART_BOARD_INIT |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 115 | help |
| 116 | The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 |
| 117 | and quad-core Cortex-A53. |
| 118 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two |
| 119 | video interfaces supporting HDMI and eDP, several DDR3 options |
| 120 | and video codec support. Peripherals include Gigabit Ethernet, |
| 121 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
| 122 | |
Andy Yan | 2d982da | 2017-06-01 18:00:55 +0800 | [diff] [blame] | 123 | config ROCKCHIP_RV1108 |
| 124 | bool "Support Rockchip RV1108" |
| 125 | select CPU_V7 |
| 126 | help |
| 127 | The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 |
| 128 | and a DSP. |
| 129 | |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 130 | config SPL_ROCKCHIP_BACK_TO_BROM |
Xu Ziyuan | 5401eb8 | 2016-07-12 19:09:49 +0800 | [diff] [blame] | 131 | bool "SPL returns to bootrom" |
| 132 | default y if ROCKCHIP_RK3036 |
Heiko Stübner | 355a880 | 2017-02-18 19:46:25 +0100 | [diff] [blame] | 133 | select ROCKCHIP_BROM_HELPER |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 134 | depends on SPL |
Xu Ziyuan | 5401eb8 | 2016-07-12 19:09:49 +0800 | [diff] [blame] | 135 | help |
| 136 | Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, |
| 137 | SPL will return to the boot rom, which will then load the U-Boot |
| 138 | binary to keep going on. |
| 139 | |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 140 | config TPL_ROCKCHIP_BACK_TO_BROM |
| 141 | bool "TPL returns to bootrom" |
| 142 | default y if ROCKCHIP_RK3368 |
| 143 | select ROCKCHIP_BROM_HELPER |
| 144 | depends on TPL |
| 145 | help |
| 146 | Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, |
| 147 | SPL will return to the boot rom, which will then load the U-Boot |
| 148 | binary to keep going on. |
| 149 | |
Kever Yang | e484f77 | 2017-04-20 17:03:46 +0800 | [diff] [blame] | 150 | config ROCKCHIP_SPL_RESERVE_IRAM |
| 151 | hex "Size of IRAM reserved in SPL" |
| 152 | default 0x4000 |
| 153 | help |
| 154 | SPL may need reserve memory for firmware loaded by SPL, whose load |
| 155 | address is in IRAM and may overlay with SPL text area if not |
| 156 | reserved. |
| 157 | |
Heiko Stübner | 355a880 | 2017-02-18 19:46:25 +0100 | [diff] [blame] | 158 | config ROCKCHIP_BROM_HELPER |
| 159 | bool |
| 160 | |
Philipp Tomsich | 9f1a447 | 2017-10-10 16:21:10 +0200 | [diff] [blame] | 161 | config SPL_ROCKCHIP_EARLYRETURN_TO_BROM |
| 162 | bool "SPL requires early-return (for RK3188-style BROM) to BROM" |
| 163 | depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK |
| 164 | help |
| 165 | Some Rockchip BROM variants (e.g. on the RK3188) load the |
| 166 | first stage in segments and enter multiple times. E.g. on |
| 167 | the RK3188, the first 1KB of the first stage are loaded |
| 168 | first and entered; after returning to the BROM, the |
| 169 | remainder of the first stage is loaded, but the BROM |
| 170 | re-enters at the same address/to the same code as previously. |
| 171 | |
| 172 | This enables support code in the BOOT0 hook for the SPL stage |
| 173 | to allow multiple entries. |
| 174 | |
| 175 | config TPL_ROCKCHIP_EARLYRETURN_TO_BROM |
| 176 | bool "TPL requires early-return (for RK3188-style BROM) to BROM" |
| 177 | depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK |
| 178 | help |
| 179 | Some Rockchip BROM variants (e.g. on the RK3188) load the |
| 180 | first stage in segments and enter multiple times. E.g. on |
| 181 | the RK3188, the first 1KB of the first stage are loaded |
| 182 | first and entered; after returning to the BROM, the |
| 183 | remainder of the first stage is loaded, but the BROM |
| 184 | re-enters at the same address/to the same code as previously. |
| 185 | |
| 186 | This enables support code in the BOOT0 hook for the TPL stage |
| 187 | to allow multiple entries. |
| 188 | |
Sandy Patterson | d70f0f3 | 2016-08-29 07:31:16 -0400 | [diff] [blame] | 189 | config SPL_MMC_SUPPORT |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 190 | default y if !SPL_ROCKCHIP_BACK_TO_BROM |
Sandy Patterson | d70f0f3 | 2016-08-29 07:31:16 -0400 | [diff] [blame] | 191 | |
huang lin | 1115b64 | 2015-11-17 14:20:27 +0800 | [diff] [blame] | 192 | source "arch/arm/mach-rockchip/rk3036/Kconfig" |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 193 | source "arch/arm/mach-rockchip/rk3188/Kconfig" |
Kever Yang | a4f460d | 2017-06-23 17:17:54 +0800 | [diff] [blame] | 194 | source "arch/arm/mach-rockchip/rk322x/Kconfig" |
Heiko Stübner | 5c91e2b | 2016-07-16 00:17:15 +0200 | [diff] [blame] | 195 | source "arch/arm/mach-rockchip/rk3288/Kconfig" |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 196 | source "arch/arm/mach-rockchip/rk3328/Kconfig" |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 197 | source "arch/arm/mach-rockchip/rk3368/Kconfig" |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 198 | source "arch/arm/mach-rockchip/rk3399/Kconfig" |
Andy Yan | 2d982da | 2017-06-01 18:00:55 +0800 | [diff] [blame] | 199 | source "arch/arm/mach-rockchip/rv1108/Kconfig" |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 200 | endif |