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Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stübner5c91e2b2016-07-16 00:17:15 +02003config ROCKCHIP_RK3036
4 bool "Support Rockchip RK3036"
5 select CPU_V7
Kever Yang0d3d7832016-07-19 21:16:59 +08006 select SUPPORT_SPL
7 select SPL
Heiko Stübner5c91e2b2016-07-16 00:17:15 +02008 help
9 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
10 including NEON and GPU, Mali-400 graphics, several DDR3 options
11 and video codec support. Peripherals include Gigabit Ethernet,
12 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
13
Heiko Stübneref6db5e2017-02-18 19:46:36 +010014config ROCKCHIP_RK3188
15 bool "Support Rockchip RK3188"
16 select CPU_V7
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080017 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010018 select SUPPORT_SPL
19 select SUPPORT_TPL
20 select SPL
Philipp Tomsich16c689c2017-10-10 16:21:15 +020021 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020022 select BOARD_LATE_INIT
Heiko Stübneref6db5e2017-02-18 19:46:36 +010023 select ROCKCHIP_BROM_HELPER
24 help
25 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
26 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
27 video interfaces, several memory options and video codec support.
28 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
29 UART, SPI, I2C and PWMs.
30
Kever Yang57d4dbf2017-06-23 17:17:52 +080031config ROCKCHIP_RK322X
32 bool "Support Rockchip RK3228/RK3229"
33 select CPU_V7
34 select SUPPORT_SPL
35 select SPL
36 select ROCKCHIP_BROM_HELPER
37 select DEBUG_UART_BOARD_INIT
38 help
39 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
40 including NEON and GPU, Mali-400 graphics, several DDR3 options
41 and video codec support. Peripherals include Gigabit Ethernet,
42 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
43
Simon Glass2cffe662015-08-30 16:55:38 -060044config ROCKCHIP_RK3288
45 bool "Support Rockchip RK3288"
Andreas Färber6c427032016-07-14 05:09:26 +020046 select CPU_V7
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080047 select SPL_BOARD_INIT if SPL
Kever Yang0d3d7832016-07-19 21:16:59 +080048 select SUPPORT_SPL
49 select SPL
Simon Glass2cffe662015-08-30 16:55:38 -060050 help
51 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
52 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
53 video interfaces supporting HDMI and eDP, several DDR3 options
54 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +010055 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -060056
Kever Yangec02b3c2017-02-23 15:37:51 +080057config ROCKCHIP_RK3328
58 bool "Support Rockchip RK3328"
59 select ARM64
60 help
61 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
62 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
63 video interfaces supporting HDMI and eDP, several DDR3 options
64 and video codec support. Peripherals include Gigabit Ethernet,
65 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
66
Andreas Färber9e3ad682017-05-15 17:51:18 +080067config ROCKCHIP_RK3368
68 bool "Support Rockchip RK3368"
69 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +020070 select SUPPORT_SPL
71 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +020072 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
73 select TPL_NEEDS_SEPARATE_STACK if TPL
Philipp Tomsich84af43e2017-06-11 23:46:25 +020074 imply SPL_SEPARATE_BSS
75 imply SPL_SERIAL_SUPPORT
76 imply TPL_SERIAL_SUPPORT
Philipp Tomsich84af43e2017-06-11 23:46:25 +020077 select DEBUG_UART_BOARD_INIT
Andreas Färber9e3ad682017-05-15 17:51:18 +080078 select SYS_NS16550
79 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +020080 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
81 into a big and little cluster with 4 cores each) Cortex-A53 including
82 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
83 (for the little cluster), PowerVR G6110 based graphics, one video
84 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
85 video codec support.
86
87 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
88 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +080089
Philipp Tomsichcbacb402017-08-02 21:26:18 +020090if ROCKCHIP_RK3368
91
92config TPL_LDSCRIPT
93 default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
94
Philipp Tomsich7d1319b2017-07-28 20:20:41 +020095config TPL_TEXT_BASE
96 default 0xff8c1000
97
98config TPL_MAX_SIZE
99 default 28672
100
101config TPL_STACK
102 default 0xff8cffff
103
Philipp Tomsichcbacb402017-08-02 21:26:18 +0200104endif
105
Kever Yang0d3d7832016-07-19 21:16:59 +0800106config ROCKCHIP_RK3399
107 bool "Support Rockchip RK3399"
108 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800109 select SUPPORT_SPL
110 select SPL
111 select SPL_SEPARATE_BSS
Philipp Tomsichd17d8cf2017-07-26 12:29:01 +0200112 select SPL_SERIAL_SUPPORT
113 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich41029e62017-04-01 12:59:25 +0200114 select DEBUG_UART_BOARD_INIT
Kever Yang0d3d7832016-07-19 21:16:59 +0800115 help
116 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
117 and quad-core Cortex-A53.
118 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
119 video interfaces supporting HDMI and eDP, several DDR3 options
120 and video codec support. Peripherals include Gigabit Ethernet,
121 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
122
Andy Yan2d982da2017-06-01 18:00:55 +0800123config ROCKCHIP_RV1108
124 bool "Support Rockchip RV1108"
125 select CPU_V7
126 help
127 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
128 and a DSP.
129
Philipp Tomsich798370f2017-06-29 11:21:15 +0200130config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800131 bool "SPL returns to bootrom"
132 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100133 select ROCKCHIP_BROM_HELPER
Philipp Tomsich798370f2017-06-29 11:21:15 +0200134 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800135 help
136 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
137 SPL will return to the boot rom, which will then load the U-Boot
138 binary to keep going on.
139
Philipp Tomsich798370f2017-06-29 11:21:15 +0200140config TPL_ROCKCHIP_BACK_TO_BROM
141 bool "TPL returns to bootrom"
142 default y if ROCKCHIP_RK3368
143 select ROCKCHIP_BROM_HELPER
144 depends on TPL
145 help
146 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
147 SPL will return to the boot rom, which will then load the U-Boot
148 binary to keep going on.
149
Kever Yange484f772017-04-20 17:03:46 +0800150config ROCKCHIP_SPL_RESERVE_IRAM
151 hex "Size of IRAM reserved in SPL"
152 default 0x4000
153 help
154 SPL may need reserve memory for firmware loaded by SPL, whose load
155 address is in IRAM and may overlay with SPL text area if not
156 reserved.
157
Heiko Stübner355a8802017-02-18 19:46:25 +0100158config ROCKCHIP_BROM_HELPER
159 bool
160
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200161config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
162 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
163 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
164 help
165 Some Rockchip BROM variants (e.g. on the RK3188) load the
166 first stage in segments and enter multiple times. E.g. on
167 the RK3188, the first 1KB of the first stage are loaded
168 first and entered; after returning to the BROM, the
169 remainder of the first stage is loaded, but the BROM
170 re-enters at the same address/to the same code as previously.
171
172 This enables support code in the BOOT0 hook for the SPL stage
173 to allow multiple entries.
174
175config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
176 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
177 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
178 help
179 Some Rockchip BROM variants (e.g. on the RK3188) load the
180 first stage in segments and enter multiple times. E.g. on
181 the RK3188, the first 1KB of the first stage are loaded
182 first and entered; after returning to the BROM, the
183 remainder of the first stage is loaded, but the BROM
184 re-enters at the same address/to the same code as previously.
185
186 This enables support code in the BOOT0 hook for the TPL stage
187 to allow multiple entries.
188
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400189config SPL_MMC_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200190 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400191
huang lin1115b642015-11-17 14:20:27 +0800192source "arch/arm/mach-rockchip/rk3036/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100193source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800194source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200195source "arch/arm/mach-rockchip/rk3288/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800196source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800197source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800198source "arch/arm/mach-rockchip/rk3399/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800199source "arch/arm/mach-rockchip/rv1108/Kconfig"
Simon Glass2cffe662015-08-30 16:55:38 -0600200endif