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Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stübner5c91e2b2016-07-16 00:17:15 +02003config ROCKCHIP_RK3036
4 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +05305 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +08006 select SUPPORT_SPL
7 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +08008 imply USB_FUNCTION_ROCKUSB
9 imply CMD_ROCKUSB
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020010 help
11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
13 and video codec support. Peripherals include Gigabit Ethernet,
14 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
15
Kever Yangaa827752017-11-28 16:04:16 +080016config ROCKCHIP_RK3128
17 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053018 select CPU_V7A
Kever Yangaa827752017-11-28 16:04:16 +080019 help
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
22 and video codec support. Peripherals include Gigabit Ethernet,
23 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
24
Heiko Stübneref6db5e2017-02-18 19:46:36 +010025config ROCKCHIP_RK3188
26 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053027 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080028 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010029 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010030 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020031 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020032 select SPL_REGMAP
33 select SPL_SYSCON
34 select SPL_RAM
35 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich16c689c2017-10-10 16:21:15 +020036 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020037 select BOARD_LATE_INIT
Heiko Stübneref6db5e2017-02-18 19:46:36 +010038 select ROCKCHIP_BROM_HELPER
39 help
40 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
41 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
42 video interfaces, several memory options and video codec support.
43 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
44 UART, SPI, I2C and PWMs.
45
Kever Yang57d4dbf2017-06-23 17:17:52 +080046config ROCKCHIP_RK322X
47 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053048 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080049 select SUPPORT_SPL
Kever Yangaff40c62019-04-02 20:41:24 +080050 select SUPPORT_TPL
Kever Yang57d4dbf2017-06-23 17:17:52 +080051 select SPL
Kever Yangaff40c62019-04-02 20:41:24 +080052 select SPL_DM
53 select SPL_OF_LIBFDT
54 select TPL
55 select TPL_DM
56 select TPL_OF_LIBFDT
57 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
58 select TPL_NEEDS_SEPARATE_STACK if TPL
59 select SPL_DRIVERS_MISC_SUPPORT
60 imply SPL_SERIAL_SUPPORT
61 imply TPL_SERIAL_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +080062 select ROCKCHIP_BROM_HELPER
Kever Yangaff40c62019-04-02 20:41:24 +080063 select TPL_LIBCOMMON_SUPPORT
64 select TPL_LIBGENERIC_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +080065 help
66 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
67 including NEON and GPU, Mali-400 graphics, several DDR3 options
68 and video codec support. Peripherals include Gigabit Ethernet,
69 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
70
Kever Yangaff40c62019-04-02 20:41:24 +080071if ROCKCHIP_RK322X
72
73config TPL_TEXT_BASE
74 default 0x10081000
75
76config TPL_MAX_SIZE
77 default 28672
78
79config TPL_STACK
80 default 0x10088000
81
82endif
83
Simon Glass2cffe662015-08-30 16:55:38 -060084config ROCKCHIP_RK3288
85 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053086 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080087 select SPL_BOARD_INIT if SPL
Kever Yang0d3d7832016-07-19 21:16:59 +080088 select SUPPORT_SPL
89 select SPL
Kever Yangf7c0a332019-07-02 11:43:05 +080090 select SUPPORT_TPL
91 imply TPL_BOOTROM_SUPPORT
92 imply TPL_CLK
93 imply TPL_DM
94 imply TPL_DRIVERS_MISC_SUPPORT
95 imply TPL_LIBCOMMON_SUPPORT
96 imply TPL_LIBGENERIC_SUPPORT
97 imply TPL_NEEDS_SEPARATE_TEXT_BASE
Kever Yangb36e7092019-07-02 11:43:06 +080098 imply TPL_NEEDS_SEPARATE_STACK
Kever Yangf7c0a332019-07-02 11:43:05 +080099 imply TPL_OF_CONTROL
100 imply TPL_OF_PLATDATA
101 imply TPL_RAM
102 imply TPL_REGMAP
103 imply TPL_SERIAL_SUPPORT
104 imply TPL_SYSCON
Eddie Caib3501fe2017-12-15 08:17:13 +0800105 imply USB_FUNCTION_ROCKUSB
106 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -0600107 help
108 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
109 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
110 video interfaces supporting HDMI and eDP, several DDR3 options
111 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +0100112 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -0600113
Jagan Tekie5df8342018-02-23 13:13:10 +0530114if ROCKCHIP_RK3288
115
Jagan Teki843ac352018-02-23 13:13:11 +0530116config TPL_TEXT_BASE
117 default 0xff704000
118
Tom Rinie34a2f32019-01-22 17:09:25 -0500119config TPL_MAX_SIZE
120 default 32768
121
Kever Yangb36e7092019-07-02 11:43:06 +0800122config TPL_STACK
123 default 0xff718000
124
Jagan Tekie5df8342018-02-23 13:13:10 +0530125endif
126
Kever Yangec02b3c2017-02-23 15:37:51 +0800127config ROCKCHIP_RK3328
128 bool "Support Rockchip RK3328"
129 select ARM64
Kever Yang07be6692019-06-09 00:27:15 +0300130 select SUPPORT_SPL
131 select SPL
132 imply SPL_SERIAL_SUPPORT
133 imply SPL_SEPARATE_BSS
134 select ENABLE_ARM_SOC_BOOT0_HOOK
135 select DEBUG_UART_BOARD_INIT
136 select SYS_NS16550
Kever Yangec02b3c2017-02-23 15:37:51 +0800137 help
138 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
139 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
140 video interfaces supporting HDMI and eDP, several DDR3 options
141 and video codec support. Peripherals include Gigabit Ethernet,
142 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
143
Andreas Färber9e3ad682017-05-15 17:51:18 +0800144config ROCKCHIP_RK3368
145 bool "Support Rockchip RK3368"
146 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200147 select SUPPORT_SPL
148 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200149 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
150 select TPL_NEEDS_SEPARATE_STACK if TPL
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200151 imply SPL_SEPARATE_BSS
152 imply SPL_SERIAL_SUPPORT
153 imply TPL_SERIAL_SUPPORT
Andreas Färber9e3ad682017-05-15 17:51:18 +0800154 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200155 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
156 into a big and little cluster with 4 cores each) Cortex-A53 including
157 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
158 (for the little cluster), PowerVR G6110 based graphics, one video
159 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
160 video codec support.
161
162 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
163 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800164
Philipp Tomsichcbacb402017-08-02 21:26:18 +0200165if ROCKCHIP_RK3368
166
Philipp Tomsich7d1319b2017-07-28 20:20:41 +0200167config TPL_TEXT_BASE
168 default 0xff8c1000
169
170config TPL_MAX_SIZE
171 default 28672
172
173config TPL_STACK
174 default 0xff8cffff
175
Philipp Tomsichcbacb402017-08-02 21:26:18 +0200176endif
177
Kever Yang0d3d7832016-07-19 21:16:59 +0800178config ROCKCHIP_RK3399
179 bool "Support Rockchip RK3399"
180 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800181 select SUPPORT_SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800182 select SUPPORT_TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800183 select SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530184 select SPL_ATF
185 select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Jagan Tekice063b92019-06-21 00:25:03 +0530186 select SPL_BOARD_INIT if SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530187 select SPL_LOAD_FIT
188 select SPL_CLK if SPL
189 select SPL_PINCTRL if SPL
190 select SPL_RAM if SPL
191 select SPL_REGMAP if SPL
192 select SPL_SYSCON if SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800193 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
194 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800195 select SPL_SEPARATE_BSS
Philipp Tomsichd17d8cf2017-07-26 12:29:01 +0200196 select SPL_SERIAL_SUPPORT
197 select SPL_DRIVERS_MISC_SUPPORT
Jagan Tekicd433892019-05-08 11:11:43 +0530198 select CLK
199 select FIT
200 select PINCTRL
201 select RAM
202 select REGMAP
203 select SYSCON
204 select DM_PMIC
205 select DM_REGULATOR_FIXED
Andy Yan70378cb2017-10-11 15:00:16 +0800206 select BOARD_LATE_INIT
Andy Yand2349d92017-10-11 15:00:49 +0800207 select ROCKCHIP_BROM_HELPER
Kever Yangfca798d2018-11-09 11:18:15 +0800208 imply TPL_SERIAL_SUPPORT
209 imply TPL_LIBCOMMON_SUPPORT
210 imply TPL_LIBGENERIC_SUPPORT
211 imply TPL_SYS_MALLOC_SIMPLE
Jagan Teki64a44b82019-06-21 00:25:06 +0530212 imply TPL_BOARD_INIT
Kever Yangfca798d2018-11-09 11:18:15 +0800213 imply TPL_BOOTROM_SUPPORT
214 imply TPL_DRIVERS_MISC_SUPPORT
215 imply TPL_OF_CONTROL
216 imply TPL_DM
217 imply TPL_REGMAP
218 imply TPL_SYSCON
219 imply TPL_RAM
220 imply TPL_CLK
221 imply TPL_TINY_MEMSET
Kever Yang0d3d7832016-07-19 21:16:59 +0800222 help
223 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
224 and quad-core Cortex-A53.
225 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
226 video interfaces supporting HDMI and eDP, several DDR3 options
227 and video codec support. Peripherals include Gigabit Ethernet,
228 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
229
Kever Yangfca798d2018-11-09 11:18:15 +0800230if ROCKCHIP_RK3399
231
232config TPL_LDSCRIPT
233 default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
234
235config TPL_TEXT_BASE
236 default 0xff8c2000
237
238config TPL_MAX_SIZE
239 default 188416
240
241config TPL_STACK
242 default 0xff8effff
243
244endif
245
Andy Yan2d982da2017-06-01 18:00:55 +0800246config ROCKCHIP_RV1108
247 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530248 select CPU_V7A
Andy Yan2d982da2017-06-01 18:00:55 +0800249 help
250 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
251 and a DSP.
252
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200253config ROCKCHIP_USB_UART
254 bool "Route uart output to usb pins"
255 help
256 Rockchip SoCs have the ability to route the signals of the debug
257 uart through the d+ and d- pins of a specific usb phy to enable
258 some form of closed-case debugging. With this option supported
259 SoCs will enable this routing as a debug measure.
260
Philipp Tomsich798370f2017-06-29 11:21:15 +0200261config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800262 bool "SPL returns to bootrom"
263 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100264 select ROCKCHIP_BROM_HELPER
Philipp Tomsich798370f2017-06-29 11:21:15 +0200265 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800266 help
267 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
268 SPL will return to the boot rom, which will then load the U-Boot
269 binary to keep going on.
270
Philipp Tomsich798370f2017-06-29 11:21:15 +0200271config TPL_ROCKCHIP_BACK_TO_BROM
272 bool "TPL returns to bootrom"
Kever Yangfca798d2018-11-09 11:18:15 +0800273 default y
Philipp Tomsich798370f2017-06-29 11:21:15 +0200274 select ROCKCHIP_BROM_HELPER
275 depends on TPL
276 help
277 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
278 SPL will return to the boot rom, which will then load the U-Boot
279 binary to keep going on.
280
Andy Yan70378cb2017-10-11 15:00:16 +0800281config ROCKCHIP_BOOT_MODE_REG
282 hex "Rockchip boot mode flag register address"
283 default 0x200081c8 if ROCKCHIP_RK3036
284 default 0x20004040 if ROCKCHIP_RK3188
285 default 0x110005c8 if ROCKCHIP_RK322X
286 default 0xff730094 if ROCKCHIP_RK3288
287 default 0xff738200 if ROCKCHIP_RK3368
288 default 0xff320300 if ROCKCHIP_RK3399
289 default 0x10300580 if ROCKCHIP_RV1108
290 default 0
291 help
Kever Yang9fbe17c2019-03-28 11:01:23 +0800292 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yan70378cb2017-10-11 15:00:16 +0800293 according to the value from this register.
294
Kever Yange484f772017-04-20 17:03:46 +0800295config ROCKCHIP_SPL_RESERVE_IRAM
296 hex "Size of IRAM reserved in SPL"
Kever Yang60a50072017-12-18 15:13:19 +0800297 default 0
Kever Yange484f772017-04-20 17:03:46 +0800298 help
299 SPL may need reserve memory for firmware loaded by SPL, whose load
300 address is in IRAM and may overlay with SPL text area if not
301 reserved.
302
Heiko Stübner355a8802017-02-18 19:46:25 +0100303config ROCKCHIP_BROM_HELPER
304 bool
305
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200306config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
307 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
308 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
309 help
310 Some Rockchip BROM variants (e.g. on the RK3188) load the
311 first stage in segments and enter multiple times. E.g. on
312 the RK3188, the first 1KB of the first stage are loaded
313 first and entered; after returning to the BROM, the
314 remainder of the first stage is loaded, but the BROM
315 re-enters at the same address/to the same code as previously.
316
317 This enables support code in the BOOT0 hook for the SPL stage
318 to allow multiple entries.
319
320config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
321 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
322 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
323 help
324 Some Rockchip BROM variants (e.g. on the RK3188) load the
325 first stage in segments and enter multiple times. E.g. on
326 the RK3188, the first 1KB of the first stage are loaded
327 first and entered; after returning to the BROM, the
328 remainder of the first stage is loaded, but the BROM
329 re-enters at the same address/to the same code as previously.
330
331 This enables support code in the BOOT0 hook for the TPL stage
332 to allow multiple entries.
333
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400334config SPL_MMC_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200335 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400336
huang lin1115b642015-11-17 14:20:27 +0800337source "arch/arm/mach-rockchip/rk3036/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800338source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100339source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800340source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200341source "arch/arm/mach-rockchip/rk3288/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800342source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800343source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800344source "arch/arm/mach-rockchip/rk3399/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800345source "arch/arm/mach-rockchip/rv1108/Kconfig"
Simon Glass2cffe662015-08-30 16:55:38 -0600346endif