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Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stübner5c91e2b2016-07-16 00:17:15 +02003config ROCKCHIP_RK3036
4 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +05305 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +08006 select SUPPORT_SPL
7 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +08008 imply USB_FUNCTION_ROCKUSB
9 imply CMD_ROCKUSB
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020010 help
11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
13 and video codec support. Peripherals include Gigabit Ethernet,
14 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
15
Kever Yangaa827752017-11-28 16:04:16 +080016config ROCKCHIP_RK3128
17 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053018 select CPU_V7A
Kever Yangaa827752017-11-28 16:04:16 +080019 help
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
22 and video codec support. Peripherals include Gigabit Ethernet,
23 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
24
Heiko Stübneref6db5e2017-02-18 19:46:36 +010025config ROCKCHIP_RK3188
26 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053027 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080028 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010029 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010030 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020031 select SPL_CLK
32 select SPL_PINCTRL
33 select SPL_REGMAP
34 select SPL_SYSCON
35 select SPL_RAM
36 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich16c689c2017-10-10 16:21:15 +020037 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangd2af98b2018-11-29 10:07:38 +080038 select DEBUG_UART_BOARD_INIT
Heiko Stübner015f69a2017-04-06 00:19:36 +020039 select BOARD_LATE_INIT
Heiko Stübneref6db5e2017-02-18 19:46:36 +010040 select ROCKCHIP_BROM_HELPER
41 help
42 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
43 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
44 video interfaces, several memory options and video codec support.
45 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
46 UART, SPI, I2C and PWMs.
47
Kever Yang57d4dbf2017-06-23 17:17:52 +080048config ROCKCHIP_RK322X
49 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053050 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080051 select SUPPORT_SPL
52 select SPL
53 select ROCKCHIP_BROM_HELPER
54 select DEBUG_UART_BOARD_INIT
55 help
56 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
57 including NEON and GPU, Mali-400 graphics, several DDR3 options
58 and video codec support. Peripherals include Gigabit Ethernet,
59 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
60
Simon Glass2cffe662015-08-30 16:55:38 -060061config ROCKCHIP_RK3288
62 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053063 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080064 select SPL_BOARD_INIT if SPL
Kever Yang0d3d7832016-07-19 21:16:59 +080065 select SUPPORT_SPL
66 select SPL
Eddie Caib3501fe2017-12-15 08:17:13 +080067 imply USB_FUNCTION_ROCKUSB
68 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -060069 help
70 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
71 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
72 video interfaces supporting HDMI and eDP, several DDR3 options
73 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +010074 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -060075
Jagan Tekie5df8342018-02-23 13:13:10 +053076if ROCKCHIP_RK3288
77
78config TPL_LDSCRIPT
79 default "arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds"
80
Jagan Teki843ac352018-02-23 13:13:11 +053081config TPL_TEXT_BASE
82 default 0xff704000
83
Tom Rinie34a2f32019-01-22 17:09:25 -050084config TPL_MAX_SIZE
85 default 32768
86
Jagan Tekie5df8342018-02-23 13:13:10 +053087endif
88
Kever Yangec02b3c2017-02-23 15:37:51 +080089config ROCKCHIP_RK3328
90 bool "Support Rockchip RK3328"
91 select ARM64
92 help
93 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
94 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
95 video interfaces supporting HDMI and eDP, several DDR3 options
96 and video codec support. Peripherals include Gigabit Ethernet,
97 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
98
Andreas Färber9e3ad682017-05-15 17:51:18 +080099config ROCKCHIP_RK3368
100 bool "Support Rockchip RK3368"
101 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200102 select SUPPORT_SPL
103 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200104 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
105 select TPL_NEEDS_SEPARATE_STACK if TPL
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200106 imply SPL_SEPARATE_BSS
107 imply SPL_SERIAL_SUPPORT
108 imply TPL_SERIAL_SUPPORT
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200109 select DEBUG_UART_BOARD_INIT
Andreas Färber9e3ad682017-05-15 17:51:18 +0800110 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200111 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
112 into a big and little cluster with 4 cores each) Cortex-A53 including
113 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
114 (for the little cluster), PowerVR G6110 based graphics, one video
115 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
116 video codec support.
117
118 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
119 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800120
Philipp Tomsichcbacb402017-08-02 21:26:18 +0200121if ROCKCHIP_RK3368
122
123config TPL_LDSCRIPT
124 default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
125
Philipp Tomsich7d1319b2017-07-28 20:20:41 +0200126config TPL_TEXT_BASE
127 default 0xff8c1000
128
129config TPL_MAX_SIZE
130 default 28672
131
132config TPL_STACK
133 default 0xff8cffff
134
Philipp Tomsichcbacb402017-08-02 21:26:18 +0200135endif
136
Kever Yang0d3d7832016-07-19 21:16:59 +0800137config ROCKCHIP_RK3399
138 bool "Support Rockchip RK3399"
139 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800140 select SUPPORT_SPL
141 select SPL
142 select SPL_SEPARATE_BSS
Philipp Tomsichd17d8cf2017-07-26 12:29:01 +0200143 select SPL_SERIAL_SUPPORT
144 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich41029e62017-04-01 12:59:25 +0200145 select DEBUG_UART_BOARD_INIT
Andy Yan70378cb2017-10-11 15:00:16 +0800146 select BOARD_LATE_INIT
Andy Yand2349d92017-10-11 15:00:49 +0800147 select ROCKCHIP_BROM_HELPER
Kever Yang0d3d7832016-07-19 21:16:59 +0800148 help
149 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
150 and quad-core Cortex-A53.
151 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
152 video interfaces supporting HDMI and eDP, several DDR3 options
153 and video codec support. Peripherals include Gigabit Ethernet,
154 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
155
Andy Yan2d982da2017-06-01 18:00:55 +0800156config ROCKCHIP_RV1108
157 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530158 select CPU_V7A
Andy Yan2d982da2017-06-01 18:00:55 +0800159 help
160 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
161 and a DSP.
162
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200163config ROCKCHIP_USB_UART
164 bool "Route uart output to usb pins"
165 help
166 Rockchip SoCs have the ability to route the signals of the debug
167 uart through the d+ and d- pins of a specific usb phy to enable
168 some form of closed-case debugging. With this option supported
169 SoCs will enable this routing as a debug measure.
170
Philipp Tomsich798370f2017-06-29 11:21:15 +0200171config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800172 bool "SPL returns to bootrom"
173 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100174 select ROCKCHIP_BROM_HELPER
Philipp Tomsich798370f2017-06-29 11:21:15 +0200175 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800176 help
177 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
178 SPL will return to the boot rom, which will then load the U-Boot
179 binary to keep going on.
180
Philipp Tomsich798370f2017-06-29 11:21:15 +0200181config TPL_ROCKCHIP_BACK_TO_BROM
182 bool "TPL returns to bootrom"
183 default y if ROCKCHIP_RK3368
184 select ROCKCHIP_BROM_HELPER
185 depends on TPL
186 help
187 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
188 SPL will return to the boot rom, which will then load the U-Boot
189 binary to keep going on.
190
Andy Yan70378cb2017-10-11 15:00:16 +0800191config ROCKCHIP_BOOT_MODE_REG
192 hex "Rockchip boot mode flag register address"
193 default 0x200081c8 if ROCKCHIP_RK3036
194 default 0x20004040 if ROCKCHIP_RK3188
195 default 0x110005c8 if ROCKCHIP_RK322X
196 default 0xff730094 if ROCKCHIP_RK3288
197 default 0xff738200 if ROCKCHIP_RK3368
198 default 0xff320300 if ROCKCHIP_RK3399
199 default 0x10300580 if ROCKCHIP_RV1108
200 default 0
201 help
202 The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
203 according to the value from this register.
204
Kever Yange484f772017-04-20 17:03:46 +0800205config ROCKCHIP_SPL_RESERVE_IRAM
206 hex "Size of IRAM reserved in SPL"
Kever Yang60a50072017-12-18 15:13:19 +0800207 default 0
Kever Yange484f772017-04-20 17:03:46 +0800208 help
209 SPL may need reserve memory for firmware loaded by SPL, whose load
210 address is in IRAM and may overlay with SPL text area if not
211 reserved.
212
Heiko Stübner355a8802017-02-18 19:46:25 +0100213config ROCKCHIP_BROM_HELPER
214 bool
215
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200216config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
217 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
218 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
219 help
220 Some Rockchip BROM variants (e.g. on the RK3188) load the
221 first stage in segments and enter multiple times. E.g. on
222 the RK3188, the first 1KB of the first stage are loaded
223 first and entered; after returning to the BROM, the
224 remainder of the first stage is loaded, but the BROM
225 re-enters at the same address/to the same code as previously.
226
227 This enables support code in the BOOT0 hook for the SPL stage
228 to allow multiple entries.
229
230config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
231 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
232 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
233 help
234 Some Rockchip BROM variants (e.g. on the RK3188) load the
235 first stage in segments and enter multiple times. E.g. on
236 the RK3188, the first 1KB of the first stage are loaded
237 first and entered; after returning to the BROM, the
238 remainder of the first stage is loaded, but the BROM
239 re-enters at the same address/to the same code as previously.
240
241 This enables support code in the BOOT0 hook for the TPL stage
242 to allow multiple entries.
243
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400244config SPL_MMC_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200245 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400246
huang lin1115b642015-11-17 14:20:27 +0800247source "arch/arm/mach-rockchip/rk3036/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800248source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100249source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800250source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200251source "arch/arm/mach-rockchip/rk3288/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800252source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800253source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800254source "arch/arm/mach-rockchip/rk3399/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800255source "arch/arm/mach-rockchip/rv1108/Kconfig"
Simon Glass2cffe662015-08-30 16:55:38 -0600256endif