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Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stübner5c91e2b2016-07-16 00:17:15 +02003config ROCKCHIP_RK3036
4 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +05305 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +08006 select SUPPORT_SPL
7 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +08008 imply USB_FUNCTION_ROCKUSB
9 imply CMD_ROCKUSB
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020010 help
11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
13 and video codec support. Peripherals include Gigabit Ethernet,
14 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
15
Kever Yangaa827752017-11-28 16:04:16 +080016config ROCKCHIP_RK3128
17 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053018 select CPU_V7A
Kever Yangaa827752017-11-28 16:04:16 +080019 help
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
22 and video codec support. Peripherals include Gigabit Ethernet,
23 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
24
Heiko Stübneref6db5e2017-02-18 19:46:36 +010025config ROCKCHIP_RK3188
26 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053027 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080028 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010029 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010030 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020031 select SPL_CLK
32 select SPL_PINCTRL
33 select SPL_REGMAP
34 select SPL_SYSCON
35 select SPL_RAM
36 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich16c689c2017-10-10 16:21:15 +020037 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangd2af98b2018-11-29 10:07:38 +080038 select DEBUG_UART_BOARD_INIT
Heiko Stübner015f69a2017-04-06 00:19:36 +020039 select BOARD_LATE_INIT
Heiko Stübneref6db5e2017-02-18 19:46:36 +010040 select ROCKCHIP_BROM_HELPER
41 help
42 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
43 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
44 video interfaces, several memory options and video codec support.
45 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
46 UART, SPI, I2C and PWMs.
47
Kever Yang57d4dbf2017-06-23 17:17:52 +080048config ROCKCHIP_RK322X
49 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053050 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080051 select SUPPORT_SPL
52 select SPL
53 select ROCKCHIP_BROM_HELPER
54 select DEBUG_UART_BOARD_INIT
55 help
56 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
57 including NEON and GPU, Mali-400 graphics, several DDR3 options
58 and video codec support. Peripherals include Gigabit Ethernet,
59 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
60
Simon Glass2cffe662015-08-30 16:55:38 -060061config ROCKCHIP_RK3288
62 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053063 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080064 select SPL_BOARD_INIT if SPL
Kever Yang0d3d7832016-07-19 21:16:59 +080065 select SUPPORT_SPL
66 select SPL
Eddie Caib3501fe2017-12-15 08:17:13 +080067 imply USB_FUNCTION_ROCKUSB
68 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -060069 help
70 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
71 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
72 video interfaces supporting HDMI and eDP, several DDR3 options
73 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +010074 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -060075
Jagan Tekie5df8342018-02-23 13:13:10 +053076if ROCKCHIP_RK3288
77
78config TPL_LDSCRIPT
79 default "arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds"
80
Jagan Teki843ac352018-02-23 13:13:11 +053081config TPL_TEXT_BASE
82 default 0xff704000
83
Jagan Tekie5df8342018-02-23 13:13:10 +053084endif
85
Kever Yangec02b3c2017-02-23 15:37:51 +080086config ROCKCHIP_RK3328
87 bool "Support Rockchip RK3328"
88 select ARM64
89 help
90 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
91 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
92 video interfaces supporting HDMI and eDP, several DDR3 options
93 and video codec support. Peripherals include Gigabit Ethernet,
94 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
95
Andreas Färber9e3ad682017-05-15 17:51:18 +080096config ROCKCHIP_RK3368
97 bool "Support Rockchip RK3368"
98 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +020099 select SUPPORT_SPL
100 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200101 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
102 select TPL_NEEDS_SEPARATE_STACK if TPL
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200103 imply SPL_SEPARATE_BSS
104 imply SPL_SERIAL_SUPPORT
105 imply TPL_SERIAL_SUPPORT
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200106 select DEBUG_UART_BOARD_INIT
Andreas Färber9e3ad682017-05-15 17:51:18 +0800107 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200108 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
109 into a big and little cluster with 4 cores each) Cortex-A53 including
110 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
111 (for the little cluster), PowerVR G6110 based graphics, one video
112 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
113 video codec support.
114
115 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
116 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800117
Philipp Tomsichcbacb402017-08-02 21:26:18 +0200118if ROCKCHIP_RK3368
119
120config TPL_LDSCRIPT
121 default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
122
Philipp Tomsich7d1319b2017-07-28 20:20:41 +0200123config TPL_TEXT_BASE
124 default 0xff8c1000
125
126config TPL_MAX_SIZE
127 default 28672
128
129config TPL_STACK
130 default 0xff8cffff
131
Philipp Tomsichcbacb402017-08-02 21:26:18 +0200132endif
133
Kever Yang0d3d7832016-07-19 21:16:59 +0800134config ROCKCHIP_RK3399
135 bool "Support Rockchip RK3399"
136 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800137 select SUPPORT_SPL
138 select SPL
139 select SPL_SEPARATE_BSS
Philipp Tomsichd17d8cf2017-07-26 12:29:01 +0200140 select SPL_SERIAL_SUPPORT
141 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich41029e62017-04-01 12:59:25 +0200142 select DEBUG_UART_BOARD_INIT
Andy Yan70378cb2017-10-11 15:00:16 +0800143 select BOARD_LATE_INIT
Andy Yand2349d92017-10-11 15:00:49 +0800144 select ROCKCHIP_BROM_HELPER
Kever Yang0d3d7832016-07-19 21:16:59 +0800145 help
146 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
147 and quad-core Cortex-A53.
148 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
149 video interfaces supporting HDMI and eDP, several DDR3 options
150 and video codec support. Peripherals include Gigabit Ethernet,
151 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
152
Andy Yan2d982da2017-06-01 18:00:55 +0800153config ROCKCHIP_RV1108
154 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530155 select CPU_V7A
Andy Yan2d982da2017-06-01 18:00:55 +0800156 help
157 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
158 and a DSP.
159
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200160config ROCKCHIP_USB_UART
161 bool "Route uart output to usb pins"
162 help
163 Rockchip SoCs have the ability to route the signals of the debug
164 uart through the d+ and d- pins of a specific usb phy to enable
165 some form of closed-case debugging. With this option supported
166 SoCs will enable this routing as a debug measure.
167
Philipp Tomsich798370f2017-06-29 11:21:15 +0200168config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800169 bool "SPL returns to bootrom"
170 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100171 select ROCKCHIP_BROM_HELPER
Philipp Tomsich798370f2017-06-29 11:21:15 +0200172 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800173 help
174 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
175 SPL will return to the boot rom, which will then load the U-Boot
176 binary to keep going on.
177
Philipp Tomsich798370f2017-06-29 11:21:15 +0200178config TPL_ROCKCHIP_BACK_TO_BROM
179 bool "TPL returns to bootrom"
180 default y if ROCKCHIP_RK3368
181 select ROCKCHIP_BROM_HELPER
182 depends on TPL
183 help
184 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
185 SPL will return to the boot rom, which will then load the U-Boot
186 binary to keep going on.
187
Andy Yan70378cb2017-10-11 15:00:16 +0800188config ROCKCHIP_BOOT_MODE_REG
189 hex "Rockchip boot mode flag register address"
190 default 0x200081c8 if ROCKCHIP_RK3036
191 default 0x20004040 if ROCKCHIP_RK3188
192 default 0x110005c8 if ROCKCHIP_RK322X
193 default 0xff730094 if ROCKCHIP_RK3288
194 default 0xff738200 if ROCKCHIP_RK3368
195 default 0xff320300 if ROCKCHIP_RK3399
196 default 0x10300580 if ROCKCHIP_RV1108
197 default 0
198 help
199 The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
200 according to the value from this register.
201
Kever Yange484f772017-04-20 17:03:46 +0800202config ROCKCHIP_SPL_RESERVE_IRAM
203 hex "Size of IRAM reserved in SPL"
Kever Yang60a50072017-12-18 15:13:19 +0800204 default 0
Kever Yange484f772017-04-20 17:03:46 +0800205 help
206 SPL may need reserve memory for firmware loaded by SPL, whose load
207 address is in IRAM and may overlay with SPL text area if not
208 reserved.
209
Heiko Stübner355a8802017-02-18 19:46:25 +0100210config ROCKCHIP_BROM_HELPER
211 bool
212
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200213config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
214 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
215 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
216 help
217 Some Rockchip BROM variants (e.g. on the RK3188) load the
218 first stage in segments and enter multiple times. E.g. on
219 the RK3188, the first 1KB of the first stage are loaded
220 first and entered; after returning to the BROM, the
221 remainder of the first stage is loaded, but the BROM
222 re-enters at the same address/to the same code as previously.
223
224 This enables support code in the BOOT0 hook for the SPL stage
225 to allow multiple entries.
226
227config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
228 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
229 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
230 help
231 Some Rockchip BROM variants (e.g. on the RK3188) load the
232 first stage in segments and enter multiple times. E.g. on
233 the RK3188, the first 1KB of the first stage are loaded
234 first and entered; after returning to the BROM, the
235 remainder of the first stage is loaded, but the BROM
236 re-enters at the same address/to the same code as previously.
237
238 This enables support code in the BOOT0 hook for the TPL stage
239 to allow multiple entries.
240
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400241config SPL_MMC_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200242 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400243
huang lin1115b642015-11-17 14:20:27 +0800244source "arch/arm/mach-rockchip/rk3036/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800245source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100246source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800247source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200248source "arch/arm/mach-rockchip/rk3288/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800249source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800250source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800251source "arch/arm/mach-rockchip/rk3399/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800252source "arch/arm/mach-rockchip/rv1108/Kconfig"
Simon Glass2cffe662015-08-30 16:55:38 -0600253endif