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Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stübner5c91e2b2016-07-16 00:17:15 +02003config ROCKCHIP_RK3036
4 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +05305 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +08006 select SUPPORT_SPL
7 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +08008 imply USB_FUNCTION_ROCKUSB
9 imply CMD_ROCKUSB
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020010 help
11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
13 and video codec support. Peripherals include Gigabit Ethernet,
14 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
15
Kever Yangaa827752017-11-28 16:04:16 +080016config ROCKCHIP_RK3128
17 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053018 select CPU_V7A
Kever Yangaa827752017-11-28 16:04:16 +080019 help
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
22 and video codec support. Peripherals include Gigabit Ethernet,
23 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
24
Heiko Stübneref6db5e2017-02-18 19:46:36 +010025config ROCKCHIP_RK3188
26 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053027 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080028 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010029 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010030 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020031 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020032 select SPL_REGMAP
33 select SPL_SYSCON
34 select SPL_RAM
35 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich16c689c2017-10-10 16:21:15 +020036 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020037 select BOARD_LATE_INIT
Heiko Stübneref6db5e2017-02-18 19:46:36 +010038 select ROCKCHIP_BROM_HELPER
39 help
40 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
41 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
42 video interfaces, several memory options and video codec support.
43 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
44 UART, SPI, I2C and PWMs.
45
Kever Yang57d4dbf2017-06-23 17:17:52 +080046config ROCKCHIP_RK322X
47 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053048 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080049 select SUPPORT_SPL
Kever Yangaff40c62019-04-02 20:41:24 +080050 select SUPPORT_TPL
Kever Yang57d4dbf2017-06-23 17:17:52 +080051 select SPL
Kever Yangaff40c62019-04-02 20:41:24 +080052 select SPL_DM
53 select SPL_OF_LIBFDT
54 select TPL
55 select TPL_DM
56 select TPL_OF_LIBFDT
57 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
58 select TPL_NEEDS_SEPARATE_STACK if TPL
59 select SPL_DRIVERS_MISC_SUPPORT
60 imply SPL_SERIAL_SUPPORT
61 imply TPL_SERIAL_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +080062 select ROCKCHIP_BROM_HELPER
Kever Yangaff40c62019-04-02 20:41:24 +080063 select TPL_LIBCOMMON_SUPPORT
64 select TPL_LIBGENERIC_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +080065 help
66 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
67 including NEON and GPU, Mali-400 graphics, several DDR3 options
68 and video codec support. Peripherals include Gigabit Ethernet,
69 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
70
Kever Yangaff40c62019-04-02 20:41:24 +080071if ROCKCHIP_RK322X
72
73config TPL_TEXT_BASE
74 default 0x10081000
75
76config TPL_MAX_SIZE
77 default 28672
78
79config TPL_STACK
80 default 0x10088000
81
82endif
83
Simon Glass2cffe662015-08-30 16:55:38 -060084config ROCKCHIP_RK3288
85 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053086 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080087 select SPL_BOARD_INIT if SPL
Kever Yang0d3d7832016-07-19 21:16:59 +080088 select SUPPORT_SPL
89 select SPL
Eddie Caib3501fe2017-12-15 08:17:13 +080090 imply USB_FUNCTION_ROCKUSB
91 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -060092 help
93 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
94 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
95 video interfaces supporting HDMI and eDP, several DDR3 options
96 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +010097 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -060098
Jagan Tekie5df8342018-02-23 13:13:10 +053099if ROCKCHIP_RK3288
100
Jagan Teki843ac352018-02-23 13:13:11 +0530101config TPL_TEXT_BASE
102 default 0xff704000
103
Tom Rinie34a2f32019-01-22 17:09:25 -0500104config TPL_MAX_SIZE
105 default 32768
106
Jagan Tekie5df8342018-02-23 13:13:10 +0530107endif
108
Kever Yangec02b3c2017-02-23 15:37:51 +0800109config ROCKCHIP_RK3328
110 bool "Support Rockchip RK3328"
111 select ARM64
112 help
113 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
114 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
115 video interfaces supporting HDMI and eDP, several DDR3 options
116 and video codec support. Peripherals include Gigabit Ethernet,
117 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
118
Andreas Färber9e3ad682017-05-15 17:51:18 +0800119config ROCKCHIP_RK3368
120 bool "Support Rockchip RK3368"
121 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200122 select SUPPORT_SPL
123 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200124 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
125 select TPL_NEEDS_SEPARATE_STACK if TPL
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200126 imply SPL_SEPARATE_BSS
127 imply SPL_SERIAL_SUPPORT
128 imply TPL_SERIAL_SUPPORT
Andreas Färber9e3ad682017-05-15 17:51:18 +0800129 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200130 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
131 into a big and little cluster with 4 cores each) Cortex-A53 including
132 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
133 (for the little cluster), PowerVR G6110 based graphics, one video
134 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
135 video codec support.
136
137 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
138 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800139
Philipp Tomsichcbacb402017-08-02 21:26:18 +0200140if ROCKCHIP_RK3368
141
Philipp Tomsich7d1319b2017-07-28 20:20:41 +0200142config TPL_TEXT_BASE
143 default 0xff8c1000
144
145config TPL_MAX_SIZE
146 default 28672
147
148config TPL_STACK
149 default 0xff8cffff
150
Philipp Tomsichcbacb402017-08-02 21:26:18 +0200151endif
152
Kever Yang0d3d7832016-07-19 21:16:59 +0800153config ROCKCHIP_RK3399
154 bool "Support Rockchip RK3399"
155 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800156 select SUPPORT_SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800157 select SUPPORT_TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800158 select SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530159 select SPL_ATF
160 select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
161 select SPL_LOAD_FIT
162 select SPL_CLK if SPL
163 select SPL_PINCTRL if SPL
164 select SPL_RAM if SPL
165 select SPL_REGMAP if SPL
166 select SPL_SYSCON if SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800167 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
168 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800169 select SPL_SEPARATE_BSS
Philipp Tomsichd17d8cf2017-07-26 12:29:01 +0200170 select SPL_SERIAL_SUPPORT
171 select SPL_DRIVERS_MISC_SUPPORT
Jagan Tekicd433892019-05-08 11:11:43 +0530172 select CLK
173 select FIT
174 select PINCTRL
175 select RAM
176 select REGMAP
177 select SYSCON
178 select DM_PMIC
179 select DM_REGULATOR_FIXED
Andy Yan70378cb2017-10-11 15:00:16 +0800180 select BOARD_LATE_INIT
Andy Yand2349d92017-10-11 15:00:49 +0800181 select ROCKCHIP_BROM_HELPER
Kever Yangfca798d2018-11-09 11:18:15 +0800182 imply TPL_SERIAL_SUPPORT
183 imply TPL_LIBCOMMON_SUPPORT
184 imply TPL_LIBGENERIC_SUPPORT
185 imply TPL_SYS_MALLOC_SIMPLE
186 imply TPL_BOOTROM_SUPPORT
187 imply TPL_DRIVERS_MISC_SUPPORT
188 imply TPL_OF_CONTROL
189 imply TPL_DM
190 imply TPL_REGMAP
191 imply TPL_SYSCON
192 imply TPL_RAM
193 imply TPL_CLK
194 imply TPL_TINY_MEMSET
Kever Yang0d3d7832016-07-19 21:16:59 +0800195 help
196 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
197 and quad-core Cortex-A53.
198 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
199 video interfaces supporting HDMI and eDP, several DDR3 options
200 and video codec support. Peripherals include Gigabit Ethernet,
201 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
202
Kever Yangfca798d2018-11-09 11:18:15 +0800203if ROCKCHIP_RK3399
204
205config TPL_LDSCRIPT
206 default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
207
208config TPL_TEXT_BASE
209 default 0xff8c2000
210
211config TPL_MAX_SIZE
212 default 188416
213
214config TPL_STACK
215 default 0xff8effff
216
217endif
218
Andy Yan2d982da2017-06-01 18:00:55 +0800219config ROCKCHIP_RV1108
220 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530221 select CPU_V7A
Andy Yan2d982da2017-06-01 18:00:55 +0800222 help
223 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
224 and a DSP.
225
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200226config ROCKCHIP_USB_UART
227 bool "Route uart output to usb pins"
228 help
229 Rockchip SoCs have the ability to route the signals of the debug
230 uart through the d+ and d- pins of a specific usb phy to enable
231 some form of closed-case debugging. With this option supported
232 SoCs will enable this routing as a debug measure.
233
Philipp Tomsich798370f2017-06-29 11:21:15 +0200234config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800235 bool "SPL returns to bootrom"
236 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100237 select ROCKCHIP_BROM_HELPER
Philipp Tomsich798370f2017-06-29 11:21:15 +0200238 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800239 help
240 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
241 SPL will return to the boot rom, which will then load the U-Boot
242 binary to keep going on.
243
Philipp Tomsich798370f2017-06-29 11:21:15 +0200244config TPL_ROCKCHIP_BACK_TO_BROM
245 bool "TPL returns to bootrom"
Kever Yangfca798d2018-11-09 11:18:15 +0800246 default y
Philipp Tomsich798370f2017-06-29 11:21:15 +0200247 select ROCKCHIP_BROM_HELPER
248 depends on TPL
249 help
250 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
251 SPL will return to the boot rom, which will then load the U-Boot
252 binary to keep going on.
253
Andy Yan70378cb2017-10-11 15:00:16 +0800254config ROCKCHIP_BOOT_MODE_REG
255 hex "Rockchip boot mode flag register address"
256 default 0x200081c8 if ROCKCHIP_RK3036
257 default 0x20004040 if ROCKCHIP_RK3188
258 default 0x110005c8 if ROCKCHIP_RK322X
259 default 0xff730094 if ROCKCHIP_RK3288
260 default 0xff738200 if ROCKCHIP_RK3368
261 default 0xff320300 if ROCKCHIP_RK3399
262 default 0x10300580 if ROCKCHIP_RV1108
263 default 0
264 help
Kever Yang9fbe17c2019-03-28 11:01:23 +0800265 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yan70378cb2017-10-11 15:00:16 +0800266 according to the value from this register.
267
Kever Yange484f772017-04-20 17:03:46 +0800268config ROCKCHIP_SPL_RESERVE_IRAM
269 hex "Size of IRAM reserved in SPL"
Kever Yang60a50072017-12-18 15:13:19 +0800270 default 0
Kever Yange484f772017-04-20 17:03:46 +0800271 help
272 SPL may need reserve memory for firmware loaded by SPL, whose load
273 address is in IRAM and may overlay with SPL text area if not
274 reserved.
275
Heiko Stübner355a8802017-02-18 19:46:25 +0100276config ROCKCHIP_BROM_HELPER
277 bool
278
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200279config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
280 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
281 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
282 help
283 Some Rockchip BROM variants (e.g. on the RK3188) load the
284 first stage in segments and enter multiple times. E.g. on
285 the RK3188, the first 1KB of the first stage are loaded
286 first and entered; after returning to the BROM, the
287 remainder of the first stage is loaded, but the BROM
288 re-enters at the same address/to the same code as previously.
289
290 This enables support code in the BOOT0 hook for the SPL stage
291 to allow multiple entries.
292
293config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
294 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
295 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
296 help
297 Some Rockchip BROM variants (e.g. on the RK3188) load the
298 first stage in segments and enter multiple times. E.g. on
299 the RK3188, the first 1KB of the first stage are loaded
300 first and entered; after returning to the BROM, the
301 remainder of the first stage is loaded, but the BROM
302 re-enters at the same address/to the same code as previously.
303
304 This enables support code in the BOOT0 hook for the TPL stage
305 to allow multiple entries.
306
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400307config SPL_MMC_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200308 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400309
huang lin1115b642015-11-17 14:20:27 +0800310source "arch/arm/mach-rockchip/rk3036/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800311source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100312source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800313source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200314source "arch/arm/mach-rockchip/rk3288/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800315source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800316source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800317source "arch/arm/mach-rockchip/rk3399/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800318source "arch/arm/mach-rockchip/rv1108/Kconfig"
Simon Glass2cffe662015-08-30 16:55:38 -0600319endif