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Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stübner5c91e2b2016-07-16 00:17:15 +02003config ROCKCHIP_RK3036
4 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +05305 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +08006 select SUPPORT_SPL
7 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +08008 imply USB_FUNCTION_ROCKUSB
9 imply CMD_ROCKUSB
Kever Yang427cb672019-07-22 20:02:04 +080010 imply ROCKCHIP_COMMON_BOARD
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020011 help
12 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
13 including NEON and GPU, Mali-400 graphics, several DDR3 options
14 and video codec support. Peripherals include Gigabit Ethernet,
15 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
16
Kever Yangaa827752017-11-28 16:04:16 +080017config ROCKCHIP_RK3128
18 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053019 select CPU_V7A
Kever Yangaa827752017-11-28 16:04:16 +080020 help
21 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
22 including NEON and GPU, Mali-400 graphics, several DDR3 options
23 and video codec support. Peripherals include Gigabit Ethernet,
24 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
25
Heiko Stübneref6db5e2017-02-18 19:46:36 +010026config ROCKCHIP_RK3188
27 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053028 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080029 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010030 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010031 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020032 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020033 select SPL_REGMAP
34 select SPL_SYSCON
35 select SPL_RAM
36 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich16c689c2017-10-10 16:21:15 +020037 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangbd8532e2019-07-22 19:59:15 +080038 select SPL_ROCKCHIP_BACK_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020039 select BOARD_LATE_INIT
Kever Yang3bd90402019-07-22 19:59:18 +080040 imply SPL_ROCKCHIP_COMMON_BOARD
Heiko Stübneref6db5e2017-02-18 19:46:36 +010041 help
42 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
43 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
44 video interfaces, several memory options and video codec support.
45 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
46 UART, SPI, I2C and PWMs.
47
Kever Yang57d4dbf2017-06-23 17:17:52 +080048config ROCKCHIP_RK322X
49 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053050 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080051 select SUPPORT_SPL
Kever Yangaff40c62019-04-02 20:41:24 +080052 select SUPPORT_TPL
Kever Yang57d4dbf2017-06-23 17:17:52 +080053 select SPL
Kever Yangaff40c62019-04-02 20:41:24 +080054 select SPL_DM
55 select SPL_OF_LIBFDT
56 select TPL
57 select TPL_DM
58 select TPL_OF_LIBFDT
59 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
60 select TPL_NEEDS_SEPARATE_STACK if TPL
61 select SPL_DRIVERS_MISC_SUPPORT
62 imply SPL_SERIAL_SUPPORT
Kever Yangd877fd22019-07-22 19:59:20 +080063 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +080064 imply TPL_SERIAL_SUPPORT
Kever Yang466f3fd2019-07-09 22:05:56 +080065 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +080066 select TPL_LIBCOMMON_SUPPORT
67 select TPL_LIBGENERIC_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +080068 help
69 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
70 including NEON and GPU, Mali-400 graphics, several DDR3 options
71 and video codec support. Peripherals include Gigabit Ethernet,
72 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
73
Simon Glass2cffe662015-08-30 16:55:38 -060074config ROCKCHIP_RK3288
75 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053076 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +080077 select SUPPORT_SPL
78 select SPL
Kever Yangf7c0a332019-07-02 11:43:05 +080079 select SUPPORT_TPL
Kever Yangaa67deb2019-07-22 19:59:27 +080080 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +080081 imply TPL_CLK
82 imply TPL_DM
83 imply TPL_DRIVERS_MISC_SUPPORT
84 imply TPL_LIBCOMMON_SUPPORT
85 imply TPL_LIBGENERIC_SUPPORT
86 imply TPL_NEEDS_SEPARATE_TEXT_BASE
Kever Yangb36e7092019-07-02 11:43:06 +080087 imply TPL_NEEDS_SEPARATE_STACK
Kever Yangf7c0a332019-07-02 11:43:05 +080088 imply TPL_OF_CONTROL
89 imply TPL_OF_PLATDATA
90 imply TPL_RAM
91 imply TPL_REGMAP
Kever Yange32f38e2019-07-09 22:05:57 +080092 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +080093 imply TPL_SERIAL_SUPPORT
94 imply TPL_SYSCON
Eddie Caib3501fe2017-12-15 08:17:13 +080095 imply USB_FUNCTION_ROCKUSB
96 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -060097 help
98 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
99 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
100 video interfaces supporting HDMI and eDP, several DDR3 options
101 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +0100102 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -0600103
Kever Yangec02b3c2017-02-23 15:37:51 +0800104config ROCKCHIP_RK3328
105 bool "Support Rockchip RK3328"
106 select ARM64
Kever Yang07be6692019-06-09 00:27:15 +0300107 select SUPPORT_SPL
108 select SPL
Kever Yangbb4c3252019-07-22 19:59:32 +0800109 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yang07be6692019-06-09 00:27:15 +0300110 imply SPL_SERIAL_SUPPORT
111 imply SPL_SEPARATE_BSS
112 select ENABLE_ARM_SOC_BOOT0_HOOK
113 select DEBUG_UART_BOARD_INIT
114 select SYS_NS16550
Kever Yangec02b3c2017-02-23 15:37:51 +0800115 help
116 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
117 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
118 video interfaces supporting HDMI and eDP, several DDR3 options
119 and video codec support. Peripherals include Gigabit Ethernet,
120 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
121
Andreas Färber9e3ad682017-05-15 17:51:18 +0800122config ROCKCHIP_RK3368
123 bool "Support Rockchip RK3368"
124 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200125 select SUPPORT_SPL
126 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200127 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
128 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang8bf7ed42019-07-22 19:59:34 +0800129 imply SPL_ROCKCHIP_COMMON_BOARD
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200130 imply SPL_SEPARATE_BSS
131 imply SPL_SERIAL_SUPPORT
132 imply TPL_SERIAL_SUPPORT
Kever Yang48831b22019-07-09 22:05:58 +0800133 imply TPL_ROCKCHIP_COMMON_BOARD
Andreas Färber9e3ad682017-05-15 17:51:18 +0800134 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200135 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
136 into a big and little cluster with 4 cores each) Cortex-A53 including
137 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
138 (for the little cluster), PowerVR G6110 based graphics, one video
139 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
140 video codec support.
141
142 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
143 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800144
Kever Yang0d3d7832016-07-19 21:16:59 +0800145config ROCKCHIP_RK3399
146 bool "Support Rockchip RK3399"
147 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800148 select SUPPORT_SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800149 select SUPPORT_TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800150 select SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530151 select SPL_ATF
152 select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Jagan Tekice063b92019-06-21 00:25:03 +0530153 select SPL_BOARD_INIT if SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530154 select SPL_LOAD_FIT
155 select SPL_CLK if SPL
156 select SPL_PINCTRL if SPL
157 select SPL_RAM if SPL
158 select SPL_REGMAP if SPL
159 select SPL_SYSCON if SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800160 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
161 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800162 select SPL_SEPARATE_BSS
Philipp Tomsichd17d8cf2017-07-26 12:29:01 +0200163 select SPL_SERIAL_SUPPORT
164 select SPL_DRIVERS_MISC_SUPPORT
Jagan Tekicd433892019-05-08 11:11:43 +0530165 select CLK
166 select FIT
167 select PINCTRL
168 select RAM
169 select REGMAP
170 select SYSCON
171 select DM_PMIC
172 select DM_REGULATOR_FIXED
Andy Yan70378cb2017-10-11 15:00:16 +0800173 select BOARD_LATE_INIT
Kever Yangff9afe42019-07-22 19:59:42 +0800174 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangfca798d2018-11-09 11:18:15 +0800175 imply TPL_SERIAL_SUPPORT
176 imply TPL_LIBCOMMON_SUPPORT
177 imply TPL_LIBGENERIC_SUPPORT
178 imply TPL_SYS_MALLOC_SIMPLE
Kever Yangfca798d2018-11-09 11:18:15 +0800179 imply TPL_DRIVERS_MISC_SUPPORT
180 imply TPL_OF_CONTROL
181 imply TPL_DM
182 imply TPL_REGMAP
183 imply TPL_SYSCON
184 imply TPL_RAM
185 imply TPL_CLK
186 imply TPL_TINY_MEMSET
Kever Yang3cfbb942019-07-09 22:06:01 +0800187 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yang0d3d7832016-07-19 21:16:59 +0800188 help
189 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
190 and quad-core Cortex-A53.
191 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
192 video interfaces supporting HDMI and eDP, several DDR3 options
193 and video codec support. Peripherals include Gigabit Ethernet,
194 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
195
Andy Yan2d982da2017-06-01 18:00:55 +0800196config ROCKCHIP_RV1108
197 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530198 select CPU_V7A
Andy Yan2d982da2017-06-01 18:00:55 +0800199 help
200 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
201 and a DSP.
202
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200203config ROCKCHIP_USB_UART
204 bool "Route uart output to usb pins"
205 help
206 Rockchip SoCs have the ability to route the signals of the debug
207 uart through the d+ and d- pins of a specific usb phy to enable
208 some form of closed-case debugging. With this option supported
209 SoCs will enable this routing as a debug measure.
210
Philipp Tomsich798370f2017-06-29 11:21:15 +0200211config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800212 bool "SPL returns to bootrom"
213 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100214 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800215 select SPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200216 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800217 help
218 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
219 SPL will return to the boot rom, which will then load the U-Boot
220 binary to keep going on.
221
Philipp Tomsich798370f2017-06-29 11:21:15 +0200222config TPL_ROCKCHIP_BACK_TO_BROM
223 bool "TPL returns to bootrom"
Kever Yangfca798d2018-11-09 11:18:15 +0800224 default y
Philipp Tomsich798370f2017-06-29 11:21:15 +0200225 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800226 select TPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200227 depends on TPL
228 help
229 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
230 SPL will return to the boot rom, which will then load the U-Boot
231 binary to keep going on.
232
Kever Yangbb337732019-07-22 20:02:01 +0800233config ROCKCHIP_COMMON_BOARD
234 bool "Rockchip common board file"
235 help
236 Rockchip SoCs have similar boot process, Common board file is mainly
237 in charge of common process of board_init() and board_late_init() for
238 U-Boot proper.
239
Kever Yang1d7cc72a2019-07-22 19:59:12 +0800240config SPL_ROCKCHIP_COMMON_BOARD
241 bool "Rockchip SPL common board file"
242 depends on SPL
243 help
244 Rockchip SoCs have similar boot process, SPL is mainly in charge of
245 load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
246 no TPL for the board.
247
Kever Yang34ead0f2019-07-09 22:05:55 +0800248config TPL_ROCKCHIP_COMMON_BOARD
249 bool ""
250 depends on TPL
251 help
252 Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
253 init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
254 common board is a basic TPL board init which can be shared for most
255 of SoCs to avoid copy-pase for different SoCs.
256
Andy Yan70378cb2017-10-11 15:00:16 +0800257config ROCKCHIP_BOOT_MODE_REG
258 hex "Rockchip boot mode flag register address"
Andy Yan70378cb2017-10-11 15:00:16 +0800259 help
Kever Yang9fbe17c2019-03-28 11:01:23 +0800260 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yan70378cb2017-10-11 15:00:16 +0800261 according to the value from this register.
262
Kever Yange484f772017-04-20 17:03:46 +0800263config ROCKCHIP_SPL_RESERVE_IRAM
264 hex "Size of IRAM reserved in SPL"
Kever Yang60a50072017-12-18 15:13:19 +0800265 default 0
Kever Yange484f772017-04-20 17:03:46 +0800266 help
267 SPL may need reserve memory for firmware loaded by SPL, whose load
268 address is in IRAM and may overlay with SPL text area if not
269 reserved.
270
Heiko Stübner355a8802017-02-18 19:46:25 +0100271config ROCKCHIP_BROM_HELPER
272 bool
273
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200274config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
275 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
276 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
277 help
278 Some Rockchip BROM variants (e.g. on the RK3188) load the
279 first stage in segments and enter multiple times. E.g. on
280 the RK3188, the first 1KB of the first stage are loaded
281 first and entered; after returning to the BROM, the
282 remainder of the first stage is loaded, but the BROM
283 re-enters at the same address/to the same code as previously.
284
285 This enables support code in the BOOT0 hook for the SPL stage
286 to allow multiple entries.
287
288config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
289 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
290 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
291 help
292 Some Rockchip BROM variants (e.g. on the RK3188) load the
293 first stage in segments and enter multiple times. E.g. on
294 the RK3188, the first 1KB of the first stage are loaded
295 first and entered; after returning to the BROM, the
296 remainder of the first stage is loaded, but the BROM
297 re-enters at the same address/to the same code as previously.
298
299 This enables support code in the BOOT0 hook for the TPL stage
300 to allow multiple entries.
301
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400302config SPL_MMC_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200303 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400304
huang lin1115b642015-11-17 14:20:27 +0800305source "arch/arm/mach-rockchip/rk3036/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800306source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100307source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800308source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200309source "arch/arm/mach-rockchip/rk3288/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800310source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800311source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800312source "arch/arm/mach-rockchip/rk3399/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800313source "arch/arm/mach-rockchip/rv1108/Kconfig"
Simon Glass2cffe662015-08-30 16:55:38 -0600314endif