Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 1 | if ARCH_ROCKCHIP |
| 2 | |
Heiko Stübner | 5c91e2b | 2016-07-16 00:17:15 +0200 | [diff] [blame] | 3 | config ROCKCHIP_RK3036 |
| 4 | bool "Support Rockchip RK3036" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 5 | select CPU_V7A |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 6 | select SUPPORT_SPL |
| 7 | select SPL |
Eddie Cai | a79b78f | 2018-01-17 09:51:41 +0800 | [diff] [blame] | 8 | imply USB_FUNCTION_ROCKUSB |
| 9 | imply CMD_ROCKUSB |
Heiko Stübner | 5c91e2b | 2016-07-16 00:17:15 +0200 | [diff] [blame] | 10 | help |
| 11 | The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 |
| 12 | including NEON and GPU, Mali-400 graphics, several DDR3 options |
| 13 | and video codec support. Peripherals include Gigabit Ethernet, |
| 14 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. |
| 15 | |
Kever Yang | aa82775 | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 16 | config ROCKCHIP_RK3128 |
| 17 | bool "Support Rockchip RK3128" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 18 | select CPU_V7A |
Kever Yang | aa82775 | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 19 | help |
| 20 | The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 |
| 21 | including NEON and GPU, Mali-400 graphics, several DDR3 options |
| 22 | and video codec support. Peripherals include Gigabit Ethernet, |
| 23 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. |
| 24 | |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 25 | config ROCKCHIP_RK3188 |
| 26 | bool "Support Rockchip RK3188" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 27 | select CPU_V7A |
Ley Foon Tan | 48fcc4a | 2017-05-03 17:13:32 +0800 | [diff] [blame] | 28 | select SPL_BOARD_INIT if SPL |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 29 | select SUPPORT_SPL |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 30 | select SPL |
Philipp Tomsich | 5aa3f9d | 2017-10-10 16:21:17 +0200 | [diff] [blame] | 31 | select SPL_CLK |
Philipp Tomsich | 5aa3f9d | 2017-10-10 16:21:17 +0200 | [diff] [blame] | 32 | select SPL_REGMAP |
| 33 | select SPL_SYSCON |
| 34 | select SPL_RAM |
| 35 | select SPL_DRIVERS_MISC_SUPPORT |
Philipp Tomsich | 16c689c | 2017-10-10 16:21:15 +0200 | [diff] [blame] | 36 | select SPL_ROCKCHIP_EARLYRETURN_TO_BROM |
Kever Yang | bd8532e | 2019-07-22 19:59:15 +0800 | [diff] [blame] | 37 | select SPL_ROCKCHIP_BACK_TO_BROM |
Heiko Stübner | 015f69a | 2017-04-06 00:19:36 +0200 | [diff] [blame] | 38 | select BOARD_LATE_INIT |
Kever Yang | 3bd9040 | 2019-07-22 19:59:18 +0800 | [diff] [blame] | 39 | imply SPL_ROCKCHIP_COMMON_BOARD |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 40 | help |
| 41 | The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9 |
| 42 | including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two |
| 43 | video interfaces, several memory options and video codec support. |
| 44 | Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, |
| 45 | UART, SPI, I2C and PWMs. |
| 46 | |
Kever Yang | 57d4dbf | 2017-06-23 17:17:52 +0800 | [diff] [blame] | 47 | config ROCKCHIP_RK322X |
| 48 | bool "Support Rockchip RK3228/RK3229" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 49 | select CPU_V7A |
Kever Yang | 57d4dbf | 2017-06-23 17:17:52 +0800 | [diff] [blame] | 50 | select SUPPORT_SPL |
Kever Yang | aff40c6 | 2019-04-02 20:41:24 +0800 | [diff] [blame] | 51 | select SUPPORT_TPL |
Kever Yang | 57d4dbf | 2017-06-23 17:17:52 +0800 | [diff] [blame] | 52 | select SPL |
Kever Yang | aff40c6 | 2019-04-02 20:41:24 +0800 | [diff] [blame] | 53 | select SPL_DM |
| 54 | select SPL_OF_LIBFDT |
| 55 | select TPL |
| 56 | select TPL_DM |
| 57 | select TPL_OF_LIBFDT |
| 58 | select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL |
| 59 | select TPL_NEEDS_SEPARATE_STACK if TPL |
| 60 | select SPL_DRIVERS_MISC_SUPPORT |
| 61 | imply SPL_SERIAL_SUPPORT |
Kever Yang | d877fd2 | 2019-07-22 19:59:20 +0800 | [diff] [blame] | 62 | imply SPL_ROCKCHIP_COMMON_BOARD |
Kever Yang | aff40c6 | 2019-04-02 20:41:24 +0800 | [diff] [blame] | 63 | imply TPL_SERIAL_SUPPORT |
Kever Yang | 466f3fd | 2019-07-09 22:05:56 +0800 | [diff] [blame] | 64 | imply TPL_ROCKCHIP_COMMON_BOARD |
Kever Yang | aff40c6 | 2019-04-02 20:41:24 +0800 | [diff] [blame] | 65 | select TPL_LIBCOMMON_SUPPORT |
| 66 | select TPL_LIBGENERIC_SUPPORT |
Kever Yang | 57d4dbf | 2017-06-23 17:17:52 +0800 | [diff] [blame] | 67 | help |
| 68 | The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7 |
| 69 | including NEON and GPU, Mali-400 graphics, several DDR3 options |
| 70 | and video codec support. Peripherals include Gigabit Ethernet, |
| 71 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. |
| 72 | |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 73 | config ROCKCHIP_RK3288 |
| 74 | bool "Support Rockchip RK3288" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 75 | select CPU_V7A |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 76 | select SUPPORT_SPL |
| 77 | select SPL |
Kever Yang | f7c0a33 | 2019-07-02 11:43:05 +0800 | [diff] [blame] | 78 | select SUPPORT_TPL |
Kever Yang | aa67deb | 2019-07-22 19:59:27 +0800 | [diff] [blame] | 79 | imply SPL_ROCKCHIP_COMMON_BOARD |
Kever Yang | f7c0a33 | 2019-07-02 11:43:05 +0800 | [diff] [blame] | 80 | imply TPL_CLK |
| 81 | imply TPL_DM |
| 82 | imply TPL_DRIVERS_MISC_SUPPORT |
| 83 | imply TPL_LIBCOMMON_SUPPORT |
| 84 | imply TPL_LIBGENERIC_SUPPORT |
| 85 | imply TPL_NEEDS_SEPARATE_TEXT_BASE |
Kever Yang | b36e709 | 2019-07-02 11:43:06 +0800 | [diff] [blame] | 86 | imply TPL_NEEDS_SEPARATE_STACK |
Kever Yang | f7c0a33 | 2019-07-02 11:43:05 +0800 | [diff] [blame] | 87 | imply TPL_OF_CONTROL |
| 88 | imply TPL_OF_PLATDATA |
| 89 | imply TPL_RAM |
| 90 | imply TPL_REGMAP |
Kever Yang | e32f38e | 2019-07-09 22:05:57 +0800 | [diff] [blame] | 91 | imply TPL_ROCKCHIP_COMMON_BOARD |
Kever Yang | f7c0a33 | 2019-07-02 11:43:05 +0800 | [diff] [blame] | 92 | imply TPL_SERIAL_SUPPORT |
| 93 | imply TPL_SYSCON |
Eddie Cai | b3501fe | 2017-12-15 08:17:13 +0800 | [diff] [blame] | 94 | imply USB_FUNCTION_ROCKUSB |
| 95 | imply CMD_ROCKUSB |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 96 | help |
| 97 | The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 |
| 98 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two |
| 99 | video interfaces supporting HDMI and eDP, several DDR3 options |
| 100 | and video codec support. Peripherals include Gigabit Ethernet, |
Andreas Färber | 531e8e0 | 2016-11-02 18:03:01 +0100 | [diff] [blame] | 101 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 102 | |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 103 | config ROCKCHIP_RK3328 |
| 104 | bool "Support Rockchip RK3328" |
| 105 | select ARM64 |
Kever Yang | 07be669 | 2019-06-09 00:27:15 +0300 | [diff] [blame] | 106 | select SUPPORT_SPL |
| 107 | select SPL |
Kever Yang | bb4c325 | 2019-07-22 19:59:32 +0800 | [diff] [blame] | 108 | imply SPL_ROCKCHIP_COMMON_BOARD |
Kever Yang | 07be669 | 2019-06-09 00:27:15 +0300 | [diff] [blame] | 109 | imply SPL_SERIAL_SUPPORT |
| 110 | imply SPL_SEPARATE_BSS |
| 111 | select ENABLE_ARM_SOC_BOOT0_HOOK |
| 112 | select DEBUG_UART_BOARD_INIT |
| 113 | select SYS_NS16550 |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 114 | help |
| 115 | The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. |
| 116 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two |
| 117 | video interfaces supporting HDMI and eDP, several DDR3 options |
| 118 | and video codec support. Peripherals include Gigabit Ethernet, |
| 119 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
| 120 | |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 121 | config ROCKCHIP_RK3368 |
| 122 | bool "Support Rockchip RK3368" |
| 123 | select ARM64 |
Philipp Tomsich | 84af43e | 2017-06-11 23:46:25 +0200 | [diff] [blame] | 124 | select SUPPORT_SPL |
| 125 | select SUPPORT_TPL |
Philipp Tomsich | 01b219e | 2017-07-28 20:03:07 +0200 | [diff] [blame] | 126 | select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL |
| 127 | select TPL_NEEDS_SEPARATE_STACK if TPL |
Kever Yang | 8bf7ed4 | 2019-07-22 19:59:34 +0800 | [diff] [blame] | 128 | imply SPL_ROCKCHIP_COMMON_BOARD |
Philipp Tomsich | 84af43e | 2017-06-11 23:46:25 +0200 | [diff] [blame] | 129 | imply SPL_SEPARATE_BSS |
| 130 | imply SPL_SERIAL_SUPPORT |
| 131 | imply TPL_SERIAL_SUPPORT |
Kever Yang | 48831b2 | 2019-07-09 22:05:58 +0800 | [diff] [blame] | 132 | imply TPL_ROCKCHIP_COMMON_BOARD |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 133 | help |
Philipp Tomsich | 9f3deaf | 2017-06-10 00:47:53 +0200 | [diff] [blame] | 134 | The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised |
| 135 | into a big and little cluster with 4 cores each) Cortex-A53 including |
| 136 | AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache |
| 137 | (for the little cluster), PowerVR G6110 based graphics, one video |
| 138 | output processor supporting LVDS/HDMI/eDP, several DDR3 options and |
| 139 | video codec support. |
| 140 | |
| 141 | On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, |
| 142 | I2S, UARTs, SPI, I2C and PWMs. |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 143 | |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 144 | config ROCKCHIP_RK3399 |
| 145 | bool "Support Rockchip RK3399" |
| 146 | select ARM64 |
Kever Yang | 16efdfd | 2017-02-22 16:56:38 +0800 | [diff] [blame] | 147 | select SUPPORT_SPL |
Kever Yang | fca798d | 2018-11-09 11:18:15 +0800 | [diff] [blame] | 148 | select SUPPORT_TPL |
Kever Yang | 16efdfd | 2017-02-22 16:56:38 +0800 | [diff] [blame] | 149 | select SPL |
Jagan Teki | cd43389 | 2019-05-08 11:11:43 +0530 | [diff] [blame] | 150 | select SPL_ATF |
| 151 | select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF |
Jagan Teki | ce063b9 | 2019-06-21 00:25:03 +0530 | [diff] [blame] | 152 | select SPL_BOARD_INIT if SPL |
Jagan Teki | cd43389 | 2019-05-08 11:11:43 +0530 | [diff] [blame] | 153 | select SPL_LOAD_FIT |
| 154 | select SPL_CLK if SPL |
| 155 | select SPL_PINCTRL if SPL |
| 156 | select SPL_RAM if SPL |
| 157 | select SPL_REGMAP if SPL |
| 158 | select SPL_SYSCON if SPL |
Kever Yang | fca798d | 2018-11-09 11:18:15 +0800 | [diff] [blame] | 159 | select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL |
| 160 | select TPL_NEEDS_SEPARATE_STACK if TPL |
Kever Yang | 16efdfd | 2017-02-22 16:56:38 +0800 | [diff] [blame] | 161 | select SPL_SEPARATE_BSS |
Philipp Tomsich | d17d8cf | 2017-07-26 12:29:01 +0200 | [diff] [blame] | 162 | select SPL_SERIAL_SUPPORT |
| 163 | select SPL_DRIVERS_MISC_SUPPORT |
Jagan Teki | cd43389 | 2019-05-08 11:11:43 +0530 | [diff] [blame] | 164 | select CLK |
| 165 | select FIT |
| 166 | select PINCTRL |
| 167 | select RAM |
| 168 | select REGMAP |
| 169 | select SYSCON |
| 170 | select DM_PMIC |
| 171 | select DM_REGULATOR_FIXED |
Andy Yan | 70378cb | 2017-10-11 15:00:16 +0800 | [diff] [blame] | 172 | select BOARD_LATE_INIT |
Kever Yang | ff9afe4 | 2019-07-22 19:59:42 +0800 | [diff] [blame^] | 173 | imply SPL_ROCKCHIP_COMMON_BOARD |
Kever Yang | fca798d | 2018-11-09 11:18:15 +0800 | [diff] [blame] | 174 | imply TPL_SERIAL_SUPPORT |
| 175 | imply TPL_LIBCOMMON_SUPPORT |
| 176 | imply TPL_LIBGENERIC_SUPPORT |
| 177 | imply TPL_SYS_MALLOC_SIMPLE |
Kever Yang | fca798d | 2018-11-09 11:18:15 +0800 | [diff] [blame] | 178 | imply TPL_DRIVERS_MISC_SUPPORT |
| 179 | imply TPL_OF_CONTROL |
| 180 | imply TPL_DM |
| 181 | imply TPL_REGMAP |
| 182 | imply TPL_SYSCON |
| 183 | imply TPL_RAM |
| 184 | imply TPL_CLK |
| 185 | imply TPL_TINY_MEMSET |
Kever Yang | 3cfbb94 | 2019-07-09 22:06:01 +0800 | [diff] [blame] | 186 | imply TPL_ROCKCHIP_COMMON_BOARD |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 187 | help |
| 188 | The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 |
| 189 | and quad-core Cortex-A53. |
| 190 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two |
| 191 | video interfaces supporting HDMI and eDP, several DDR3 options |
| 192 | and video codec support. Peripherals include Gigabit Ethernet, |
| 193 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
| 194 | |
Andy Yan | 2d982da | 2017-06-01 18:00:55 +0800 | [diff] [blame] | 195 | config ROCKCHIP_RV1108 |
| 196 | bool "Support Rockchip RV1108" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 197 | select CPU_V7A |
Andy Yan | 2d982da | 2017-06-01 18:00:55 +0800 | [diff] [blame] | 198 | help |
| 199 | The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 |
| 200 | and a DSP. |
| 201 | |
Heiko Stuebner | 9cc8feb | 2018-10-08 13:01:56 +0200 | [diff] [blame] | 202 | config ROCKCHIP_USB_UART |
| 203 | bool "Route uart output to usb pins" |
| 204 | help |
| 205 | Rockchip SoCs have the ability to route the signals of the debug |
| 206 | uart through the d+ and d- pins of a specific usb phy to enable |
| 207 | some form of closed-case debugging. With this option supported |
| 208 | SoCs will enable this routing as a debug measure. |
| 209 | |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 210 | config SPL_ROCKCHIP_BACK_TO_BROM |
Xu Ziyuan | 5401eb8 | 2016-07-12 19:09:49 +0800 | [diff] [blame] | 211 | bool "SPL returns to bootrom" |
| 212 | default y if ROCKCHIP_RK3036 |
Heiko Stübner | 355a880 | 2017-02-18 19:46:25 +0100 | [diff] [blame] | 213 | select ROCKCHIP_BROM_HELPER |
Kever Yang | bd8532e | 2019-07-22 19:59:15 +0800 | [diff] [blame] | 214 | select SPL_BOOTROM_SUPPORT |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 215 | depends on SPL |
Xu Ziyuan | 5401eb8 | 2016-07-12 19:09:49 +0800 | [diff] [blame] | 216 | help |
| 217 | Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, |
| 218 | SPL will return to the boot rom, which will then load the U-Boot |
| 219 | binary to keep going on. |
| 220 | |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 221 | config TPL_ROCKCHIP_BACK_TO_BROM |
| 222 | bool "TPL returns to bootrom" |
Kever Yang | fca798d | 2018-11-09 11:18:15 +0800 | [diff] [blame] | 223 | default y |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 224 | select ROCKCHIP_BROM_HELPER |
Kever Yang | bd8532e | 2019-07-22 19:59:15 +0800 | [diff] [blame] | 225 | select TPL_BOOTROM_SUPPORT |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 226 | depends on TPL |
| 227 | help |
| 228 | Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, |
| 229 | SPL will return to the boot rom, which will then load the U-Boot |
| 230 | binary to keep going on. |
| 231 | |
Kever Yang | 1d7cc72a | 2019-07-22 19:59:12 +0800 | [diff] [blame] | 232 | config SPL_ROCKCHIP_COMMON_BOARD |
| 233 | bool "Rockchip SPL common board file" |
| 234 | depends on SPL |
| 235 | help |
| 236 | Rockchip SoCs have similar boot process, SPL is mainly in charge of |
| 237 | load and boot Trust ATF/U-Boot firmware, and DRAM init if there is |
| 238 | no TPL for the board. |
| 239 | |
Kever Yang | 34ead0f | 2019-07-09 22:05:55 +0800 | [diff] [blame] | 240 | config TPL_ROCKCHIP_COMMON_BOARD |
| 241 | bool "" |
| 242 | depends on TPL |
| 243 | help |
| 244 | Rockchip SoCs have similar boot process, prefer to use TPL for DRAM |
| 245 | init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL |
| 246 | common board is a basic TPL board init which can be shared for most |
| 247 | of SoCs to avoid copy-pase for different SoCs. |
| 248 | |
Andy Yan | 70378cb | 2017-10-11 15:00:16 +0800 | [diff] [blame] | 249 | config ROCKCHIP_BOOT_MODE_REG |
| 250 | hex "Rockchip boot mode flag register address" |
Andy Yan | 70378cb | 2017-10-11 15:00:16 +0800 | [diff] [blame] | 251 | help |
Kever Yang | 9fbe17c | 2019-03-28 11:01:23 +0800 | [diff] [blame] | 252 | The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h) |
Andy Yan | 70378cb | 2017-10-11 15:00:16 +0800 | [diff] [blame] | 253 | according to the value from this register. |
| 254 | |
Kever Yang | e484f77 | 2017-04-20 17:03:46 +0800 | [diff] [blame] | 255 | config ROCKCHIP_SPL_RESERVE_IRAM |
| 256 | hex "Size of IRAM reserved in SPL" |
Kever Yang | 60a5007 | 2017-12-18 15:13:19 +0800 | [diff] [blame] | 257 | default 0 |
Kever Yang | e484f77 | 2017-04-20 17:03:46 +0800 | [diff] [blame] | 258 | help |
| 259 | SPL may need reserve memory for firmware loaded by SPL, whose load |
| 260 | address is in IRAM and may overlay with SPL text area if not |
| 261 | reserved. |
| 262 | |
Heiko Stübner | 355a880 | 2017-02-18 19:46:25 +0100 | [diff] [blame] | 263 | config ROCKCHIP_BROM_HELPER |
| 264 | bool |
| 265 | |
Philipp Tomsich | 9f1a447 | 2017-10-10 16:21:10 +0200 | [diff] [blame] | 266 | config SPL_ROCKCHIP_EARLYRETURN_TO_BROM |
| 267 | bool "SPL requires early-return (for RK3188-style BROM) to BROM" |
| 268 | depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK |
| 269 | help |
| 270 | Some Rockchip BROM variants (e.g. on the RK3188) load the |
| 271 | first stage in segments and enter multiple times. E.g. on |
| 272 | the RK3188, the first 1KB of the first stage are loaded |
| 273 | first and entered; after returning to the BROM, the |
| 274 | remainder of the first stage is loaded, but the BROM |
| 275 | re-enters at the same address/to the same code as previously. |
| 276 | |
| 277 | This enables support code in the BOOT0 hook for the SPL stage |
| 278 | to allow multiple entries. |
| 279 | |
| 280 | config TPL_ROCKCHIP_EARLYRETURN_TO_BROM |
| 281 | bool "TPL requires early-return (for RK3188-style BROM) to BROM" |
| 282 | depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK |
| 283 | help |
| 284 | Some Rockchip BROM variants (e.g. on the RK3188) load the |
| 285 | first stage in segments and enter multiple times. E.g. on |
| 286 | the RK3188, the first 1KB of the first stage are loaded |
| 287 | first and entered; after returning to the BROM, the |
| 288 | remainder of the first stage is loaded, but the BROM |
| 289 | re-enters at the same address/to the same code as previously. |
| 290 | |
| 291 | This enables support code in the BOOT0 hook for the TPL stage |
| 292 | to allow multiple entries. |
| 293 | |
Sandy Patterson | d70f0f3 | 2016-08-29 07:31:16 -0400 | [diff] [blame] | 294 | config SPL_MMC_SUPPORT |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 295 | default y if !SPL_ROCKCHIP_BACK_TO_BROM |
Sandy Patterson | d70f0f3 | 2016-08-29 07:31:16 -0400 | [diff] [blame] | 296 | |
huang lin | 1115b64 | 2015-11-17 14:20:27 +0800 | [diff] [blame] | 297 | source "arch/arm/mach-rockchip/rk3036/Kconfig" |
Kever Yang | aa82775 | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 298 | source "arch/arm/mach-rockchip/rk3128/Kconfig" |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 299 | source "arch/arm/mach-rockchip/rk3188/Kconfig" |
Kever Yang | a4f460d | 2017-06-23 17:17:54 +0800 | [diff] [blame] | 300 | source "arch/arm/mach-rockchip/rk322x/Kconfig" |
Heiko Stübner | 5c91e2b | 2016-07-16 00:17:15 +0200 | [diff] [blame] | 301 | source "arch/arm/mach-rockchip/rk3288/Kconfig" |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 302 | source "arch/arm/mach-rockchip/rk3328/Kconfig" |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 303 | source "arch/arm/mach-rockchip/rk3368/Kconfig" |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 304 | source "arch/arm/mach-rockchip/rk3399/Kconfig" |
Andy Yan | 2d982da | 2017-06-01 18:00:55 +0800 | [diff] [blame] | 305 | source "arch/arm/mach-rockchip/rv1108/Kconfig" |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 306 | endif |