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Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stübner5c91e2b2016-07-16 00:17:15 +02003config ROCKCHIP_RK3036
4 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +05305 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +08006 select SUPPORT_SPL
7 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +08008 imply USB_FUNCTION_ROCKUSB
9 imply CMD_ROCKUSB
Kever Yang427cb672019-07-22 20:02:04 +080010 imply ROCKCHIP_COMMON_BOARD
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020011 help
12 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
13 including NEON and GPU, Mali-400 graphics, several DDR3 options
14 and video codec support. Peripherals include Gigabit Ethernet,
15 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
16
Kever Yangaa827752017-11-28 16:04:16 +080017config ROCKCHIP_RK3128
18 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053019 select CPU_V7A
Kever Yang96362722019-07-22 20:02:05 +080020 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa827752017-11-28 16:04:16 +080021 help
22 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
23 including NEON and GPU, Mali-400 graphics, several DDR3 options
24 and video codec support. Peripherals include Gigabit Ethernet,
25 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
26
Heiko Stübneref6db5e2017-02-18 19:46:36 +010027config ROCKCHIP_RK3188
28 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053029 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080030 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010031 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010032 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020033 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020034 select SPL_REGMAP
35 select SPL_SYSCON
36 select SPL_RAM
37 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich16c689c2017-10-10 16:21:15 +020038 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangbd8532e2019-07-22 19:59:15 +080039 select SPL_ROCKCHIP_BACK_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020040 select BOARD_LATE_INIT
Kever Yang3bd90402019-07-22 19:59:18 +080041 imply SPL_ROCKCHIP_COMMON_BOARD
Heiko Stübneref6db5e2017-02-18 19:46:36 +010042 help
43 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
44 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
45 video interfaces, several memory options and video codec support.
46 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
47 UART, SPI, I2C and PWMs.
48
Kever Yang57d4dbf2017-06-23 17:17:52 +080049config ROCKCHIP_RK322X
50 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053051 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080052 select SUPPORT_SPL
Kever Yangaff40c62019-04-02 20:41:24 +080053 select SUPPORT_TPL
Kever Yang57d4dbf2017-06-23 17:17:52 +080054 select SPL
Kever Yangaff40c62019-04-02 20:41:24 +080055 select SPL_DM
56 select SPL_OF_LIBFDT
57 select TPL
58 select TPL_DM
59 select TPL_OF_LIBFDT
60 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
61 select TPL_NEEDS_SEPARATE_STACK if TPL
62 select SPL_DRIVERS_MISC_SUPPORT
63 imply SPL_SERIAL_SUPPORT
Kever Yangd877fd22019-07-22 19:59:20 +080064 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +080065 imply TPL_SERIAL_SUPPORT
Kever Yang466f3fd2019-07-09 22:05:56 +080066 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +080067 select TPL_LIBCOMMON_SUPPORT
68 select TPL_LIBGENERIC_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +080069 help
70 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
71 including NEON and GPU, Mali-400 graphics, several DDR3 options
72 and video codec support. Peripherals include Gigabit Ethernet,
73 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
74
Simon Glass2cffe662015-08-30 16:55:38 -060075config ROCKCHIP_RK3288
76 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053077 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +080078 select SUPPORT_SPL
79 select SPL
Kever Yangf7c0a332019-07-02 11:43:05 +080080 select SUPPORT_TPL
Kever Yangaa67deb2019-07-22 19:59:27 +080081 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +080082 imply TPL_CLK
83 imply TPL_DM
84 imply TPL_DRIVERS_MISC_SUPPORT
85 imply TPL_LIBCOMMON_SUPPORT
86 imply TPL_LIBGENERIC_SUPPORT
87 imply TPL_NEEDS_SEPARATE_TEXT_BASE
Kever Yangb36e7092019-07-02 11:43:06 +080088 imply TPL_NEEDS_SEPARATE_STACK
Kever Yangf7c0a332019-07-02 11:43:05 +080089 imply TPL_OF_CONTROL
90 imply TPL_OF_PLATDATA
91 imply TPL_RAM
92 imply TPL_REGMAP
Kever Yange32f38e2019-07-09 22:05:57 +080093 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +080094 imply TPL_SERIAL_SUPPORT
95 imply TPL_SYSCON
Eddie Caib3501fe2017-12-15 08:17:13 +080096 imply USB_FUNCTION_ROCKUSB
97 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -060098 help
99 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
100 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
101 video interfaces supporting HDMI and eDP, several DDR3 options
102 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +0100103 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -0600104
Kever Yangec02b3c2017-02-23 15:37:51 +0800105config ROCKCHIP_RK3328
106 bool "Support Rockchip RK3328"
107 select ARM64
Kever Yang07be6692019-06-09 00:27:15 +0300108 select SUPPORT_SPL
109 select SPL
Kever Yangbb4c3252019-07-22 19:59:32 +0800110 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yang07be6692019-06-09 00:27:15 +0300111 imply SPL_SERIAL_SUPPORT
112 imply SPL_SEPARATE_BSS
113 select ENABLE_ARM_SOC_BOOT0_HOOK
114 select DEBUG_UART_BOARD_INIT
115 select SYS_NS16550
Kever Yangec02b3c2017-02-23 15:37:51 +0800116 help
117 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
118 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
119 video interfaces supporting HDMI and eDP, several DDR3 options
120 and video codec support. Peripherals include Gigabit Ethernet,
121 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
122
Andreas Färber9e3ad682017-05-15 17:51:18 +0800123config ROCKCHIP_RK3368
124 bool "Support Rockchip RK3368"
125 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200126 select SUPPORT_SPL
127 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200128 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
129 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang8bf7ed42019-07-22 19:59:34 +0800130 imply SPL_ROCKCHIP_COMMON_BOARD
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200131 imply SPL_SEPARATE_BSS
132 imply SPL_SERIAL_SUPPORT
133 imply TPL_SERIAL_SUPPORT
Kever Yang48831b22019-07-09 22:05:58 +0800134 imply TPL_ROCKCHIP_COMMON_BOARD
Andreas Färber9e3ad682017-05-15 17:51:18 +0800135 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200136 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
137 into a big and little cluster with 4 cores each) Cortex-A53 including
138 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
139 (for the little cluster), PowerVR G6110 based graphics, one video
140 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
141 video codec support.
142
143 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
144 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800145
Kever Yang0d3d7832016-07-19 21:16:59 +0800146config ROCKCHIP_RK3399
147 bool "Support Rockchip RK3399"
148 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800149 select SUPPORT_SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800150 select SUPPORT_TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800151 select SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530152 select SPL_ATF
153 select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Jagan Tekice063b92019-06-21 00:25:03 +0530154 select SPL_BOARD_INIT if SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530155 select SPL_LOAD_FIT
156 select SPL_CLK if SPL
157 select SPL_PINCTRL if SPL
158 select SPL_RAM if SPL
159 select SPL_REGMAP if SPL
160 select SPL_SYSCON if SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800161 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
162 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800163 select SPL_SEPARATE_BSS
Philipp Tomsichd17d8cf2017-07-26 12:29:01 +0200164 select SPL_SERIAL_SUPPORT
165 select SPL_DRIVERS_MISC_SUPPORT
Jagan Tekicd433892019-05-08 11:11:43 +0530166 select CLK
167 select FIT
168 select PINCTRL
169 select RAM
170 select REGMAP
171 select SYSCON
172 select DM_PMIC
173 select DM_REGULATOR_FIXED
Andy Yan70378cb2017-10-11 15:00:16 +0800174 select BOARD_LATE_INIT
Kever Yangff9afe42019-07-22 19:59:42 +0800175 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangfca798d2018-11-09 11:18:15 +0800176 imply TPL_SERIAL_SUPPORT
177 imply TPL_LIBCOMMON_SUPPORT
178 imply TPL_LIBGENERIC_SUPPORT
179 imply TPL_SYS_MALLOC_SIMPLE
Kever Yangfca798d2018-11-09 11:18:15 +0800180 imply TPL_DRIVERS_MISC_SUPPORT
181 imply TPL_OF_CONTROL
182 imply TPL_DM
183 imply TPL_REGMAP
184 imply TPL_SYSCON
185 imply TPL_RAM
186 imply TPL_CLK
187 imply TPL_TINY_MEMSET
Kever Yang3cfbb942019-07-09 22:06:01 +0800188 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yang0d3d7832016-07-19 21:16:59 +0800189 help
190 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
191 and quad-core Cortex-A53.
192 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
193 video interfaces supporting HDMI and eDP, several DDR3 options
194 and video codec support. Peripherals include Gigabit Ethernet,
195 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
196
Andy Yan2d982da2017-06-01 18:00:55 +0800197config ROCKCHIP_RV1108
198 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530199 select CPU_V7A
Andy Yan2d982da2017-06-01 18:00:55 +0800200 help
201 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
202 and a DSP.
203
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200204config ROCKCHIP_USB_UART
205 bool "Route uart output to usb pins"
206 help
207 Rockchip SoCs have the ability to route the signals of the debug
208 uart through the d+ and d- pins of a specific usb phy to enable
209 some form of closed-case debugging. With this option supported
210 SoCs will enable this routing as a debug measure.
211
Philipp Tomsich798370f2017-06-29 11:21:15 +0200212config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800213 bool "SPL returns to bootrom"
214 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100215 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800216 select SPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200217 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800218 help
219 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
220 SPL will return to the boot rom, which will then load the U-Boot
221 binary to keep going on.
222
Philipp Tomsich798370f2017-06-29 11:21:15 +0200223config TPL_ROCKCHIP_BACK_TO_BROM
224 bool "TPL returns to bootrom"
Kever Yangfca798d2018-11-09 11:18:15 +0800225 default y
Philipp Tomsich798370f2017-06-29 11:21:15 +0200226 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800227 select TPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200228 depends on TPL
229 help
230 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
231 SPL will return to the boot rom, which will then load the U-Boot
232 binary to keep going on.
233
Kever Yangbb337732019-07-22 20:02:01 +0800234config ROCKCHIP_COMMON_BOARD
235 bool "Rockchip common board file"
236 help
237 Rockchip SoCs have similar boot process, Common board file is mainly
238 in charge of common process of board_init() and board_late_init() for
239 U-Boot proper.
240
Kever Yang1d7cc72a2019-07-22 19:59:12 +0800241config SPL_ROCKCHIP_COMMON_BOARD
242 bool "Rockchip SPL common board file"
243 depends on SPL
244 help
245 Rockchip SoCs have similar boot process, SPL is mainly in charge of
246 load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
247 no TPL for the board.
248
Kever Yang34ead0f2019-07-09 22:05:55 +0800249config TPL_ROCKCHIP_COMMON_BOARD
250 bool ""
251 depends on TPL
252 help
253 Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
254 init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
255 common board is a basic TPL board init which can be shared for most
256 of SoCs to avoid copy-pase for different SoCs.
257
Andy Yan70378cb2017-10-11 15:00:16 +0800258config ROCKCHIP_BOOT_MODE_REG
259 hex "Rockchip boot mode flag register address"
Andy Yan70378cb2017-10-11 15:00:16 +0800260 help
Kever Yang9fbe17c2019-03-28 11:01:23 +0800261 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yan70378cb2017-10-11 15:00:16 +0800262 according to the value from this register.
263
Kever Yange484f772017-04-20 17:03:46 +0800264config ROCKCHIP_SPL_RESERVE_IRAM
265 hex "Size of IRAM reserved in SPL"
Kever Yang60a50072017-12-18 15:13:19 +0800266 default 0
Kever Yange484f772017-04-20 17:03:46 +0800267 help
268 SPL may need reserve memory for firmware loaded by SPL, whose load
269 address is in IRAM and may overlay with SPL text area if not
270 reserved.
271
Heiko Stübner355a8802017-02-18 19:46:25 +0100272config ROCKCHIP_BROM_HELPER
273 bool
274
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200275config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
276 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
277 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
278 help
279 Some Rockchip BROM variants (e.g. on the RK3188) load the
280 first stage in segments and enter multiple times. E.g. on
281 the RK3188, the first 1KB of the first stage are loaded
282 first and entered; after returning to the BROM, the
283 remainder of the first stage is loaded, but the BROM
284 re-enters at the same address/to the same code as previously.
285
286 This enables support code in the BOOT0 hook for the SPL stage
287 to allow multiple entries.
288
289config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
290 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
291 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
292 help
293 Some Rockchip BROM variants (e.g. on the RK3188) load the
294 first stage in segments and enter multiple times. E.g. on
295 the RK3188, the first 1KB of the first stage are loaded
296 first and entered; after returning to the BROM, the
297 remainder of the first stage is loaded, but the BROM
298 re-enters at the same address/to the same code as previously.
299
300 This enables support code in the BOOT0 hook for the TPL stage
301 to allow multiple entries.
302
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400303config SPL_MMC_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200304 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400305
huang lin1115b642015-11-17 14:20:27 +0800306source "arch/arm/mach-rockchip/rk3036/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800307source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100308source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800309source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200310source "arch/arm/mach-rockchip/rk3288/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800311source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800312source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800313source "arch/arm/mach-rockchip/rk3399/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800314source "arch/arm/mach-rockchip/rv1108/Kconfig"
Simon Glass2cffe662015-08-30 16:55:38 -0600315endif