blob: 1bc7ee90427583dd2a56dd5a3c1166375735c990 [file] [log] [blame]
Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stuebnerfc367852019-07-16 22:18:21 +02003config ROCKCHIP_PX30
4 bool "Support Rockchip PX30"
5 select ARM64
6 select SUPPORT_SPL
7 select SUPPORT_TPL
8 select SPL
9 select TPL
10 select TPL_TINY_FRAMEWORK if TPL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020011 select TPL_NEEDS_SEPARATE_STACK if TPL
12 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -060013 select SPL_SERIAL
14 select TPL_SERIAL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020015 select DEBUG_UART_BOARD_INIT
16 imply ROCKCHIP_COMMON_BOARD
17 imply SPL_ROCKCHIP_COMMON_BOARD
18 help
19 The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
20 including NEON and GPU, Mali-400 graphics, several DDR3 options
21 and video codec support. Peripherals include Gigabit Ethernet,
22 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
23
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020024config ROCKCHIP_RK3036
25 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053026 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +080027 select SUPPORT_SPL
28 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +080029 imply USB_FUNCTION_ROCKUSB
30 imply CMD_ROCKUSB
Kever Yang427cb672019-07-22 20:02:04 +080031 imply ROCKCHIP_COMMON_BOARD
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020032 help
33 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
34 including NEON and GPU, Mali-400 graphics, several DDR3 options
35 and video codec support. Peripherals include Gigabit Ethernet,
36 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
37
Johan Jonkera289fc72022-04-16 17:09:47 +020038config ROCKCHIP_RK3066
39 bool "Support Rockchip RK3066"
40 select CPU_V7A
41 select SPL_BOARD_INIT if SPL
42 select SUPPORT_SPL
43 select SUPPORT_TPL
44 select SPL
45 select TPL
46 select TPL_ROCKCHIP_BACK_TO_BROM
47 select TPL_ROCKCHIP_EARLYRETURN_TO_BROM
48 imply ROCKCHIP_COMMON_BOARD
49 imply SPL_ROCKCHIP_COMMON_BOARD
50 imply SPL_SERIAL
51 imply TPL_ROCKCHIP_COMMON_BOARD
52 imply TPL_SERIAL
53 help
54 The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
55 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
56 video interfaces, several memory options and video codec support.
57 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
58 UART, SPI, I2C and PWMs.
59
Kever Yangaa827752017-11-28 16:04:16 +080060config ROCKCHIP_RK3128
61 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053062 select CPU_V7A
Kever Yang96362722019-07-22 20:02:05 +080063 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa827752017-11-28 16:04:16 +080064 help
65 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
66 including NEON and GPU, Mali-400 graphics, several DDR3 options
67 and video codec support. Peripherals include Gigabit Ethernet,
68 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
69
Heiko Stübneref6db5e2017-02-18 19:46:36 +010070config ROCKCHIP_RK3188
71 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053072 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080073 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010074 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010075 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020076 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020077 select SPL_REGMAP
78 select SPL_SYSCON
79 select SPL_RAM
Simon Glass284cb9c2021-07-10 21:14:31 -060080 select SPL_DRIVERS_MISC
Philipp Tomsich16c689c2017-10-10 16:21:15 +020081 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangbd8532e2019-07-22 19:59:15 +080082 select SPL_ROCKCHIP_BACK_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020083 select BOARD_LATE_INIT
Kever Yangbfd3f872019-07-22 20:02:09 +080084 imply ROCKCHIP_COMMON_BOARD
Kever Yang3bd90402019-07-22 19:59:18 +080085 imply SPL_ROCKCHIP_COMMON_BOARD
Heiko Stübneref6db5e2017-02-18 19:46:36 +010086 help
87 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
88 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
89 video interfaces, several memory options and video codec support.
90 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
91 UART, SPI, I2C and PWMs.
92
Kever Yang57d4dbf2017-06-23 17:17:52 +080093config ROCKCHIP_RK322X
94 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053095 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080096 select SUPPORT_SPL
Kever Yangaff40c62019-04-02 20:41:24 +080097 select SUPPORT_TPL
Kever Yang57d4dbf2017-06-23 17:17:52 +080098 select SPL
Kever Yangaff40c62019-04-02 20:41:24 +080099 select SPL_DM
100 select SPL_OF_LIBFDT
101 select TPL
102 select TPL_DM
103 select TPL_OF_LIBFDT
Kever Yangaff40c62019-04-02 20:41:24 +0800104 select TPL_NEEDS_SEPARATE_STACK if TPL
Simon Glass284cb9c2021-07-10 21:14:31 -0600105 select SPL_DRIVERS_MISC
Kever Yang0b517732019-07-22 20:02:07 +0800106 imply ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600107 imply SPL_SERIAL
Kever Yangd877fd22019-07-22 19:59:20 +0800108 imply SPL_ROCKCHIP_COMMON_BOARD
Alex Bee4fe31122023-07-18 16:57:13 +0200109 select SPL_OPTEE_IMAGE if SPL_FIT
Simon Glassf4d60392021-08-08 12:20:12 -0600110 imply TPL_SERIAL
Kever Yang466f3fd2019-07-09 22:05:56 +0800111 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +0800112 select TPL_LIBCOMMON_SUPPORT
113 select TPL_LIBGENERIC_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +0800114 help
115 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
116 including NEON and GPU, Mali-400 graphics, several DDR3 options
117 and video codec support. Peripherals include Gigabit Ethernet,
118 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
119
Simon Glass2cffe662015-08-30 16:55:38 -0600120config ROCKCHIP_RK3288
121 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530122 select CPU_V7A
John Keepingd5cb7712023-02-23 19:28:51 +0000123 select OF_SYSTEM_SETUP
Tom Rinie1e85442021-08-27 21:18:30 -0400124 select SKIP_LOWLEVEL_INIT_ONLY
Kever Yang0d3d7832016-07-19 21:16:59 +0800125 select SUPPORT_SPL
126 select SPL
Kever Yangf7c0a332019-07-02 11:43:05 +0800127 select SUPPORT_TPL
Johan Jonker9a26fb12023-12-27 13:06:47 +0100128 select FDT_64BIT
Jagan Teki7b7cc952020-01-23 19:42:19 +0530129 imply PRE_CONSOLE_BUFFER
Kever Yangba875012019-07-22 20:02:15 +0800130 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa67deb2019-07-22 19:59:27 +0800131 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +0800132 imply TPL_CLK
133 imply TPL_DM
Simon Glass284cb9c2021-07-10 21:14:31 -0600134 imply TPL_DRIVERS_MISC
Kever Yangf7c0a332019-07-02 11:43:05 +0800135 imply TPL_LIBCOMMON_SUPPORT
136 imply TPL_LIBGENERIC_SUPPORT
Kever Yangb36e7092019-07-02 11:43:06 +0800137 imply TPL_NEEDS_SEPARATE_STACK
Kever Yangf7c0a332019-07-02 11:43:05 +0800138 imply TPL_OF_CONTROL
139 imply TPL_OF_PLATDATA
140 imply TPL_RAM
141 imply TPL_REGMAP
Kever Yange32f38e2019-07-09 22:05:57 +0800142 imply TPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600143 imply TPL_SERIAL
Kever Yangf7c0a332019-07-02 11:43:05 +0800144 imply TPL_SYSCON
Eddie Caib3501fe2017-12-15 08:17:13 +0800145 imply USB_FUNCTION_ROCKUSB
146 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -0600147 help
148 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
149 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
150 video interfaces supporting HDMI and eDP, several DDR3 options
151 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +0100152 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -0600153
Andy Yanb5e16302019-11-14 11:21:12 +0800154config ROCKCHIP_RK3308
155 bool "Support Rockchip RK3308"
156 select ARM64
Andy Yanb5e16302019-11-14 11:21:12 +0800157 select SUPPORT_SPL
158 select SUPPORT_TPL
159 select SPL
160 select SPL_ATF
161 select SPL_ATF_NO_PLATFORM_PARAM
162 select SPL_LOAD_FIT
163 imply ROCKCHIP_COMMON_BOARD
164 imply SPL_ROCKCHIP_COMMON_BOARD
165 imply SPL_CLK
166 imply SPL_REGMAP
167 imply SPL_SYSCON
168 imply SPL_RAM
Simon Glassf4d60392021-08-08 12:20:12 -0600169 imply SPL_SERIAL
Andy Yanb5e16302019-11-14 11:21:12 +0800170 imply SPL_SEPARATE_BSS
171 help
172 The Rockchip RK3308 is a ARM-based Soc which embedded with quad
173 Cortex-A35 and highly integrated audio interfaces.
174
Kever Yangec02b3c2017-02-23 15:37:51 +0800175config ROCKCHIP_RK3328
176 bool "Support Rockchip RK3328"
177 select ARM64
Kever Yang07be6692019-06-09 00:27:15 +0300178 select SUPPORT_SPL
179 select SPL
Kever Yang69871852019-08-02 10:40:01 +0300180 select SUPPORT_TPL
181 select TPL
Kever Yang69871852019-08-02 10:40:01 +0300182 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang205e2cc2019-07-22 20:02:16 +0800183 imply ROCKCHIP_COMMON_BOARD
YouMin Chenb9f7df32019-11-15 11:04:44 +0800184 imply ROCKCHIP_SDRAM_COMMON
Kever Yangbb4c3252019-07-22 19:59:32 +0800185 imply SPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600186 imply SPL_SERIAL
187 imply TPL_SERIAL
Kever Yang07be6692019-06-09 00:27:15 +0300188 imply SPL_SEPARATE_BSS
189 select ENABLE_ARM_SOC_BOOT0_HOOK
190 select DEBUG_UART_BOARD_INIT
191 select SYS_NS16550
Kever Yangec02b3c2017-02-23 15:37:51 +0800192 help
193 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
194 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
195 video interfaces supporting HDMI and eDP, several DDR3 options
196 and video codec support. Peripherals include Gigabit Ethernet,
197 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
198
Andreas Färber9e3ad682017-05-15 17:51:18 +0800199config ROCKCHIP_RK3368
200 bool "Support Rockchip RK3368"
201 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200202 select SUPPORT_SPL
203 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200204 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang35b401e2019-07-22 20:02:17 +0800205 imply ROCKCHIP_COMMON_BOARD
Kever Yang8bf7ed42019-07-22 19:59:34 +0800206 imply SPL_ROCKCHIP_COMMON_BOARD
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200207 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600208 imply SPL_SERIAL
209 imply TPL_SERIAL
Kever Yang48831b22019-07-09 22:05:58 +0800210 imply TPL_ROCKCHIP_COMMON_BOARD
Andreas Färber9e3ad682017-05-15 17:51:18 +0800211 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200212 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
213 into a big and little cluster with 4 cores each) Cortex-A53 including
214 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
215 (for the little cluster), PowerVR G6110 based graphics, one video
216 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
217 video codec support.
218
219 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
220 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800221
Kever Yang0d3d7832016-07-19 21:16:59 +0800222config ROCKCHIP_RK3399
223 bool "Support Rockchip RK3399"
224 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800225 select SUPPORT_SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800226 select SUPPORT_TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800227 select SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530228 select SPL_ATF
Jagan Tekice063b92019-06-21 00:25:03 +0530229 select SPL_BOARD_INIT if SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530230 select SPL_LOAD_FIT
231 select SPL_CLK if SPL
232 select SPL_PINCTRL if SPL
233 select SPL_RAM if SPL
234 select SPL_REGMAP if SPL
235 select SPL_SYSCON if SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800236 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800237 select SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600238 select SPL_SERIAL
Simon Glass284cb9c2021-07-10 21:14:31 -0600239 select SPL_DRIVERS_MISC
Jagan Tekicd433892019-05-08 11:11:43 +0530240 select CLK
241 select FIT
242 select PINCTRL
243 select RAM
244 select REGMAP
245 select SYSCON
246 select DM_PMIC
247 select DM_REGULATOR_FIXED
Andy Yan70378cb2017-10-11 15:00:16 +0800248 select BOARD_LATE_INIT
Sughosh Ganuc1b8e8b2022-11-10 14:49:15 +0530249 imply PARTITION_TYPE_GUID
Jagan Teki9249d5c2020-04-02 17:11:23 +0530250 imply PRE_CONSOLE_BUFFER
Kever Yang9554a4e2019-07-22 20:02:19 +0800251 imply ROCKCHIP_COMMON_BOARD
YouMin Chen23ae72e2019-11-15 11:04:45 +0800252 imply ROCKCHIP_SDRAM_COMMON
Kever Yangff9afe42019-07-22 19:59:42 +0800253 imply SPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600254 imply TPL_SERIAL
Kever Yangfca798d2018-11-09 11:18:15 +0800255 imply TPL_LIBCOMMON_SUPPORT
256 imply TPL_LIBGENERIC_SUPPORT
257 imply TPL_SYS_MALLOC_SIMPLE
Simon Glass284cb9c2021-07-10 21:14:31 -0600258 imply TPL_DRIVERS_MISC
Kever Yangfca798d2018-11-09 11:18:15 +0800259 imply TPL_OF_CONTROL
260 imply TPL_DM
261 imply TPL_REGMAP
262 imply TPL_SYSCON
263 imply TPL_RAM
264 imply TPL_CLK
265 imply TPL_TINY_MEMSET
Kever Yang3cfbb942019-07-09 22:06:01 +0800266 imply TPL_ROCKCHIP_COMMON_BOARD
Jagan Tekie7043012020-01-09 14:22:19 +0530267 imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
Shantur Rathorec0009892024-01-21 22:04:47 +0000268 imply BOOTSTD_FULL
Jagan Tekie7043012020-01-09 14:22:19 +0530269 imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
Kever Yang0d3d7832016-07-19 21:16:59 +0800270 help
271 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
272 and quad-core Cortex-A53.
273 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
274 video interfaces supporting HDMI and eDP, several DDR3 options
275 and video codec support. Peripherals include Gigabit Ethernet,
276 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
277
Joseph Chen72cd8792021-06-02 15:58:25 +0800278config ROCKCHIP_RK3568
279 bool "Support Rockchip RK3568"
280 select ARM64
Nico Cheng00ceeb02021-10-26 10:42:19 +0800281 select SUPPORT_SPL
282 select SPL
Joseph Chen72cd8792021-06-02 15:58:25 +0800283 select CLK
284 select PINCTRL
285 select RAM
286 select REGMAP
287 select SYSCON
288 select BOARD_LATE_INIT
Manoj Saib34b19c2023-02-17 17:28:44 +0530289 select DM_REGULATOR_FIXED
Jagan Tekice0bbac2023-02-17 17:28:34 +0530290 select DM_RESET
Jonas Karlman47af53c2023-04-17 19:07:15 +0000291 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Joseph Chen72cd8792021-06-02 15:58:25 +0800292 imply ROCKCHIP_COMMON_BOARD
Jonas Karlmanf4d27e92023-04-17 19:07:17 +0000293 imply OF_LIBFDT_OVERLAY
Jonas Karlmanbe56bb52023-02-22 22:44:41 +0000294 imply ROCKCHIP_OTP
295 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000296 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
297 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Joseph Chen72cd8792021-06-02 15:58:25 +0800298 help
299 The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
300 including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
301 two video interfaces supporting HDMI and eDP, several DDR3 options
302 and video codec support. Peripherals include Gigabit Ethernet,
303 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
304
Jagan Teki8967dea2023-01-30 20:27:45 +0530305config ROCKCHIP_RK3588
306 bool "Support Rockchip RK3588"
307 select ARM64
308 select SUPPORT_SPL
309 select SPL
310 select CLK
311 select PINCTRL
312 select RAM
313 select REGMAP
314 select SYSCON
315 select BOARD_LATE_INIT
Jonas Karlman9bfd6512023-05-17 18:26:37 +0000316 select DM_REGULATOR_FIXED
317 select DM_RESET
Jonas Karlman47af53c2023-04-17 19:07:15 +0000318 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Jagan Teki8967dea2023-01-30 20:27:45 +0530319 imply ROCKCHIP_COMMON_BOARD
Jonas Karlmanf4d27e92023-04-17 19:07:17 +0000320 imply OF_LIBFDT_OVERLAY
Jonas Karlmaneeb19172023-02-22 22:44:41 +0000321 imply ROCKCHIP_OTP
322 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000323 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
324 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Jonas Karlmanfc805c22023-04-17 19:07:21 +0000325 imply CLK_SCMI
326 imply SCMI_FIRMWARE
Shantur Rathorec0009892024-01-21 22:04:47 +0000327 imply BOOTSTD_FULL
Jagan Teki8967dea2023-01-30 20:27:45 +0530328 help
329 The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
330 quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
331 HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1,
332 SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet,
333 SDIO3.0 I2C, UART, SPI, GPIO and PWM.
334
Andy Yan2d982da2017-06-01 18:00:55 +0800335config ROCKCHIP_RV1108
336 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530337 select CPU_V7A
Kever Yanga2b336e2019-07-22 20:02:21 +0800338 imply ROCKCHIP_COMMON_BOARD
Andy Yan2d982da2017-06-01 18:00:55 +0800339 help
340 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
341 and a DSP.
342
Jagan Teki249a2382022-12-14 23:21:05 +0530343config ROCKCHIP_RV1126
344 bool "Support Rockchip RV1126"
345 select CPU_V7A
346 select SKIP_LOWLEVEL_INIT_ONLY
347 select TPL
348 select SUPPORT_TPL
349 select TPL_NEEDS_SEPARATE_STACK
350 select TPL_ROCKCHIP_BACK_TO_BROM
351 select SPL
352 select SUPPORT_SPL
353 select SPL_STACK_R
354 select CLK
355 select FIT
356 select PINCTRL
357 select RAM
358 select ROCKCHIP_SDRAM_COMMON
359 select REGMAP
360 select SYSCON
361 select DM_PMIC
362 select DM_REGULATOR_FIXED
363 select DM_RESET
364 select REGULATOR_RK8XX
365 select PMIC_RK8XX
366 select BOARD_LATE_INIT
367 imply ROCKCHIP_COMMON_BOARD
Tim Lunnd0812b22024-01-24 14:26:01 +1100368 select SPL_OPTEE_IMAGE if SPL_FIT
Jagan Tekid679f622023-07-29 19:11:42 +0530369 imply OF_LIBFDT_OVERLAY
Tim Lunncbfee492023-10-31 13:07:15 +1100370 imply ROCKCHIP_OTP
371 imply MISC_INIT_R
Jagan Teki249a2382022-12-14 23:21:05 +0530372 imply TPL_DM
373 imply TPL_LIBCOMMON_SUPPORT
374 imply TPL_LIBGENERIC_SUPPORT
375 imply TPL_OF_CONTROL
376 imply TPL_OF_PLATDATA
377 imply TPL_RAM
378 imply TPL_ROCKCHIP_COMMON_BOARD
379 imply TPL_SERIAL
380 imply SPL_CLK
381 imply SPL_DM
382 imply SPL_DRIVERS_MISC
383 imply SPL_LIBCOMMON_SUPPORT
384 imply SPL_LIBGENERIC_SUPPORT
385 imply SPL_OF_CONTROL
386 imply SPL_RAM
387 imply SPL_REGMAP
388 imply SPL_ROCKCHIP_COMMON_BOARD
389 imply SPL_SERIAL
390 imply SPL_SYSCON
391
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200392config ROCKCHIP_USB_UART
393 bool "Route uart output to usb pins"
394 help
395 Rockchip SoCs have the ability to route the signals of the debug
396 uart through the d+ and d- pins of a specific usb phy to enable
397 some form of closed-case debugging. With this option supported
398 SoCs will enable this routing as a debug measure.
399
Philipp Tomsich798370f2017-06-29 11:21:15 +0200400config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800401 bool "SPL returns to bootrom"
402 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100403 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800404 select SPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200405 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800406 help
407 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
408 SPL will return to the boot rom, which will then load the U-Boot
409 binary to keep going on.
410
Philipp Tomsich798370f2017-06-29 11:21:15 +0200411config TPL_ROCKCHIP_BACK_TO_BROM
412 bool "TPL returns to bootrom"
Kever Yangfca798d2018-11-09 11:18:15 +0800413 default y
Johan Jonkera768ff52023-10-27 20:35:37 +0200414 select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066
Kever Yangbd8532e2019-07-22 19:59:15 +0800415 select TPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200416 depends on TPL
417 help
418 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
419 SPL will return to the boot rom, which will then load the U-Boot
420 binary to keep going on.
421
Kever Yangbb337732019-07-22 20:02:01 +0800422config ROCKCHIP_COMMON_BOARD
423 bool "Rockchip common board file"
424 help
425 Rockchip SoCs have similar boot process, Common board file is mainly
426 in charge of common process of board_init() and board_late_init() for
427 U-Boot proper.
428
Kever Yang1d7cc72a2019-07-22 19:59:12 +0800429config SPL_ROCKCHIP_COMMON_BOARD
430 bool "Rockchip SPL common board file"
431 depends on SPL
432 help
433 Rockchip SoCs have similar boot process, SPL is mainly in charge of
434 load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
435 no TPL for the board.
436
Kever Yang34ead0f2019-07-09 22:05:55 +0800437config TPL_ROCKCHIP_COMMON_BOARD
Thomas Hebbcfbebf82019-12-20 18:05:22 -0800438 bool "Rockchip TPL common board file"
Kever Yang34ead0f2019-07-09 22:05:55 +0800439 depends on TPL
440 help
441 Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
442 init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
443 common board is a basic TPL board init which can be shared for most
Thomas Hebbfd37f242019-11-13 18:18:03 -0800444 of SoCs to avoid copy-paste for different SoCs.
Kever Yang34ead0f2019-07-09 22:05:55 +0800445
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000446config ROCKCHIP_EXTERNAL_TPL
447 bool "Use external TPL binary"
Massimo Pegorer8c20dfa2023-09-09 11:33:24 +0200448 default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000449 help
450 Some Rockchip SoCs require an external TPL to initialize DRAM.
451 Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
452 include the external TPL in the image built by binman.
453
Andy Yan70378cb2017-10-11 15:00:16 +0800454config ROCKCHIP_BOOT_MODE_REG
455 hex "Rockchip boot mode flag register address"
Andy Yan70378cb2017-10-11 15:00:16 +0800456 help
Kever Yang9fbe17c2019-03-28 11:01:23 +0800457 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yan70378cb2017-10-11 15:00:16 +0800458 according to the value from this register.
459
Chris Morgan7c9de742022-05-27 13:18:20 -0500460config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON
461 bool "Disable device boot on power plug-in"
462 depends on PMIC_RK8XX
Chris Morgan7c9de742022-05-27 13:18:20 -0500463 ---help---
464 Say Y here to prevent the device from booting up because of a plug-in
465 event. When set, the device will boot briefly to determine why it was
466 powered on, and if it was determined because of a plug-in event
467 instead of a button press event it will shut back off.
468
Johan Jonkerf6fc8952022-04-09 18:55:02 +0200469config ROCKCHIP_STIMER
470 bool "Rockchip STIMER support"
471 default y
472 help
473 Enable Rockchip STIMER support.
474
475config ROCKCHIP_STIMER_BASE
476 hex
477 depends on ROCKCHIP_STIMER
478
Kever Yange484f772017-04-20 17:03:46 +0800479config ROCKCHIP_SPL_RESERVE_IRAM
480 hex "Size of IRAM reserved in SPL"
Tom Rinif18679c2023-08-02 11:09:43 -0400481 default 0x0
Kever Yange484f772017-04-20 17:03:46 +0800482 help
483 SPL may need reserve memory for firmware loaded by SPL, whose load
484 address is in IRAM and may overlay with SPL text area if not
485 reserved.
486
Heiko Stübner355a8802017-02-18 19:46:25 +0100487config ROCKCHIP_BROM_HELPER
488 bool
489
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200490config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
491 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
492 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
493 help
494 Some Rockchip BROM variants (e.g. on the RK3188) load the
495 first stage in segments and enter multiple times. E.g. on
496 the RK3188, the first 1KB of the first stage are loaded
497 first and entered; after returning to the BROM, the
498 remainder of the first stage is loaded, but the BROM
499 re-enters at the same address/to the same code as previously.
500
501 This enables support code in the BOOT0 hook for the SPL stage
502 to allow multiple entries.
503
504config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
505 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
506 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
507 help
508 Some Rockchip BROM variants (e.g. on the RK3188) load the
509 first stage in segments and enter multiple times. E.g. on
510 the RK3188, the first 1KB of the first stage are loaded
511 first and entered; after returning to the BROM, the
512 remainder of the first stage is loaded, but the BROM
513 re-enters at the same address/to the same code as previously.
514
515 This enables support code in the BOOT0 hook for the TPL stage
516 to allow multiple entries.
517
Simon Glassb58bfe02021-08-08 12:20:09 -0600518config SPL_MMC
Philipp Tomsich798370f2017-06-29 11:21:15 +0200519 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400520
Simon Glass88315f72020-07-19 13:55:57 -0600521config ROCKCHIP_SPI_IMAGE
522 bool "Build a SPI image for rockchip"
Simon Glass88315f72020-07-19 13:55:57 -0600523 help
524 Some Rockchip SoCs support booting from SPI flash. Enable this
Quentin Schulz12df9cf2022-09-02 15:10:54 +0200525 option to produce a SPI-flash image containing U-Boot. The image
526 is built by binman. U-Boot sits near the start of the image.
Simon Glass88315f72020-07-19 13:55:57 -0600527
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300528config LNX_KRNL_IMG_TEXT_OFFSET_BASE
Simon Glass72cc5382022-10-20 18:22:39 -0600529 default TEXT_BASE
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300530
Heiko Stuebnerfc367852019-07-16 22:18:21 +0200531source "arch/arm/mach-rockchip/px30/Kconfig"
huang lin1115b642015-11-17 14:20:27 +0800532source "arch/arm/mach-rockchip/rk3036/Kconfig"
Johan Jonkera289fc72022-04-16 17:09:47 +0200533source "arch/arm/mach-rockchip/rk3066/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800534source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100535source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800536source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200537source "arch/arm/mach-rockchip/rk3288/Kconfig"
Andy Yanb5e16302019-11-14 11:21:12 +0800538source "arch/arm/mach-rockchip/rk3308/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800539source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800540source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800541source "arch/arm/mach-rockchip/rk3399/Kconfig"
Joseph Chen16899892021-06-02 16:13:46 +0800542source "arch/arm/mach-rockchip/rk3568/Kconfig"
Jagan Teki8967dea2023-01-30 20:27:45 +0530543source "arch/arm/mach-rockchip/rk3588/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800544source "arch/arm/mach-rockchip/rv1108/Kconfig"
Jagan Teki249a2382022-12-14 23:21:05 +0530545source "arch/arm/mach-rockchip/rv1126/Kconfig"
Simon Glass2cffe662015-08-30 16:55:38 -0600546endif