blob: f1caf4f3738bb0c45bf4643cf8a929693325f01e [file] [log] [blame]
Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stuebnerfc367852019-07-16 22:18:21 +02003config ROCKCHIP_PX30
4 bool "Support Rockchip PX30"
5 select ARM64
6 select SUPPORT_SPL
7 select SUPPORT_TPL
8 select SPL
9 select TPL
10 select TPL_TINY_FRAMEWORK if TPL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020011 select TPL_NEEDS_SEPARATE_STACK if TPL
12 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -060013 select SPL_SERIAL
14 select TPL_SERIAL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020015 select DEBUG_UART_BOARD_INIT
16 imply ROCKCHIP_COMMON_BOARD
17 imply SPL_ROCKCHIP_COMMON_BOARD
18 help
19 The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
20 including NEON and GPU, Mali-400 graphics, several DDR3 options
21 and video codec support. Peripherals include Gigabit Ethernet,
22 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
23
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020024config ROCKCHIP_RK3036
25 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053026 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +080027 select SUPPORT_SPL
28 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +080029 imply USB_FUNCTION_ROCKUSB
30 imply CMD_ROCKUSB
Kever Yang427cb672019-07-22 20:02:04 +080031 imply ROCKCHIP_COMMON_BOARD
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020032 help
33 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
34 including NEON and GPU, Mali-400 graphics, several DDR3 options
35 and video codec support. Peripherals include Gigabit Ethernet,
36 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
37
Johan Jonkera289fc72022-04-16 17:09:47 +020038config ROCKCHIP_RK3066
39 bool "Support Rockchip RK3066"
40 select CPU_V7A
41 select SPL_BOARD_INIT if SPL
42 select SUPPORT_SPL
43 select SUPPORT_TPL
44 select SPL
45 select TPL
46 select TPL_ROCKCHIP_BACK_TO_BROM
47 select TPL_ROCKCHIP_EARLYRETURN_TO_BROM
48 imply ROCKCHIP_COMMON_BOARD
49 imply SPL_ROCKCHIP_COMMON_BOARD
50 imply SPL_SERIAL
51 imply TPL_ROCKCHIP_COMMON_BOARD
52 imply TPL_SERIAL
53 help
54 The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
55 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
56 video interfaces, several memory options and video codec support.
57 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
58 UART, SPI, I2C and PWMs.
59
Kever Yangaa827752017-11-28 16:04:16 +080060config ROCKCHIP_RK3128
61 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053062 select CPU_V7A
Kever Yang96362722019-07-22 20:02:05 +080063 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa827752017-11-28 16:04:16 +080064 help
65 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
66 including NEON and GPU, Mali-400 graphics, several DDR3 options
67 and video codec support. Peripherals include Gigabit Ethernet,
68 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
69
Heiko Stübneref6db5e2017-02-18 19:46:36 +010070config ROCKCHIP_RK3188
71 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053072 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080073 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010074 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010075 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020076 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020077 select SPL_REGMAP
78 select SPL_SYSCON
79 select SPL_RAM
Simon Glass284cb9c2021-07-10 21:14:31 -060080 select SPL_DRIVERS_MISC
Philipp Tomsich16c689c2017-10-10 16:21:15 +020081 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangbd8532e2019-07-22 19:59:15 +080082 select SPL_ROCKCHIP_BACK_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020083 select BOARD_LATE_INIT
Kever Yangbfd3f872019-07-22 20:02:09 +080084 imply ROCKCHIP_COMMON_BOARD
Kever Yang3bd90402019-07-22 19:59:18 +080085 imply SPL_ROCKCHIP_COMMON_BOARD
Heiko Stübneref6db5e2017-02-18 19:46:36 +010086 help
87 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
88 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
89 video interfaces, several memory options and video codec support.
90 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
91 UART, SPI, I2C and PWMs.
92
Kever Yang57d4dbf2017-06-23 17:17:52 +080093config ROCKCHIP_RK322X
94 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053095 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080096 select SUPPORT_SPL
Kever Yangaff40c62019-04-02 20:41:24 +080097 select SUPPORT_TPL
Kever Yang57d4dbf2017-06-23 17:17:52 +080098 select SPL
Kever Yangaff40c62019-04-02 20:41:24 +080099 select SPL_DM
100 select SPL_OF_LIBFDT
101 select TPL
102 select TPL_DM
103 select TPL_OF_LIBFDT
Kever Yangaff40c62019-04-02 20:41:24 +0800104 select TPL_NEEDS_SEPARATE_STACK if TPL
Simon Glass284cb9c2021-07-10 21:14:31 -0600105 select SPL_DRIVERS_MISC
Kever Yang0b517732019-07-22 20:02:07 +0800106 imply ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600107 imply SPL_SERIAL
Kever Yangd877fd22019-07-22 19:59:20 +0800108 imply SPL_ROCKCHIP_COMMON_BOARD
Alex Bee4fe31122023-07-18 16:57:13 +0200109 select SPL_OPTEE_IMAGE if SPL_FIT
Simon Glassf4d60392021-08-08 12:20:12 -0600110 imply TPL_SERIAL
Kever Yang466f3fd2019-07-09 22:05:56 +0800111 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +0800112 select TPL_LIBCOMMON_SUPPORT
113 select TPL_LIBGENERIC_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +0800114 help
115 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
116 including NEON and GPU, Mali-400 graphics, several DDR3 options
117 and video codec support. Peripherals include Gigabit Ethernet,
118 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
119
Simon Glass2cffe662015-08-30 16:55:38 -0600120config ROCKCHIP_RK3288
121 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530122 select CPU_V7A
John Keepingd5cb7712023-02-23 19:28:51 +0000123 select OF_SYSTEM_SETUP
Tom Rinie1e85442021-08-27 21:18:30 -0400124 select SKIP_LOWLEVEL_INIT_ONLY
Kever Yang0d3d7832016-07-19 21:16:59 +0800125 select SUPPORT_SPL
126 select SPL
Kever Yangf7c0a332019-07-02 11:43:05 +0800127 select SUPPORT_TPL
Johan Jonker9a26fb12023-12-27 13:06:47 +0100128 select FDT_64BIT
Jagan Teki7b7cc952020-01-23 19:42:19 +0530129 imply PRE_CONSOLE_BUFFER
Kever Yangba875012019-07-22 20:02:15 +0800130 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa67deb2019-07-22 19:59:27 +0800131 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +0800132 imply TPL_CLK
133 imply TPL_DM
Simon Glass284cb9c2021-07-10 21:14:31 -0600134 imply TPL_DRIVERS_MISC
Kever Yangf7c0a332019-07-02 11:43:05 +0800135 imply TPL_LIBCOMMON_SUPPORT
136 imply TPL_LIBGENERIC_SUPPORT
Kever Yangb36e7092019-07-02 11:43:06 +0800137 imply TPL_NEEDS_SEPARATE_STACK
Kever Yangf7c0a332019-07-02 11:43:05 +0800138 imply TPL_OF_CONTROL
139 imply TPL_OF_PLATDATA
140 imply TPL_RAM
141 imply TPL_REGMAP
Kever Yange32f38e2019-07-09 22:05:57 +0800142 imply TPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600143 imply TPL_SERIAL
Kever Yangf7c0a332019-07-02 11:43:05 +0800144 imply TPL_SYSCON
Eddie Caib3501fe2017-12-15 08:17:13 +0800145 imply USB_FUNCTION_ROCKUSB
146 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -0600147 help
148 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
149 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
150 video interfaces supporting HDMI and eDP, several DDR3 options
151 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +0100152 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -0600153
Andy Yanb5e16302019-11-14 11:21:12 +0800154config ROCKCHIP_RK3308
155 bool "Support Rockchip RK3308"
156 select ARM64
Andy Yanb5e16302019-11-14 11:21:12 +0800157 select SUPPORT_SPL
158 select SUPPORT_TPL
159 select SPL
160 select SPL_ATF
161 select SPL_ATF_NO_PLATFORM_PARAM
162 select SPL_LOAD_FIT
Jonas Karlmana2caa162024-04-08 18:14:00 +0000163 imply ARMV8_CRYPTO
164 imply ARMV8_SET_SMPEN
Jonas Karlmanfbced692024-04-08 18:14:02 +0000165 imply DM_RNG
Jonas Karlmana2caa162024-04-08 18:14:00 +0000166 imply LEGACY_IMAGE_FORMAT
Jonas Karlman1cf34dd2024-04-08 18:14:01 +0000167 imply MISC
168 imply MISC_INIT_R
Jonas Karlman0cab3c52024-05-04 19:42:53 +0000169 imply OF_UPSTREAM
Jonas Karlmanfbced692024-04-08 18:14:02 +0000170 imply RNG_ROCKCHIP
Andy Yanb5e16302019-11-14 11:21:12 +0800171 imply ROCKCHIP_COMMON_BOARD
Jonas Karlman1cf34dd2024-04-08 18:14:01 +0000172 imply ROCKCHIP_OTP
Andy Yanb5e16302019-11-14 11:21:12 +0800173 imply SPL_CLK
Jonas Karlmana499c982024-04-08 18:14:03 +0000174 imply SPL_DM_SEQ_ALIAS
Jonas Karlmana2caa162024-04-08 18:14:00 +0000175 imply SPL_FIT_SIGNATURE
Jonas Karlmana499c982024-04-08 18:14:03 +0000176 imply SPL_PINCTRL
Andy Yanb5e16302019-11-14 11:21:12 +0800177 imply SPL_RAM
Jonas Karlman16b0f902024-04-08 18:13:59 +0000178 imply SPL_REGMAP
179 imply SPL_ROCKCHIP_COMMON_BOARD
Andy Yanb5e16302019-11-14 11:21:12 +0800180 imply SPL_SEPARATE_BSS
Jonas Karlman16b0f902024-04-08 18:13:59 +0000181 imply SPL_SERIAL
182 imply SPL_SYSCON
Andy Yanb5e16302019-11-14 11:21:12 +0800183 help
184 The Rockchip RK3308 is a ARM-based Soc which embedded with quad
185 Cortex-A35 and highly integrated audio interfaces.
186
Kever Yangec02b3c2017-02-23 15:37:51 +0800187config ROCKCHIP_RK3328
188 bool "Support Rockchip RK3328"
189 select ARM64
Kever Yang07be6692019-06-09 00:27:15 +0300190 select SUPPORT_SPL
191 select SPL
Kever Yang69871852019-08-02 10:40:01 +0300192 select SUPPORT_TPL
193 select TPL
Kever Yang69871852019-08-02 10:40:01 +0300194 select TPL_NEEDS_SEPARATE_STACK if TPL
Jonas Karlman1b3d9dd2024-04-21 20:09:02 +0000195 imply ARMV8_CRYPTO
196 imply ARMV8_SET_SMPEN
Jonas Karlman86d4ebb2024-04-21 20:09:01 +0000197 imply MISC
198 imply MISC_INIT_R
Jonas Karlman1b3d9dd2024-04-21 20:09:02 +0000199 imply OF_LIVE
Jagan Tekifb71c882024-01-17 13:21:52 +0530200 imply PRE_CONSOLE_BUFFER
Kever Yang205e2cc2019-07-22 20:02:16 +0800201 imply ROCKCHIP_COMMON_BOARD
Jonas Karlman86d4ebb2024-04-21 20:09:01 +0000202 imply ROCKCHIP_EFUSE
YouMin Chenb9f7df32019-11-15 11:04:44 +0800203 imply ROCKCHIP_SDRAM_COMMON
Kever Yangbb4c3252019-07-22 19:59:32 +0800204 imply SPL_ROCKCHIP_COMMON_BOARD
Jonas Karlman86d4ebb2024-04-21 20:09:01 +0000205 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600206 imply SPL_SERIAL
207 imply TPL_SERIAL
Kever Yangec02b3c2017-02-23 15:37:51 +0800208 help
209 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
210 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
211 video interfaces supporting HDMI and eDP, several DDR3 options
212 and video codec support. Peripherals include Gigabit Ethernet,
213 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
214
Andreas Färber9e3ad682017-05-15 17:51:18 +0800215config ROCKCHIP_RK3368
216 bool "Support Rockchip RK3368"
217 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200218 select SUPPORT_SPL
219 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200220 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang35b401e2019-07-22 20:02:17 +0800221 imply ROCKCHIP_COMMON_BOARD
Kever Yang8bf7ed42019-07-22 19:59:34 +0800222 imply SPL_ROCKCHIP_COMMON_BOARD
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200223 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600224 imply SPL_SERIAL
225 imply TPL_SERIAL
Kever Yang48831b22019-07-09 22:05:58 +0800226 imply TPL_ROCKCHIP_COMMON_BOARD
Andreas Färber9e3ad682017-05-15 17:51:18 +0800227 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200228 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
229 into a big and little cluster with 4 cores each) Cortex-A53 including
230 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
231 (for the little cluster), PowerVR G6110 based graphics, one video
232 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
233 video codec support.
234
235 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
236 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800237
Kever Yang0d3d7832016-07-19 21:16:59 +0800238config ROCKCHIP_RK3399
239 bool "Support Rockchip RK3399"
240 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800241 select SUPPORT_SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800242 select SUPPORT_TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800243 select SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530244 select SPL_ATF
Jagan Tekice063b92019-06-21 00:25:03 +0530245 select SPL_BOARD_INIT if SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530246 select SPL_LOAD_FIT
247 select SPL_CLK if SPL
248 select SPL_PINCTRL if SPL
249 select SPL_RAM if SPL
250 select SPL_REGMAP if SPL
251 select SPL_SYSCON if SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800252 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800253 select SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600254 select SPL_SERIAL
Jagan Tekicd433892019-05-08 11:11:43 +0530255 select CLK
256 select FIT
257 select PINCTRL
258 select RAM
259 select REGMAP
260 select SYSCON
261 select DM_PMIC
262 select DM_REGULATOR_FIXED
Andy Yan70378cb2017-10-11 15:00:16 +0800263 select BOARD_LATE_INIT
Jonas Karlman8b663722024-04-30 15:30:13 +0000264 imply ARMV8_CRYPTO
265 imply ARMV8_SET_SMPEN
Jonas Karlmana6389252024-04-30 15:30:12 +0000266 imply BOOTSTD_FULL
267 imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
Jonas Karlman0ad89712024-04-30 15:30:14 +0000268 imply DM_RNG
Jonas Karlman8b663722024-04-30 15:30:13 +0000269 imply LEGACY_IMAGE_FORMAT
Jonas Karlmana6389252024-04-30 15:30:12 +0000270 imply MISC
271 imply MISC_INIT_R
Jonas Karlman7f22b182024-04-30 15:30:16 +0000272 imply OF_LIBFDT_OVERLAY
Jonas Karlman8b663722024-04-30 15:30:13 +0000273 imply OF_LIVE
Sughosh Ganuc1b8e8b2022-11-10 14:49:15 +0530274 imply PARTITION_TYPE_GUID
Jonas Karlman8660d332024-04-30 15:30:15 +0000275 imply PHY_GIGE if GMAC_ROCKCHIP
Jagan Teki9249d5c2020-04-02 17:11:23 +0530276 imply PRE_CONSOLE_BUFFER
Jonas Karlman0ad89712024-04-30 15:30:14 +0000277 imply RNG_ROCKCHIP
Kever Yang9554a4e2019-07-22 20:02:19 +0800278 imply ROCKCHIP_COMMON_BOARD
Jonas Karlmana6389252024-04-30 15:30:12 +0000279 imply ROCKCHIP_EFUSE
YouMin Chen23ae72e2019-11-15 11:04:45 +0800280 imply ROCKCHIP_SDRAM_COMMON
Jonas Karlman20e63412024-04-30 15:30:25 +0000281 imply SPL_DM_SEQ_ALIAS
Jonas Karlman8b663722024-04-30 15:30:13 +0000282 imply SPL_FIT_SIGNATURE
Kever Yangff9afe42019-07-22 19:59:42 +0800283 imply SPL_ROCKCHIP_COMMON_BOARD
Jonas Karlmana6389252024-04-30 15:30:12 +0000284 imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
285 imply TPL_CLK
286 imply TPL_DM
Kever Yangfca798d2018-11-09 11:18:15 +0800287 imply TPL_LIBCOMMON_SUPPORT
288 imply TPL_LIBGENERIC_SUPPORT
Kever Yangfca798d2018-11-09 11:18:15 +0800289 imply TPL_OF_CONTROL
Jonas Karlmana6389252024-04-30 15:30:12 +0000290 imply TPL_RAM
Kever Yangfca798d2018-11-09 11:18:15 +0800291 imply TPL_REGMAP
Jonas Karlmana6389252024-04-30 15:30:12 +0000292 imply TPL_ROCKCHIP_COMMON_BOARD
293 imply TPL_SERIAL
294 imply TPL_SYS_MALLOC_SIMPLE
Kever Yangfca798d2018-11-09 11:18:15 +0800295 imply TPL_SYSCON
Kever Yangfca798d2018-11-09 11:18:15 +0800296 imply TPL_TINY_MEMSET
Kever Yang0d3d7832016-07-19 21:16:59 +0800297 help
298 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
299 and quad-core Cortex-A53.
300 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
301 video interfaces supporting HDMI and eDP, several DDR3 options
302 and video codec support. Peripherals include Gigabit Ethernet,
303 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
304
Joseph Chen72cd8792021-06-02 15:58:25 +0800305config ROCKCHIP_RK3568
306 bool "Support Rockchip RK3568"
307 select ARM64
Nico Cheng00ceeb02021-10-26 10:42:19 +0800308 select SUPPORT_SPL
309 select SPL
Joseph Chen72cd8792021-06-02 15:58:25 +0800310 select CLK
311 select PINCTRL
312 select RAM
313 select REGMAP
314 select SYSCON
315 select BOARD_LATE_INIT
Manoj Saib34b19c2023-02-17 17:28:44 +0530316 select DM_REGULATOR_FIXED
Jagan Tekice0bbac2023-02-17 17:28:34 +0530317 select DM_RESET
Jonas Karlmanc1bb7122024-04-22 06:28:47 +0000318 imply BOOTSTD_FULL
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000319 imply DM_RNG
Jonas Karlmanbe56bb52023-02-22 22:44:41 +0000320 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000321 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000322 imply OF_LIBFDT_OVERLAY
Jonas Karlmane8b5bae2024-04-22 06:28:46 +0000323 imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000324 imply RNG_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000325 imply ROCKCHIP_COMMON_BOARD
326 imply ROCKCHIP_OTP
327 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000328 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Joseph Chen72cd8792021-06-02 15:58:25 +0800329 help
330 The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
331 including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
332 two video interfaces supporting HDMI and eDP, several DDR3 options
333 and video codec support. Peripherals include Gigabit Ethernet,
334 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
335
Jagan Teki8967dea2023-01-30 20:27:45 +0530336config ROCKCHIP_RK3588
337 bool "Support Rockchip RK3588"
338 select ARM64
339 select SUPPORT_SPL
340 select SPL
341 select CLK
342 select PINCTRL
343 select RAM
344 select REGMAP
345 select SYSCON
346 select BOARD_LATE_INIT
Jonas Karlman9bfd6512023-05-17 18:26:37 +0000347 select DM_REGULATOR_FIXED
348 select DM_RESET
Jonas Karlman0eb24592024-04-22 06:28:44 +0000349 imply BOOTSTD_FULL
350 imply CLK_SCMI
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000351 imply DM_RNG
Jonas Karlmaneeb19172023-02-22 22:44:41 +0000352 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000353 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000354 imply OF_LIBFDT_OVERLAY
Jonas Karlmane8b5bae2024-04-22 06:28:46 +0000355 imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000356 imply RNG_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000357 imply ROCKCHIP_COMMON_BOARD
358 imply ROCKCHIP_OTP
Jonas Karlmanfc805c22023-04-17 19:07:21 +0000359 imply SCMI_FIRMWARE
Jonas Karlman0eb24592024-04-22 06:28:44 +0000360 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
361 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Jagan Teki8967dea2023-01-30 20:27:45 +0530362 help
363 The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
364 quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
365 HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1,
366 SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet,
367 SDIO3.0 I2C, UART, SPI, GPIO and PWM.
368
Andy Yan2d982da2017-06-01 18:00:55 +0800369config ROCKCHIP_RV1108
370 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530371 select CPU_V7A
Kever Yanga2b336e2019-07-22 20:02:21 +0800372 imply ROCKCHIP_COMMON_BOARD
Andy Yan2d982da2017-06-01 18:00:55 +0800373 help
374 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
375 and a DSP.
376
Jagan Teki249a2382022-12-14 23:21:05 +0530377config ROCKCHIP_RV1126
378 bool "Support Rockchip RV1126"
379 select CPU_V7A
380 select SKIP_LOWLEVEL_INIT_ONLY
381 select TPL
382 select SUPPORT_TPL
383 select TPL_NEEDS_SEPARATE_STACK
384 select TPL_ROCKCHIP_BACK_TO_BROM
385 select SPL
386 select SUPPORT_SPL
387 select SPL_STACK_R
388 select CLK
389 select FIT
390 select PINCTRL
391 select RAM
392 select ROCKCHIP_SDRAM_COMMON
393 select REGMAP
394 select SYSCON
395 select DM_PMIC
396 select DM_REGULATOR_FIXED
397 select DM_RESET
398 select REGULATOR_RK8XX
399 select PMIC_RK8XX
400 select BOARD_LATE_INIT
401 imply ROCKCHIP_COMMON_BOARD
Tim Lunnd0812b22024-01-24 14:26:01 +1100402 select SPL_OPTEE_IMAGE if SPL_FIT
Jagan Tekid679f622023-07-29 19:11:42 +0530403 imply OF_LIBFDT_OVERLAY
Tim Lunncbfee492023-10-31 13:07:15 +1100404 imply ROCKCHIP_OTP
405 imply MISC_INIT_R
Jagan Teki249a2382022-12-14 23:21:05 +0530406 imply TPL_DM
407 imply TPL_LIBCOMMON_SUPPORT
408 imply TPL_LIBGENERIC_SUPPORT
409 imply TPL_OF_CONTROL
410 imply TPL_OF_PLATDATA
411 imply TPL_RAM
412 imply TPL_ROCKCHIP_COMMON_BOARD
413 imply TPL_SERIAL
414 imply SPL_CLK
415 imply SPL_DM
416 imply SPL_DRIVERS_MISC
417 imply SPL_LIBCOMMON_SUPPORT
418 imply SPL_LIBGENERIC_SUPPORT
419 imply SPL_OF_CONTROL
420 imply SPL_RAM
421 imply SPL_REGMAP
422 imply SPL_ROCKCHIP_COMMON_BOARD
423 imply SPL_SERIAL
424 imply SPL_SYSCON
425
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200426config ROCKCHIP_USB_UART
427 bool "Route uart output to usb pins"
428 help
429 Rockchip SoCs have the ability to route the signals of the debug
430 uart through the d+ and d- pins of a specific usb phy to enable
431 some form of closed-case debugging. With this option supported
432 SoCs will enable this routing as a debug measure.
433
Philipp Tomsich798370f2017-06-29 11:21:15 +0200434config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800435 bool "SPL returns to bootrom"
436 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100437 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800438 select SPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200439 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800440 help
441 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
442 SPL will return to the boot rom, which will then load the U-Boot
443 binary to keep going on.
444
Philipp Tomsich798370f2017-06-29 11:21:15 +0200445config TPL_ROCKCHIP_BACK_TO_BROM
446 bool "TPL returns to bootrom"
Kever Yangfca798d2018-11-09 11:18:15 +0800447 default y
Johan Jonkera768ff52023-10-27 20:35:37 +0200448 select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066
Kever Yangbd8532e2019-07-22 19:59:15 +0800449 select TPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200450 depends on TPL
451 help
452 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
453 SPL will return to the boot rom, which will then load the U-Boot
454 binary to keep going on.
455
Kever Yangbb337732019-07-22 20:02:01 +0800456config ROCKCHIP_COMMON_BOARD
457 bool "Rockchip common board file"
458 help
459 Rockchip SoCs have similar boot process, Common board file is mainly
460 in charge of common process of board_init() and board_late_init() for
461 U-Boot proper.
462
Kever Yang1d7cc72a2019-07-22 19:59:12 +0800463config SPL_ROCKCHIP_COMMON_BOARD
464 bool "Rockchip SPL common board file"
465 depends on SPL
466 help
467 Rockchip SoCs have similar boot process, SPL is mainly in charge of
468 load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
469 no TPL for the board.
470
Kever Yang34ead0f2019-07-09 22:05:55 +0800471config TPL_ROCKCHIP_COMMON_BOARD
Thomas Hebbcfbebf82019-12-20 18:05:22 -0800472 bool "Rockchip TPL common board file"
Kever Yang34ead0f2019-07-09 22:05:55 +0800473 depends on TPL
474 help
475 Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
476 init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
477 common board is a basic TPL board init which can be shared for most
Thomas Hebbfd37f242019-11-13 18:18:03 -0800478 of SoCs to avoid copy-paste for different SoCs.
Kever Yang34ead0f2019-07-09 22:05:55 +0800479
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000480config ROCKCHIP_EXTERNAL_TPL
481 bool "Use external TPL binary"
Massimo Pegorer8c20dfa2023-09-09 11:33:24 +0200482 default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000483 help
484 Some Rockchip SoCs require an external TPL to initialize DRAM.
485 Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
486 include the external TPL in the image built by binman.
487
Andy Yan70378cb2017-10-11 15:00:16 +0800488config ROCKCHIP_BOOT_MODE_REG
489 hex "Rockchip boot mode flag register address"
Andy Yan70378cb2017-10-11 15:00:16 +0800490 help
Kever Yang9fbe17c2019-03-28 11:01:23 +0800491 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yan70378cb2017-10-11 15:00:16 +0800492 according to the value from this register.
493
Chris Morgan7c9de742022-05-27 13:18:20 -0500494config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON
495 bool "Disable device boot on power plug-in"
496 depends on PMIC_RK8XX
Chris Morgan7c9de742022-05-27 13:18:20 -0500497 ---help---
498 Say Y here to prevent the device from booting up because of a plug-in
499 event. When set, the device will boot briefly to determine why it was
500 powered on, and if it was determined because of a plug-in event
501 instead of a button press event it will shut back off.
502
Johan Jonkerf6fc8952022-04-09 18:55:02 +0200503config ROCKCHIP_STIMER
504 bool "Rockchip STIMER support"
505 default y
506 help
507 Enable Rockchip STIMER support.
508
509config ROCKCHIP_STIMER_BASE
510 hex
511 depends on ROCKCHIP_STIMER
512
Kever Yange484f772017-04-20 17:03:46 +0800513config ROCKCHIP_SPL_RESERVE_IRAM
514 hex "Size of IRAM reserved in SPL"
Tom Rinif18679c2023-08-02 11:09:43 -0400515 default 0x0
Kever Yange484f772017-04-20 17:03:46 +0800516 help
517 SPL may need reserve memory for firmware loaded by SPL, whose load
518 address is in IRAM and may overlay with SPL text area if not
519 reserved.
520
Heiko Stübner355a8802017-02-18 19:46:25 +0100521config ROCKCHIP_BROM_HELPER
522 bool
523
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200524config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
525 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
526 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
527 help
528 Some Rockchip BROM variants (e.g. on the RK3188) load the
529 first stage in segments and enter multiple times. E.g. on
530 the RK3188, the first 1KB of the first stage are loaded
531 first and entered; after returning to the BROM, the
532 remainder of the first stage is loaded, but the BROM
533 re-enters at the same address/to the same code as previously.
534
535 This enables support code in the BOOT0 hook for the SPL stage
536 to allow multiple entries.
537
Quentin Schulz95b568f2024-03-11 13:01:54 +0100538config ROCKCHIP_DISABLE_FORCE_JTAG
539 bool "Disable force_jtag feature"
540 default y
541 depends on SPL
542 help
543 Rockchip SoCs can automatically switch between jtag and sdmmc based
544 on the following rules:
545 - all the SDMMC pins including SDMMC_DET set as SDMMC function in
546 GRF,
547 - force_jtag bit in GRF is 1,
548 - SDMMC_DET is low (no card detected),
549
550 Some HW design may not route the SD card card detect to SDMMC_DET
551 pin, thus breaking the SD card support in some cases because JTAG
552 would be auto-enabled by mistake.
553
554 Also, enabling JTAG at runtime may be an undesired feature, e.g.
555 because it could be a security vulnerability.
556
557 This disables force_jtag feature, which you may want for debugging
558 purposes.
559
560 If unsure, say Y.
561
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200562config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
563 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
564 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
565 help
566 Some Rockchip BROM variants (e.g. on the RK3188) load the
567 first stage in segments and enter multiple times. E.g. on
568 the RK3188, the first 1KB of the first stage are loaded
569 first and entered; after returning to the BROM, the
570 remainder of the first stage is loaded, but the BROM
571 re-enters at the same address/to the same code as previously.
572
573 This enables support code in the BOOT0 hook for the TPL stage
574 to allow multiple entries.
575
Simon Glassb58bfe02021-08-08 12:20:09 -0600576config SPL_MMC
Philipp Tomsich798370f2017-06-29 11:21:15 +0200577 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400578
Simon Glass88315f72020-07-19 13:55:57 -0600579config ROCKCHIP_SPI_IMAGE
580 bool "Build a SPI image for rockchip"
Simon Glass88315f72020-07-19 13:55:57 -0600581 help
582 Some Rockchip SoCs support booting from SPI flash. Enable this
Quentin Schulz12df9cf2022-09-02 15:10:54 +0200583 option to produce a SPI-flash image containing U-Boot. The image
584 is built by binman. U-Boot sits near the start of the image.
Simon Glass88315f72020-07-19 13:55:57 -0600585
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300586config LNX_KRNL_IMG_TEXT_OFFSET_BASE
Simon Glass72cc5382022-10-20 18:22:39 -0600587 default TEXT_BASE
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300588
Jonas Karlmane4453632024-03-02 19:16:11 +0000589config ROCKCHIP_COMMON_STACK_ADDR
590 bool
591 depends on SPL_SHARES_INIT_SP_ADDR
592 select HAS_CUSTOM_SYS_INIT_SP_ADDR
593 imply SPL_LIBCOMMON_SUPPORT if SPL
594 imply SPL_LIBGENERIC_SUPPORT if SPL
595 imply SPL_ROCKCHIP_COMMON_BOARD if SPL
596 imply SPL_SYS_MALLOC_F if SPL
597 imply SPL_SYS_MALLOC_SIMPLE if SPL
598 imply TPL_LIBCOMMON_SUPPORT if TPL
599 imply TPL_LIBGENERIC_SUPPORT if TPL
600 imply TPL_ROCKCHIP_COMMON_BOARD if TPL
601 imply TPL_SYS_MALLOC_F if TPL
602 imply TPL_SYS_MALLOC_SIMPLE if TPL
603
Quentin Schulzfb2d1ec2024-04-25 12:46:25 +0200604config NR_DRAM_BANKS
605 default 10 if ROCKCHIP_EXTERNAL_TPL
606
Heiko Stuebnerfc367852019-07-16 22:18:21 +0200607source "arch/arm/mach-rockchip/px30/Kconfig"
huang lin1115b642015-11-17 14:20:27 +0800608source "arch/arm/mach-rockchip/rk3036/Kconfig"
Johan Jonkera289fc72022-04-16 17:09:47 +0200609source "arch/arm/mach-rockchip/rk3066/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800610source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100611source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800612source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200613source "arch/arm/mach-rockchip/rk3288/Kconfig"
Andy Yanb5e16302019-11-14 11:21:12 +0800614source "arch/arm/mach-rockchip/rk3308/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800615source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800616source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800617source "arch/arm/mach-rockchip/rk3399/Kconfig"
Joseph Chen16899892021-06-02 16:13:46 +0800618source "arch/arm/mach-rockchip/rk3568/Kconfig"
Jagan Teki8967dea2023-01-30 20:27:45 +0530619source "arch/arm/mach-rockchip/rk3588/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800620source "arch/arm/mach-rockchip/rv1108/Kconfig"
Jagan Teki249a2382022-12-14 23:21:05 +0530621source "arch/arm/mach-rockchip/rv1126/Kconfig"
Jonas Karlmane4453632024-03-02 19:16:11 +0000622
623if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR
624
625config CUSTOM_SYS_INIT_SP_ADDR
626 default 0x3f00000
627
628config SYS_MALLOC_F_LEN
629 default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
630
631config SPL_SYS_MALLOC_F_LEN
632 default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
633
634config TPL_SYS_MALLOC_F_LEN
635 default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
636
637config TEXT_BASE
638 default 0x00200000 if ARM64
639
640config SPL_TEXT_BASE
641 default 0x0 if ARM64
642
643config SPL_HAS_BSS_LINKER_SECTION
644 default y if ARM64
645
646config SPL_BSS_START_ADDR
647 default 0x3f80000
648
649config SPL_BSS_MAX_SIZE
650 default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000
651
652config SPL_STACK_R
653 default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
654
655config SPL_STACK_R_ADDR
656 default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
657
658config SPL_STACK_R_MALLOC_SIMPLE_LEN
659 default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000
660
661endif
Simon Glass2cffe662015-08-30 16:55:38 -0600662endif