blob: 6f1213b1710cca8392122839848659291caf3680 [file] [log] [blame]
Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stuebnerfc367852019-07-16 22:18:21 +02003config ROCKCHIP_PX30
4 bool "Support Rockchip PX30"
5 select ARM64
6 select SUPPORT_SPL
7 select SUPPORT_TPL
8 select SPL
9 select TPL
10 select TPL_TINY_FRAMEWORK if TPL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020011 select TPL_NEEDS_SEPARATE_STACK if TPL
12 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -060013 select SPL_SERIAL
14 select TPL_SERIAL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020015 select DEBUG_UART_BOARD_INIT
16 imply ROCKCHIP_COMMON_BOARD
17 imply SPL_ROCKCHIP_COMMON_BOARD
18 help
19 The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
20 including NEON and GPU, Mali-400 graphics, several DDR3 options
21 and video codec support. Peripherals include Gigabit Ethernet,
22 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
23
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020024config ROCKCHIP_RK3036
25 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053026 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +080027 select SUPPORT_SPL
28 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +080029 imply USB_FUNCTION_ROCKUSB
30 imply CMD_ROCKUSB
Kever Yang427cb672019-07-22 20:02:04 +080031 imply ROCKCHIP_COMMON_BOARD
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020032 help
33 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
34 including NEON and GPU, Mali-400 graphics, several DDR3 options
35 and video codec support. Peripherals include Gigabit Ethernet,
36 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
37
Johan Jonkera289fc72022-04-16 17:09:47 +020038config ROCKCHIP_RK3066
39 bool "Support Rockchip RK3066"
40 select CPU_V7A
41 select SPL_BOARD_INIT if SPL
42 select SUPPORT_SPL
43 select SUPPORT_TPL
44 select SPL
45 select TPL
46 select TPL_ROCKCHIP_BACK_TO_BROM
47 select TPL_ROCKCHIP_EARLYRETURN_TO_BROM
48 imply ROCKCHIP_COMMON_BOARD
49 imply SPL_ROCKCHIP_COMMON_BOARD
50 imply SPL_SERIAL
51 imply TPL_ROCKCHIP_COMMON_BOARD
52 imply TPL_SERIAL
53 help
54 The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
55 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
56 video interfaces, several memory options and video codec support.
57 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
58 UART, SPI, I2C and PWMs.
59
Kever Yangaa827752017-11-28 16:04:16 +080060config ROCKCHIP_RK3128
61 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053062 select CPU_V7A
Kever Yang96362722019-07-22 20:02:05 +080063 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa827752017-11-28 16:04:16 +080064 help
65 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
66 including NEON and GPU, Mali-400 graphics, several DDR3 options
67 and video codec support. Peripherals include Gigabit Ethernet,
68 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
69
Heiko Stübneref6db5e2017-02-18 19:46:36 +010070config ROCKCHIP_RK3188
71 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053072 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080073 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010074 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010075 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020076 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020077 select SPL_REGMAP
78 select SPL_SYSCON
79 select SPL_RAM
Simon Glass284cb9c2021-07-10 21:14:31 -060080 select SPL_DRIVERS_MISC
Philipp Tomsich16c689c2017-10-10 16:21:15 +020081 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangbd8532e2019-07-22 19:59:15 +080082 select SPL_ROCKCHIP_BACK_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020083 select BOARD_LATE_INIT
Kever Yangbfd3f872019-07-22 20:02:09 +080084 imply ROCKCHIP_COMMON_BOARD
Kever Yang3bd90402019-07-22 19:59:18 +080085 imply SPL_ROCKCHIP_COMMON_BOARD
Heiko Stübneref6db5e2017-02-18 19:46:36 +010086 help
87 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
88 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
89 video interfaces, several memory options and video codec support.
90 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
91 UART, SPI, I2C and PWMs.
92
Kever Yang57d4dbf2017-06-23 17:17:52 +080093config ROCKCHIP_RK322X
94 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053095 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080096 select SUPPORT_SPL
Kever Yangaff40c62019-04-02 20:41:24 +080097 select SUPPORT_TPL
Kever Yang57d4dbf2017-06-23 17:17:52 +080098 select SPL
Kever Yangaff40c62019-04-02 20:41:24 +080099 select SPL_DM
100 select SPL_OF_LIBFDT
101 select TPL
102 select TPL_DM
103 select TPL_OF_LIBFDT
Kever Yangaff40c62019-04-02 20:41:24 +0800104 select TPL_NEEDS_SEPARATE_STACK if TPL
Simon Glass284cb9c2021-07-10 21:14:31 -0600105 select SPL_DRIVERS_MISC
Kever Yang0b517732019-07-22 20:02:07 +0800106 imply ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600107 imply SPL_SERIAL
Kever Yangd877fd22019-07-22 19:59:20 +0800108 imply SPL_ROCKCHIP_COMMON_BOARD
Alex Bee4fe31122023-07-18 16:57:13 +0200109 select SPL_OPTEE_IMAGE if SPL_FIT
Simon Glassf4d60392021-08-08 12:20:12 -0600110 imply TPL_SERIAL
Kever Yang466f3fd2019-07-09 22:05:56 +0800111 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +0800112 select TPL_LIBCOMMON_SUPPORT
113 select TPL_LIBGENERIC_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +0800114 help
115 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
116 including NEON and GPU, Mali-400 graphics, several DDR3 options
117 and video codec support. Peripherals include Gigabit Ethernet,
118 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
119
Simon Glass2cffe662015-08-30 16:55:38 -0600120config ROCKCHIP_RK3288
121 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530122 select CPU_V7A
John Keepingd5cb7712023-02-23 19:28:51 +0000123 select OF_SYSTEM_SETUP
Tom Rinie1e85442021-08-27 21:18:30 -0400124 select SKIP_LOWLEVEL_INIT_ONLY
Kever Yang0d3d7832016-07-19 21:16:59 +0800125 select SUPPORT_SPL
126 select SPL
Kever Yangf7c0a332019-07-02 11:43:05 +0800127 select SUPPORT_TPL
Johan Jonker9a26fb12023-12-27 13:06:47 +0100128 select FDT_64BIT
Jagan Teki7b7cc952020-01-23 19:42:19 +0530129 imply PRE_CONSOLE_BUFFER
Kever Yangba875012019-07-22 20:02:15 +0800130 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa67deb2019-07-22 19:59:27 +0800131 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +0800132 imply TPL_CLK
133 imply TPL_DM
Simon Glass284cb9c2021-07-10 21:14:31 -0600134 imply TPL_DRIVERS_MISC
Kever Yangf7c0a332019-07-02 11:43:05 +0800135 imply TPL_LIBCOMMON_SUPPORT
136 imply TPL_LIBGENERIC_SUPPORT
Kever Yangb36e7092019-07-02 11:43:06 +0800137 imply TPL_NEEDS_SEPARATE_STACK
Kever Yangf7c0a332019-07-02 11:43:05 +0800138 imply TPL_OF_CONTROL
139 imply TPL_OF_PLATDATA
140 imply TPL_RAM
141 imply TPL_REGMAP
Kever Yange32f38e2019-07-09 22:05:57 +0800142 imply TPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600143 imply TPL_SERIAL
Kever Yangf7c0a332019-07-02 11:43:05 +0800144 imply TPL_SYSCON
Eddie Caib3501fe2017-12-15 08:17:13 +0800145 imply USB_FUNCTION_ROCKUSB
146 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -0600147 help
148 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
149 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
150 video interfaces supporting HDMI and eDP, several DDR3 options
151 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +0100152 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -0600153
Andy Yanb5e16302019-11-14 11:21:12 +0800154config ROCKCHIP_RK3308
155 bool "Support Rockchip RK3308"
156 select ARM64
Andy Yanb5e16302019-11-14 11:21:12 +0800157 select SUPPORT_SPL
158 select SUPPORT_TPL
159 select SPL
160 select SPL_ATF
161 select SPL_ATF_NO_PLATFORM_PARAM
162 select SPL_LOAD_FIT
Jonas Karlmana2caa162024-04-08 18:14:00 +0000163 imply ARMV8_CRYPTO
164 imply ARMV8_SET_SMPEN
Jonas Karlmanfbced692024-04-08 18:14:02 +0000165 imply DM_RNG
Jonas Karlmana2caa162024-04-08 18:14:00 +0000166 imply LEGACY_IMAGE_FORMAT
Jonas Karlman1cf34dd2024-04-08 18:14:01 +0000167 imply MISC
168 imply MISC_INIT_R
Jonas Karlmanfbced692024-04-08 18:14:02 +0000169 imply RNG_ROCKCHIP
Andy Yanb5e16302019-11-14 11:21:12 +0800170 imply ROCKCHIP_COMMON_BOARD
Jonas Karlman1cf34dd2024-04-08 18:14:01 +0000171 imply ROCKCHIP_OTP
Andy Yanb5e16302019-11-14 11:21:12 +0800172 imply SPL_CLK
Jonas Karlmana499c982024-04-08 18:14:03 +0000173 imply SPL_DM_SEQ_ALIAS
Jonas Karlmana2caa162024-04-08 18:14:00 +0000174 imply SPL_FIT_SIGNATURE
Jonas Karlmana499c982024-04-08 18:14:03 +0000175 imply SPL_PINCTRL
Andy Yanb5e16302019-11-14 11:21:12 +0800176 imply SPL_RAM
Jonas Karlman16b0f902024-04-08 18:13:59 +0000177 imply SPL_REGMAP
178 imply SPL_ROCKCHIP_COMMON_BOARD
Andy Yanb5e16302019-11-14 11:21:12 +0800179 imply SPL_SEPARATE_BSS
Jonas Karlman16b0f902024-04-08 18:13:59 +0000180 imply SPL_SERIAL
181 imply SPL_SYSCON
Andy Yanb5e16302019-11-14 11:21:12 +0800182 help
183 The Rockchip RK3308 is a ARM-based Soc which embedded with quad
184 Cortex-A35 and highly integrated audio interfaces.
185
Kever Yangec02b3c2017-02-23 15:37:51 +0800186config ROCKCHIP_RK3328
187 bool "Support Rockchip RK3328"
188 select ARM64
Kever Yang07be6692019-06-09 00:27:15 +0300189 select SUPPORT_SPL
190 select SPL
Kever Yang69871852019-08-02 10:40:01 +0300191 select SUPPORT_TPL
192 select TPL
Kever Yang69871852019-08-02 10:40:01 +0300193 select TPL_NEEDS_SEPARATE_STACK if TPL
Jonas Karlman1b3d9dd2024-04-21 20:09:02 +0000194 imply ARMV8_CRYPTO
195 imply ARMV8_SET_SMPEN
Jonas Karlman86d4ebb2024-04-21 20:09:01 +0000196 imply MISC
197 imply MISC_INIT_R
Jonas Karlman1b3d9dd2024-04-21 20:09:02 +0000198 imply OF_LIVE
Jagan Tekifb71c882024-01-17 13:21:52 +0530199 imply PRE_CONSOLE_BUFFER
Kever Yang205e2cc2019-07-22 20:02:16 +0800200 imply ROCKCHIP_COMMON_BOARD
Jonas Karlman86d4ebb2024-04-21 20:09:01 +0000201 imply ROCKCHIP_EFUSE
YouMin Chenb9f7df32019-11-15 11:04:44 +0800202 imply ROCKCHIP_SDRAM_COMMON
Kever Yangbb4c3252019-07-22 19:59:32 +0800203 imply SPL_ROCKCHIP_COMMON_BOARD
Jonas Karlman86d4ebb2024-04-21 20:09:01 +0000204 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600205 imply SPL_SERIAL
206 imply TPL_SERIAL
Kever Yangec02b3c2017-02-23 15:37:51 +0800207 help
208 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
209 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
210 video interfaces supporting HDMI and eDP, several DDR3 options
211 and video codec support. Peripherals include Gigabit Ethernet,
212 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
213
Andreas Färber9e3ad682017-05-15 17:51:18 +0800214config ROCKCHIP_RK3368
215 bool "Support Rockchip RK3368"
216 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200217 select SUPPORT_SPL
218 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200219 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang35b401e2019-07-22 20:02:17 +0800220 imply ROCKCHIP_COMMON_BOARD
Kever Yang8bf7ed42019-07-22 19:59:34 +0800221 imply SPL_ROCKCHIP_COMMON_BOARD
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200222 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600223 imply SPL_SERIAL
224 imply TPL_SERIAL
Kever Yang48831b22019-07-09 22:05:58 +0800225 imply TPL_ROCKCHIP_COMMON_BOARD
Andreas Färber9e3ad682017-05-15 17:51:18 +0800226 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200227 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
228 into a big and little cluster with 4 cores each) Cortex-A53 including
229 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
230 (for the little cluster), PowerVR G6110 based graphics, one video
231 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
232 video codec support.
233
234 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
235 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800236
Kever Yang0d3d7832016-07-19 21:16:59 +0800237config ROCKCHIP_RK3399
238 bool "Support Rockchip RK3399"
239 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800240 select SUPPORT_SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800241 select SUPPORT_TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800242 select SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530243 select SPL_ATF
Jagan Tekice063b92019-06-21 00:25:03 +0530244 select SPL_BOARD_INIT if SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530245 select SPL_LOAD_FIT
246 select SPL_CLK if SPL
247 select SPL_PINCTRL if SPL
248 select SPL_RAM if SPL
249 select SPL_REGMAP if SPL
250 select SPL_SYSCON if SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800251 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800252 select SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600253 select SPL_SERIAL
Simon Glass284cb9c2021-07-10 21:14:31 -0600254 select SPL_DRIVERS_MISC
Jagan Tekicd433892019-05-08 11:11:43 +0530255 select CLK
256 select FIT
257 select PINCTRL
258 select RAM
259 select REGMAP
260 select SYSCON
261 select DM_PMIC
262 select DM_REGULATOR_FIXED
Andy Yan70378cb2017-10-11 15:00:16 +0800263 select BOARD_LATE_INIT
Jonas Karlman8b663722024-04-30 15:30:13 +0000264 imply ARMV8_CRYPTO
265 imply ARMV8_SET_SMPEN
Jonas Karlmana6389252024-04-30 15:30:12 +0000266 imply BOOTSTD_FULL
267 imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
Jonas Karlman0ad89712024-04-30 15:30:14 +0000268 imply DM_RNG
Jonas Karlman8b663722024-04-30 15:30:13 +0000269 imply LEGACY_IMAGE_FORMAT
Jonas Karlmana6389252024-04-30 15:30:12 +0000270 imply MISC
271 imply MISC_INIT_R
Jonas Karlman8b663722024-04-30 15:30:13 +0000272 imply OF_LIVE
Sughosh Ganuc1b8e8b2022-11-10 14:49:15 +0530273 imply PARTITION_TYPE_GUID
Jonas Karlman8660d332024-04-30 15:30:15 +0000274 imply PHY_GIGE if GMAC_ROCKCHIP
Jagan Teki9249d5c2020-04-02 17:11:23 +0530275 imply PRE_CONSOLE_BUFFER
Jonas Karlman0ad89712024-04-30 15:30:14 +0000276 imply RNG_ROCKCHIP
Kever Yang9554a4e2019-07-22 20:02:19 +0800277 imply ROCKCHIP_COMMON_BOARD
Jonas Karlmana6389252024-04-30 15:30:12 +0000278 imply ROCKCHIP_EFUSE
YouMin Chen23ae72e2019-11-15 11:04:45 +0800279 imply ROCKCHIP_SDRAM_COMMON
Jonas Karlman8b663722024-04-30 15:30:13 +0000280 imply SPL_FIT_SIGNATURE
Kever Yangff9afe42019-07-22 19:59:42 +0800281 imply SPL_ROCKCHIP_COMMON_BOARD
Jonas Karlmana6389252024-04-30 15:30:12 +0000282 imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
283 imply TPL_CLK
284 imply TPL_DM
285 imply TPL_DRIVERS_MISC
Kever Yangfca798d2018-11-09 11:18:15 +0800286 imply TPL_LIBCOMMON_SUPPORT
287 imply TPL_LIBGENERIC_SUPPORT
Kever Yangfca798d2018-11-09 11:18:15 +0800288 imply TPL_OF_CONTROL
Jonas Karlmana6389252024-04-30 15:30:12 +0000289 imply TPL_RAM
Kever Yangfca798d2018-11-09 11:18:15 +0800290 imply TPL_REGMAP
Jonas Karlmana6389252024-04-30 15:30:12 +0000291 imply TPL_ROCKCHIP_COMMON_BOARD
292 imply TPL_SERIAL
293 imply TPL_SYS_MALLOC_SIMPLE
Kever Yangfca798d2018-11-09 11:18:15 +0800294 imply TPL_SYSCON
Kever Yangfca798d2018-11-09 11:18:15 +0800295 imply TPL_TINY_MEMSET
Kever Yang0d3d7832016-07-19 21:16:59 +0800296 help
297 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
298 and quad-core Cortex-A53.
299 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
300 video interfaces supporting HDMI and eDP, several DDR3 options
301 and video codec support. Peripherals include Gigabit Ethernet,
302 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
303
Joseph Chen72cd8792021-06-02 15:58:25 +0800304config ROCKCHIP_RK3568
305 bool "Support Rockchip RK3568"
306 select ARM64
Nico Cheng00ceeb02021-10-26 10:42:19 +0800307 select SUPPORT_SPL
308 select SPL
Joseph Chen72cd8792021-06-02 15:58:25 +0800309 select CLK
310 select PINCTRL
311 select RAM
312 select REGMAP
313 select SYSCON
314 select BOARD_LATE_INIT
Manoj Saib34b19c2023-02-17 17:28:44 +0530315 select DM_REGULATOR_FIXED
Jagan Tekice0bbac2023-02-17 17:28:34 +0530316 select DM_RESET
Jonas Karlmanc1bb7122024-04-22 06:28:47 +0000317 imply BOOTSTD_FULL
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000318 imply DM_RNG
Jonas Karlmanbe56bb52023-02-22 22:44:41 +0000319 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000320 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000321 imply OF_LIBFDT_OVERLAY
Jonas Karlmane8b5bae2024-04-22 06:28:46 +0000322 imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000323 imply RNG_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000324 imply ROCKCHIP_COMMON_BOARD
325 imply ROCKCHIP_OTP
326 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000327 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Joseph Chen72cd8792021-06-02 15:58:25 +0800328 help
329 The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
330 including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
331 two video interfaces supporting HDMI and eDP, several DDR3 options
332 and video codec support. Peripherals include Gigabit Ethernet,
333 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
334
Jagan Teki8967dea2023-01-30 20:27:45 +0530335config ROCKCHIP_RK3588
336 bool "Support Rockchip RK3588"
337 select ARM64
338 select SUPPORT_SPL
339 select SPL
340 select CLK
341 select PINCTRL
342 select RAM
343 select REGMAP
344 select SYSCON
345 select BOARD_LATE_INIT
Jonas Karlman9bfd6512023-05-17 18:26:37 +0000346 select DM_REGULATOR_FIXED
347 select DM_RESET
Jonas Karlman0eb24592024-04-22 06:28:44 +0000348 imply BOOTSTD_FULL
349 imply CLK_SCMI
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000350 imply DM_RNG
Jonas Karlmaneeb19172023-02-22 22:44:41 +0000351 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000352 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000353 imply OF_LIBFDT_OVERLAY
Jonas Karlmane8b5bae2024-04-22 06:28:46 +0000354 imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000355 imply RNG_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000356 imply ROCKCHIP_COMMON_BOARD
357 imply ROCKCHIP_OTP
Jonas Karlmanfc805c22023-04-17 19:07:21 +0000358 imply SCMI_FIRMWARE
Jonas Karlman0eb24592024-04-22 06:28:44 +0000359 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
360 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Jagan Teki8967dea2023-01-30 20:27:45 +0530361 help
362 The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
363 quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
364 HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1,
365 SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet,
366 SDIO3.0 I2C, UART, SPI, GPIO and PWM.
367
Andy Yan2d982da2017-06-01 18:00:55 +0800368config ROCKCHIP_RV1108
369 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530370 select CPU_V7A
Kever Yanga2b336e2019-07-22 20:02:21 +0800371 imply ROCKCHIP_COMMON_BOARD
Andy Yan2d982da2017-06-01 18:00:55 +0800372 help
373 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
374 and a DSP.
375
Jagan Teki249a2382022-12-14 23:21:05 +0530376config ROCKCHIP_RV1126
377 bool "Support Rockchip RV1126"
378 select CPU_V7A
379 select SKIP_LOWLEVEL_INIT_ONLY
380 select TPL
381 select SUPPORT_TPL
382 select TPL_NEEDS_SEPARATE_STACK
383 select TPL_ROCKCHIP_BACK_TO_BROM
384 select SPL
385 select SUPPORT_SPL
386 select SPL_STACK_R
387 select CLK
388 select FIT
389 select PINCTRL
390 select RAM
391 select ROCKCHIP_SDRAM_COMMON
392 select REGMAP
393 select SYSCON
394 select DM_PMIC
395 select DM_REGULATOR_FIXED
396 select DM_RESET
397 select REGULATOR_RK8XX
398 select PMIC_RK8XX
399 select BOARD_LATE_INIT
400 imply ROCKCHIP_COMMON_BOARD
Tim Lunnd0812b22024-01-24 14:26:01 +1100401 select SPL_OPTEE_IMAGE if SPL_FIT
Jagan Tekid679f622023-07-29 19:11:42 +0530402 imply OF_LIBFDT_OVERLAY
Tim Lunncbfee492023-10-31 13:07:15 +1100403 imply ROCKCHIP_OTP
404 imply MISC_INIT_R
Jagan Teki249a2382022-12-14 23:21:05 +0530405 imply TPL_DM
406 imply TPL_LIBCOMMON_SUPPORT
407 imply TPL_LIBGENERIC_SUPPORT
408 imply TPL_OF_CONTROL
409 imply TPL_OF_PLATDATA
410 imply TPL_RAM
411 imply TPL_ROCKCHIP_COMMON_BOARD
412 imply TPL_SERIAL
413 imply SPL_CLK
414 imply SPL_DM
415 imply SPL_DRIVERS_MISC
416 imply SPL_LIBCOMMON_SUPPORT
417 imply SPL_LIBGENERIC_SUPPORT
418 imply SPL_OF_CONTROL
419 imply SPL_RAM
420 imply SPL_REGMAP
421 imply SPL_ROCKCHIP_COMMON_BOARD
422 imply SPL_SERIAL
423 imply SPL_SYSCON
424
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200425config ROCKCHIP_USB_UART
426 bool "Route uart output to usb pins"
427 help
428 Rockchip SoCs have the ability to route the signals of the debug
429 uart through the d+ and d- pins of a specific usb phy to enable
430 some form of closed-case debugging. With this option supported
431 SoCs will enable this routing as a debug measure.
432
Philipp Tomsich798370f2017-06-29 11:21:15 +0200433config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800434 bool "SPL returns to bootrom"
435 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100436 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800437 select SPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200438 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800439 help
440 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
441 SPL will return to the boot rom, which will then load the U-Boot
442 binary to keep going on.
443
Philipp Tomsich798370f2017-06-29 11:21:15 +0200444config TPL_ROCKCHIP_BACK_TO_BROM
445 bool "TPL returns to bootrom"
Kever Yangfca798d2018-11-09 11:18:15 +0800446 default y
Johan Jonkera768ff52023-10-27 20:35:37 +0200447 select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066
Kever Yangbd8532e2019-07-22 19:59:15 +0800448 select TPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200449 depends on TPL
450 help
451 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
452 SPL will return to the boot rom, which will then load the U-Boot
453 binary to keep going on.
454
Kever Yangbb337732019-07-22 20:02:01 +0800455config ROCKCHIP_COMMON_BOARD
456 bool "Rockchip common board file"
457 help
458 Rockchip SoCs have similar boot process, Common board file is mainly
459 in charge of common process of board_init() and board_late_init() for
460 U-Boot proper.
461
Kever Yang1d7cc72a2019-07-22 19:59:12 +0800462config SPL_ROCKCHIP_COMMON_BOARD
463 bool "Rockchip SPL common board file"
464 depends on SPL
465 help
466 Rockchip SoCs have similar boot process, SPL is mainly in charge of
467 load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
468 no TPL for the board.
469
Kever Yang34ead0f2019-07-09 22:05:55 +0800470config TPL_ROCKCHIP_COMMON_BOARD
Thomas Hebbcfbebf82019-12-20 18:05:22 -0800471 bool "Rockchip TPL common board file"
Kever Yang34ead0f2019-07-09 22:05:55 +0800472 depends on TPL
473 help
474 Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
475 init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
476 common board is a basic TPL board init which can be shared for most
Thomas Hebbfd37f242019-11-13 18:18:03 -0800477 of SoCs to avoid copy-paste for different SoCs.
Kever Yang34ead0f2019-07-09 22:05:55 +0800478
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000479config ROCKCHIP_EXTERNAL_TPL
480 bool "Use external TPL binary"
Massimo Pegorer8c20dfa2023-09-09 11:33:24 +0200481 default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000482 help
483 Some Rockchip SoCs require an external TPL to initialize DRAM.
484 Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
485 include the external TPL in the image built by binman.
486
Andy Yan70378cb2017-10-11 15:00:16 +0800487config ROCKCHIP_BOOT_MODE_REG
488 hex "Rockchip boot mode flag register address"
Andy Yan70378cb2017-10-11 15:00:16 +0800489 help
Kever Yang9fbe17c2019-03-28 11:01:23 +0800490 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yan70378cb2017-10-11 15:00:16 +0800491 according to the value from this register.
492
Chris Morgan7c9de742022-05-27 13:18:20 -0500493config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON
494 bool "Disable device boot on power plug-in"
495 depends on PMIC_RK8XX
Chris Morgan7c9de742022-05-27 13:18:20 -0500496 ---help---
497 Say Y here to prevent the device from booting up because of a plug-in
498 event. When set, the device will boot briefly to determine why it was
499 powered on, and if it was determined because of a plug-in event
500 instead of a button press event it will shut back off.
501
Johan Jonkerf6fc8952022-04-09 18:55:02 +0200502config ROCKCHIP_STIMER
503 bool "Rockchip STIMER support"
504 default y
505 help
506 Enable Rockchip STIMER support.
507
508config ROCKCHIP_STIMER_BASE
509 hex
510 depends on ROCKCHIP_STIMER
511
Kever Yange484f772017-04-20 17:03:46 +0800512config ROCKCHIP_SPL_RESERVE_IRAM
513 hex "Size of IRAM reserved in SPL"
Tom Rinif18679c2023-08-02 11:09:43 -0400514 default 0x0
Kever Yange484f772017-04-20 17:03:46 +0800515 help
516 SPL may need reserve memory for firmware loaded by SPL, whose load
517 address is in IRAM and may overlay with SPL text area if not
518 reserved.
519
Heiko Stübner355a8802017-02-18 19:46:25 +0100520config ROCKCHIP_BROM_HELPER
521 bool
522
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200523config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
524 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
525 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
526 help
527 Some Rockchip BROM variants (e.g. on the RK3188) load the
528 first stage in segments and enter multiple times. E.g. on
529 the RK3188, the first 1KB of the first stage are loaded
530 first and entered; after returning to the BROM, the
531 remainder of the first stage is loaded, but the BROM
532 re-enters at the same address/to the same code as previously.
533
534 This enables support code in the BOOT0 hook for the SPL stage
535 to allow multiple entries.
536
Quentin Schulz95b568f2024-03-11 13:01:54 +0100537config ROCKCHIP_DISABLE_FORCE_JTAG
538 bool "Disable force_jtag feature"
539 default y
540 depends on SPL
541 help
542 Rockchip SoCs can automatically switch between jtag and sdmmc based
543 on the following rules:
544 - all the SDMMC pins including SDMMC_DET set as SDMMC function in
545 GRF,
546 - force_jtag bit in GRF is 1,
547 - SDMMC_DET is low (no card detected),
548
549 Some HW design may not route the SD card card detect to SDMMC_DET
550 pin, thus breaking the SD card support in some cases because JTAG
551 would be auto-enabled by mistake.
552
553 Also, enabling JTAG at runtime may be an undesired feature, e.g.
554 because it could be a security vulnerability.
555
556 This disables force_jtag feature, which you may want for debugging
557 purposes.
558
559 If unsure, say Y.
560
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200561config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
562 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
563 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
564 help
565 Some Rockchip BROM variants (e.g. on the RK3188) load the
566 first stage in segments and enter multiple times. E.g. on
567 the RK3188, the first 1KB of the first stage are loaded
568 first and entered; after returning to the BROM, the
569 remainder of the first stage is loaded, but the BROM
570 re-enters at the same address/to the same code as previously.
571
572 This enables support code in the BOOT0 hook for the TPL stage
573 to allow multiple entries.
574
Simon Glassb58bfe02021-08-08 12:20:09 -0600575config SPL_MMC
Philipp Tomsich798370f2017-06-29 11:21:15 +0200576 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400577
Simon Glass88315f72020-07-19 13:55:57 -0600578config ROCKCHIP_SPI_IMAGE
579 bool "Build a SPI image for rockchip"
Simon Glass88315f72020-07-19 13:55:57 -0600580 help
581 Some Rockchip SoCs support booting from SPI flash. Enable this
Quentin Schulz12df9cf2022-09-02 15:10:54 +0200582 option to produce a SPI-flash image containing U-Boot. The image
583 is built by binman. U-Boot sits near the start of the image.
Simon Glass88315f72020-07-19 13:55:57 -0600584
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300585config LNX_KRNL_IMG_TEXT_OFFSET_BASE
Simon Glass72cc5382022-10-20 18:22:39 -0600586 default TEXT_BASE
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300587
Jonas Karlmane4453632024-03-02 19:16:11 +0000588config ROCKCHIP_COMMON_STACK_ADDR
589 bool
590 depends on SPL_SHARES_INIT_SP_ADDR
591 select HAS_CUSTOM_SYS_INIT_SP_ADDR
592 imply SPL_LIBCOMMON_SUPPORT if SPL
593 imply SPL_LIBGENERIC_SUPPORT if SPL
594 imply SPL_ROCKCHIP_COMMON_BOARD if SPL
595 imply SPL_SYS_MALLOC_F if SPL
596 imply SPL_SYS_MALLOC_SIMPLE if SPL
597 imply TPL_LIBCOMMON_SUPPORT if TPL
598 imply TPL_LIBGENERIC_SUPPORT if TPL
599 imply TPL_ROCKCHIP_COMMON_BOARD if TPL
600 imply TPL_SYS_MALLOC_F if TPL
601 imply TPL_SYS_MALLOC_SIMPLE if TPL
602
Quentin Schulzfb2d1ec2024-04-25 12:46:25 +0200603config NR_DRAM_BANKS
604 default 10 if ROCKCHIP_EXTERNAL_TPL
605
Heiko Stuebnerfc367852019-07-16 22:18:21 +0200606source "arch/arm/mach-rockchip/px30/Kconfig"
huang lin1115b642015-11-17 14:20:27 +0800607source "arch/arm/mach-rockchip/rk3036/Kconfig"
Johan Jonkera289fc72022-04-16 17:09:47 +0200608source "arch/arm/mach-rockchip/rk3066/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800609source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100610source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800611source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200612source "arch/arm/mach-rockchip/rk3288/Kconfig"
Andy Yanb5e16302019-11-14 11:21:12 +0800613source "arch/arm/mach-rockchip/rk3308/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800614source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800615source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800616source "arch/arm/mach-rockchip/rk3399/Kconfig"
Joseph Chen16899892021-06-02 16:13:46 +0800617source "arch/arm/mach-rockchip/rk3568/Kconfig"
Jagan Teki8967dea2023-01-30 20:27:45 +0530618source "arch/arm/mach-rockchip/rk3588/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800619source "arch/arm/mach-rockchip/rv1108/Kconfig"
Jagan Teki249a2382022-12-14 23:21:05 +0530620source "arch/arm/mach-rockchip/rv1126/Kconfig"
Jonas Karlmane4453632024-03-02 19:16:11 +0000621
622if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR
623
624config CUSTOM_SYS_INIT_SP_ADDR
625 default 0x3f00000
626
627config SYS_MALLOC_F_LEN
628 default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
629
630config SPL_SYS_MALLOC_F_LEN
631 default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
632
633config TPL_SYS_MALLOC_F_LEN
634 default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
635
636config TEXT_BASE
637 default 0x00200000 if ARM64
638
639config SPL_TEXT_BASE
640 default 0x0 if ARM64
641
642config SPL_HAS_BSS_LINKER_SECTION
643 default y if ARM64
644
645config SPL_BSS_START_ADDR
646 default 0x3f80000
647
648config SPL_BSS_MAX_SIZE
649 default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000
650
651config SPL_STACK_R
652 default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
653
654config SPL_STACK_R_ADDR
655 default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
656
657config SPL_STACK_R_MALLOC_SIMPLE_LEN
658 default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000
659
660endif
Simon Glass2cffe662015-08-30 16:55:38 -0600661endif