blob: 0902eb285453536172485f3e3c2a878595036587 [file] [log] [blame]
Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stuebnerfc367852019-07-16 22:18:21 +02003config ROCKCHIP_PX30
4 bool "Support Rockchip PX30"
5 select ARM64
6 select SUPPORT_SPL
7 select SUPPORT_TPL
8 select SPL
9 select TPL
10 select TPL_TINY_FRAMEWORK if TPL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020011 select TPL_NEEDS_SEPARATE_STACK if TPL
12 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -060013 select SPL_SERIAL
14 select TPL_SERIAL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020015 select DEBUG_UART_BOARD_INIT
16 imply ROCKCHIP_COMMON_BOARD
17 imply SPL_ROCKCHIP_COMMON_BOARD
18 help
19 The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
20 including NEON and GPU, Mali-400 graphics, several DDR3 options
21 and video codec support. Peripherals include Gigabit Ethernet,
22 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
23
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020024config ROCKCHIP_RK3036
25 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053026 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +080027 select SUPPORT_SPL
28 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +080029 imply USB_FUNCTION_ROCKUSB
30 imply CMD_ROCKUSB
Kever Yang427cb672019-07-22 20:02:04 +080031 imply ROCKCHIP_COMMON_BOARD
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020032 help
33 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
34 including NEON and GPU, Mali-400 graphics, several DDR3 options
35 and video codec support. Peripherals include Gigabit Ethernet,
36 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
37
Johan Jonkera289fc72022-04-16 17:09:47 +020038config ROCKCHIP_RK3066
39 bool "Support Rockchip RK3066"
40 select CPU_V7A
41 select SPL_BOARD_INIT if SPL
42 select SUPPORT_SPL
43 select SUPPORT_TPL
44 select SPL
45 select TPL
46 select TPL_ROCKCHIP_BACK_TO_BROM
47 select TPL_ROCKCHIP_EARLYRETURN_TO_BROM
48 imply ROCKCHIP_COMMON_BOARD
49 imply SPL_ROCKCHIP_COMMON_BOARD
50 imply SPL_SERIAL
51 imply TPL_ROCKCHIP_COMMON_BOARD
52 imply TPL_SERIAL
53 help
54 The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
55 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
56 video interfaces, several memory options and video codec support.
57 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
58 UART, SPI, I2C and PWMs.
59
Kever Yangaa827752017-11-28 16:04:16 +080060config ROCKCHIP_RK3128
61 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053062 select CPU_V7A
Kever Yang96362722019-07-22 20:02:05 +080063 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa827752017-11-28 16:04:16 +080064 help
65 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
66 including NEON and GPU, Mali-400 graphics, several DDR3 options
67 and video codec support. Peripherals include Gigabit Ethernet,
68 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
69
Heiko Stübneref6db5e2017-02-18 19:46:36 +010070config ROCKCHIP_RK3188
71 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053072 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080073 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010074 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010075 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020076 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020077 select SPL_REGMAP
78 select SPL_SYSCON
79 select SPL_RAM
Simon Glass284cb9c2021-07-10 21:14:31 -060080 select SPL_DRIVERS_MISC
Philipp Tomsich16c689c2017-10-10 16:21:15 +020081 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangbd8532e2019-07-22 19:59:15 +080082 select SPL_ROCKCHIP_BACK_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020083 select BOARD_LATE_INIT
Kever Yangbfd3f872019-07-22 20:02:09 +080084 imply ROCKCHIP_COMMON_BOARD
Kever Yang3bd90402019-07-22 19:59:18 +080085 imply SPL_ROCKCHIP_COMMON_BOARD
Heiko Stübneref6db5e2017-02-18 19:46:36 +010086 help
87 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
88 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
89 video interfaces, several memory options and video codec support.
90 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
91 UART, SPI, I2C and PWMs.
92
Kever Yang57d4dbf2017-06-23 17:17:52 +080093config ROCKCHIP_RK322X
94 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053095 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080096 select SUPPORT_SPL
Kever Yangaff40c62019-04-02 20:41:24 +080097 select SUPPORT_TPL
Kever Yang57d4dbf2017-06-23 17:17:52 +080098 select SPL
Kever Yangaff40c62019-04-02 20:41:24 +080099 select SPL_DM
100 select SPL_OF_LIBFDT
101 select TPL
102 select TPL_DM
103 select TPL_OF_LIBFDT
Kever Yangaff40c62019-04-02 20:41:24 +0800104 select TPL_NEEDS_SEPARATE_STACK if TPL
Simon Glass284cb9c2021-07-10 21:14:31 -0600105 select SPL_DRIVERS_MISC
Kever Yang0b517732019-07-22 20:02:07 +0800106 imply ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600107 imply SPL_SERIAL
Kever Yangd877fd22019-07-22 19:59:20 +0800108 imply SPL_ROCKCHIP_COMMON_BOARD
Alex Bee4fe31122023-07-18 16:57:13 +0200109 select SPL_OPTEE_IMAGE if SPL_FIT
Simon Glassf4d60392021-08-08 12:20:12 -0600110 imply TPL_SERIAL
Kever Yang466f3fd2019-07-09 22:05:56 +0800111 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +0800112 select TPL_LIBCOMMON_SUPPORT
113 select TPL_LIBGENERIC_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +0800114 help
115 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
116 including NEON and GPU, Mali-400 graphics, several DDR3 options
117 and video codec support. Peripherals include Gigabit Ethernet,
118 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
119
Simon Glass2cffe662015-08-30 16:55:38 -0600120config ROCKCHIP_RK3288
121 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530122 select CPU_V7A
John Keepingd5cb7712023-02-23 19:28:51 +0000123 select OF_SYSTEM_SETUP
Tom Rinie1e85442021-08-27 21:18:30 -0400124 select SKIP_LOWLEVEL_INIT_ONLY
Kever Yang0d3d7832016-07-19 21:16:59 +0800125 select SUPPORT_SPL
126 select SPL
Kever Yangf7c0a332019-07-02 11:43:05 +0800127 select SUPPORT_TPL
Johan Jonker9a26fb12023-12-27 13:06:47 +0100128 select FDT_64BIT
Jagan Teki7b7cc952020-01-23 19:42:19 +0530129 imply PRE_CONSOLE_BUFFER
Kever Yangba875012019-07-22 20:02:15 +0800130 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa67deb2019-07-22 19:59:27 +0800131 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +0800132 imply TPL_CLK
133 imply TPL_DM
Simon Glass284cb9c2021-07-10 21:14:31 -0600134 imply TPL_DRIVERS_MISC
Kever Yangf7c0a332019-07-02 11:43:05 +0800135 imply TPL_LIBCOMMON_SUPPORT
136 imply TPL_LIBGENERIC_SUPPORT
Kever Yangb36e7092019-07-02 11:43:06 +0800137 imply TPL_NEEDS_SEPARATE_STACK
Kever Yangf7c0a332019-07-02 11:43:05 +0800138 imply TPL_OF_CONTROL
139 imply TPL_OF_PLATDATA
140 imply TPL_RAM
141 imply TPL_REGMAP
Kever Yange32f38e2019-07-09 22:05:57 +0800142 imply TPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600143 imply TPL_SERIAL
Kever Yangf7c0a332019-07-02 11:43:05 +0800144 imply TPL_SYSCON
Eddie Caib3501fe2017-12-15 08:17:13 +0800145 imply USB_FUNCTION_ROCKUSB
146 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -0600147 help
148 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
149 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
150 video interfaces supporting HDMI and eDP, several DDR3 options
151 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +0100152 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -0600153
Andy Yanb5e16302019-11-14 11:21:12 +0800154config ROCKCHIP_RK3308
155 bool "Support Rockchip RK3308"
156 select ARM64
Andy Yanb5e16302019-11-14 11:21:12 +0800157 select SUPPORT_SPL
158 select SUPPORT_TPL
159 select SPL
160 select SPL_ATF
161 select SPL_ATF_NO_PLATFORM_PARAM
162 select SPL_LOAD_FIT
Jonas Karlmana2caa162024-04-08 18:14:00 +0000163 imply ARMV8_CRYPTO
164 imply ARMV8_SET_SMPEN
165 imply LEGACY_IMAGE_FORMAT
Andy Yanb5e16302019-11-14 11:21:12 +0800166 imply ROCKCHIP_COMMON_BOARD
Andy Yanb5e16302019-11-14 11:21:12 +0800167 imply SPL_CLK
Jonas Karlmana2caa162024-04-08 18:14:00 +0000168 imply SPL_FIT_SIGNATURE
Andy Yanb5e16302019-11-14 11:21:12 +0800169 imply SPL_RAM
Jonas Karlman16b0f902024-04-08 18:13:59 +0000170 imply SPL_REGMAP
171 imply SPL_ROCKCHIP_COMMON_BOARD
Andy Yanb5e16302019-11-14 11:21:12 +0800172 imply SPL_SEPARATE_BSS
Jonas Karlman16b0f902024-04-08 18:13:59 +0000173 imply SPL_SERIAL
174 imply SPL_SYSCON
Andy Yanb5e16302019-11-14 11:21:12 +0800175 help
176 The Rockchip RK3308 is a ARM-based Soc which embedded with quad
177 Cortex-A35 and highly integrated audio interfaces.
178
Kever Yangec02b3c2017-02-23 15:37:51 +0800179config ROCKCHIP_RK3328
180 bool "Support Rockchip RK3328"
181 select ARM64
Kever Yang07be6692019-06-09 00:27:15 +0300182 select SUPPORT_SPL
183 select SPL
Kever Yang69871852019-08-02 10:40:01 +0300184 select SUPPORT_TPL
185 select TPL
Kever Yang69871852019-08-02 10:40:01 +0300186 select TPL_NEEDS_SEPARATE_STACK if TPL
Jagan Tekifb71c882024-01-17 13:21:52 +0530187 imply PRE_CONSOLE_BUFFER
Kever Yang205e2cc2019-07-22 20:02:16 +0800188 imply ROCKCHIP_COMMON_BOARD
YouMin Chenb9f7df32019-11-15 11:04:44 +0800189 imply ROCKCHIP_SDRAM_COMMON
Kever Yangbb4c3252019-07-22 19:59:32 +0800190 imply SPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600191 imply SPL_SERIAL
192 imply TPL_SERIAL
Kever Yang07be6692019-06-09 00:27:15 +0300193 imply SPL_SEPARATE_BSS
194 select ENABLE_ARM_SOC_BOOT0_HOOK
195 select DEBUG_UART_BOARD_INIT
196 select SYS_NS16550
Chen-Yu Tsaibc261472024-02-12 21:51:04 +0800197 imply MISC
198 imply ROCKCHIP_EFUSE
199 imply MISC_INIT_R
Kever Yangec02b3c2017-02-23 15:37:51 +0800200 help
201 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
202 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
203 video interfaces supporting HDMI and eDP, several DDR3 options
204 and video codec support. Peripherals include Gigabit Ethernet,
205 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
206
Andreas Färber9e3ad682017-05-15 17:51:18 +0800207config ROCKCHIP_RK3368
208 bool "Support Rockchip RK3368"
209 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200210 select SUPPORT_SPL
211 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200212 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang35b401e2019-07-22 20:02:17 +0800213 imply ROCKCHIP_COMMON_BOARD
Kever Yang8bf7ed42019-07-22 19:59:34 +0800214 imply SPL_ROCKCHIP_COMMON_BOARD
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200215 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600216 imply SPL_SERIAL
217 imply TPL_SERIAL
Kever Yang48831b22019-07-09 22:05:58 +0800218 imply TPL_ROCKCHIP_COMMON_BOARD
Andreas Färber9e3ad682017-05-15 17:51:18 +0800219 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200220 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
221 into a big and little cluster with 4 cores each) Cortex-A53 including
222 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
223 (for the little cluster), PowerVR G6110 based graphics, one video
224 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
225 video codec support.
226
227 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
228 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800229
Kever Yang0d3d7832016-07-19 21:16:59 +0800230config ROCKCHIP_RK3399
231 bool "Support Rockchip RK3399"
232 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800233 select SUPPORT_SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800234 select SUPPORT_TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800235 select SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530236 select SPL_ATF
Jagan Tekice063b92019-06-21 00:25:03 +0530237 select SPL_BOARD_INIT if SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530238 select SPL_LOAD_FIT
239 select SPL_CLK if SPL
240 select SPL_PINCTRL if SPL
241 select SPL_RAM if SPL
242 select SPL_REGMAP if SPL
243 select SPL_SYSCON if SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800244 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800245 select SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600246 select SPL_SERIAL
Simon Glass284cb9c2021-07-10 21:14:31 -0600247 select SPL_DRIVERS_MISC
Jagan Tekicd433892019-05-08 11:11:43 +0530248 select CLK
249 select FIT
250 select PINCTRL
251 select RAM
252 select REGMAP
253 select SYSCON
254 select DM_PMIC
255 select DM_REGULATOR_FIXED
Andy Yan70378cb2017-10-11 15:00:16 +0800256 select BOARD_LATE_INIT
Sughosh Ganuc1b8e8b2022-11-10 14:49:15 +0530257 imply PARTITION_TYPE_GUID
Jagan Teki9249d5c2020-04-02 17:11:23 +0530258 imply PRE_CONSOLE_BUFFER
Kever Yang9554a4e2019-07-22 20:02:19 +0800259 imply ROCKCHIP_COMMON_BOARD
YouMin Chen23ae72e2019-11-15 11:04:45 +0800260 imply ROCKCHIP_SDRAM_COMMON
Kever Yangff9afe42019-07-22 19:59:42 +0800261 imply SPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600262 imply TPL_SERIAL
Kever Yangfca798d2018-11-09 11:18:15 +0800263 imply TPL_LIBCOMMON_SUPPORT
264 imply TPL_LIBGENERIC_SUPPORT
265 imply TPL_SYS_MALLOC_SIMPLE
Simon Glass284cb9c2021-07-10 21:14:31 -0600266 imply TPL_DRIVERS_MISC
Kever Yangfca798d2018-11-09 11:18:15 +0800267 imply TPL_OF_CONTROL
268 imply TPL_DM
269 imply TPL_REGMAP
270 imply TPL_SYSCON
271 imply TPL_RAM
272 imply TPL_CLK
273 imply TPL_TINY_MEMSET
Kever Yang3cfbb942019-07-09 22:06:01 +0800274 imply TPL_ROCKCHIP_COMMON_BOARD
Jagan Tekie7043012020-01-09 14:22:19 +0530275 imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
Shantur Rathorec0009892024-01-21 22:04:47 +0000276 imply BOOTSTD_FULL
Jagan Tekie7043012020-01-09 14:22:19 +0530277 imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
Chen-Yu Tsai3ccaa1d2024-02-12 21:51:05 +0800278 imply MISC
279 imply ROCKCHIP_EFUSE
280 imply MISC_INIT_R
Kever Yang0d3d7832016-07-19 21:16:59 +0800281 help
282 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
283 and quad-core Cortex-A53.
284 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
285 video interfaces supporting HDMI and eDP, several DDR3 options
286 and video codec support. Peripherals include Gigabit Ethernet,
287 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
288
Joseph Chen72cd8792021-06-02 15:58:25 +0800289config ROCKCHIP_RK3568
290 bool "Support Rockchip RK3568"
291 select ARM64
Nico Cheng00ceeb02021-10-26 10:42:19 +0800292 select SUPPORT_SPL
293 select SPL
Joseph Chen72cd8792021-06-02 15:58:25 +0800294 select CLK
295 select PINCTRL
296 select RAM
297 select REGMAP
298 select SYSCON
299 select BOARD_LATE_INIT
Manoj Saib34b19c2023-02-17 17:28:44 +0530300 select DM_REGULATOR_FIXED
Jagan Tekice0bbac2023-02-17 17:28:34 +0530301 select DM_RESET
Jonas Karlman47af53c2023-04-17 19:07:15 +0000302 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Joseph Chen72cd8792021-06-02 15:58:25 +0800303 imply ROCKCHIP_COMMON_BOARD
Jonas Karlmanf4d27e92023-04-17 19:07:17 +0000304 imply OF_LIBFDT_OVERLAY
Jonas Karlmanbe56bb52023-02-22 22:44:41 +0000305 imply ROCKCHIP_OTP
306 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000307 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
308 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Joseph Chen72cd8792021-06-02 15:58:25 +0800309 help
310 The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
311 including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
312 two video interfaces supporting HDMI and eDP, several DDR3 options
313 and video codec support. Peripherals include Gigabit Ethernet,
314 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
315
Jagan Teki8967dea2023-01-30 20:27:45 +0530316config ROCKCHIP_RK3588
317 bool "Support Rockchip RK3588"
318 select ARM64
319 select SUPPORT_SPL
320 select SPL
321 select CLK
322 select PINCTRL
323 select RAM
324 select REGMAP
325 select SYSCON
326 select BOARD_LATE_INIT
Jonas Karlman9bfd6512023-05-17 18:26:37 +0000327 select DM_REGULATOR_FIXED
328 select DM_RESET
Jonas Karlman47af53c2023-04-17 19:07:15 +0000329 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Jagan Teki8967dea2023-01-30 20:27:45 +0530330 imply ROCKCHIP_COMMON_BOARD
Jonas Karlmanf4d27e92023-04-17 19:07:17 +0000331 imply OF_LIBFDT_OVERLAY
Jonas Karlmaneeb19172023-02-22 22:44:41 +0000332 imply ROCKCHIP_OTP
333 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000334 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
335 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Jonas Karlmanfc805c22023-04-17 19:07:21 +0000336 imply CLK_SCMI
337 imply SCMI_FIRMWARE
Shantur Rathorec0009892024-01-21 22:04:47 +0000338 imply BOOTSTD_FULL
Jagan Teki8967dea2023-01-30 20:27:45 +0530339 help
340 The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
341 quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
342 HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1,
343 SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet,
344 SDIO3.0 I2C, UART, SPI, GPIO and PWM.
345
Andy Yan2d982da2017-06-01 18:00:55 +0800346config ROCKCHIP_RV1108
347 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530348 select CPU_V7A
Kever Yanga2b336e2019-07-22 20:02:21 +0800349 imply ROCKCHIP_COMMON_BOARD
Andy Yan2d982da2017-06-01 18:00:55 +0800350 help
351 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
352 and a DSP.
353
Jagan Teki249a2382022-12-14 23:21:05 +0530354config ROCKCHIP_RV1126
355 bool "Support Rockchip RV1126"
356 select CPU_V7A
357 select SKIP_LOWLEVEL_INIT_ONLY
358 select TPL
359 select SUPPORT_TPL
360 select TPL_NEEDS_SEPARATE_STACK
361 select TPL_ROCKCHIP_BACK_TO_BROM
362 select SPL
363 select SUPPORT_SPL
364 select SPL_STACK_R
365 select CLK
366 select FIT
367 select PINCTRL
368 select RAM
369 select ROCKCHIP_SDRAM_COMMON
370 select REGMAP
371 select SYSCON
372 select DM_PMIC
373 select DM_REGULATOR_FIXED
374 select DM_RESET
375 select REGULATOR_RK8XX
376 select PMIC_RK8XX
377 select BOARD_LATE_INIT
378 imply ROCKCHIP_COMMON_BOARD
Tim Lunnd0812b22024-01-24 14:26:01 +1100379 select SPL_OPTEE_IMAGE if SPL_FIT
Jagan Tekid679f622023-07-29 19:11:42 +0530380 imply OF_LIBFDT_OVERLAY
Tim Lunncbfee492023-10-31 13:07:15 +1100381 imply ROCKCHIP_OTP
382 imply MISC_INIT_R
Jagan Teki249a2382022-12-14 23:21:05 +0530383 imply TPL_DM
384 imply TPL_LIBCOMMON_SUPPORT
385 imply TPL_LIBGENERIC_SUPPORT
386 imply TPL_OF_CONTROL
387 imply TPL_OF_PLATDATA
388 imply TPL_RAM
389 imply TPL_ROCKCHIP_COMMON_BOARD
390 imply TPL_SERIAL
391 imply SPL_CLK
392 imply SPL_DM
393 imply SPL_DRIVERS_MISC
394 imply SPL_LIBCOMMON_SUPPORT
395 imply SPL_LIBGENERIC_SUPPORT
396 imply SPL_OF_CONTROL
397 imply SPL_RAM
398 imply SPL_REGMAP
399 imply SPL_ROCKCHIP_COMMON_BOARD
400 imply SPL_SERIAL
401 imply SPL_SYSCON
402
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200403config ROCKCHIP_USB_UART
404 bool "Route uart output to usb pins"
405 help
406 Rockchip SoCs have the ability to route the signals of the debug
407 uart through the d+ and d- pins of a specific usb phy to enable
408 some form of closed-case debugging. With this option supported
409 SoCs will enable this routing as a debug measure.
410
Philipp Tomsich798370f2017-06-29 11:21:15 +0200411config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800412 bool "SPL returns to bootrom"
413 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100414 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800415 select SPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200416 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800417 help
418 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
419 SPL will return to the boot rom, which will then load the U-Boot
420 binary to keep going on.
421
Philipp Tomsich798370f2017-06-29 11:21:15 +0200422config TPL_ROCKCHIP_BACK_TO_BROM
423 bool "TPL returns to bootrom"
Kever Yangfca798d2018-11-09 11:18:15 +0800424 default y
Johan Jonkera768ff52023-10-27 20:35:37 +0200425 select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066
Kever Yangbd8532e2019-07-22 19:59:15 +0800426 select TPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200427 depends on TPL
428 help
429 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
430 SPL will return to the boot rom, which will then load the U-Boot
431 binary to keep going on.
432
Kever Yangbb337732019-07-22 20:02:01 +0800433config ROCKCHIP_COMMON_BOARD
434 bool "Rockchip common board file"
435 help
436 Rockchip SoCs have similar boot process, Common board file is mainly
437 in charge of common process of board_init() and board_late_init() for
438 U-Boot proper.
439
Kever Yang1d7cc72a2019-07-22 19:59:12 +0800440config SPL_ROCKCHIP_COMMON_BOARD
441 bool "Rockchip SPL common board file"
442 depends on SPL
443 help
444 Rockchip SoCs have similar boot process, SPL is mainly in charge of
445 load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
446 no TPL for the board.
447
Kever Yang34ead0f2019-07-09 22:05:55 +0800448config TPL_ROCKCHIP_COMMON_BOARD
Thomas Hebbcfbebf82019-12-20 18:05:22 -0800449 bool "Rockchip TPL common board file"
Kever Yang34ead0f2019-07-09 22:05:55 +0800450 depends on TPL
451 help
452 Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
453 init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
454 common board is a basic TPL board init which can be shared for most
Thomas Hebbfd37f242019-11-13 18:18:03 -0800455 of SoCs to avoid copy-paste for different SoCs.
Kever Yang34ead0f2019-07-09 22:05:55 +0800456
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000457config ROCKCHIP_EXTERNAL_TPL
458 bool "Use external TPL binary"
Massimo Pegorer8c20dfa2023-09-09 11:33:24 +0200459 default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000460 help
461 Some Rockchip SoCs require an external TPL to initialize DRAM.
462 Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
463 include the external TPL in the image built by binman.
464
Andy Yan70378cb2017-10-11 15:00:16 +0800465config ROCKCHIP_BOOT_MODE_REG
466 hex "Rockchip boot mode flag register address"
Andy Yan70378cb2017-10-11 15:00:16 +0800467 help
Kever Yang9fbe17c2019-03-28 11:01:23 +0800468 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yan70378cb2017-10-11 15:00:16 +0800469 according to the value from this register.
470
Chris Morgan7c9de742022-05-27 13:18:20 -0500471config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON
472 bool "Disable device boot on power plug-in"
473 depends on PMIC_RK8XX
Chris Morgan7c9de742022-05-27 13:18:20 -0500474 ---help---
475 Say Y here to prevent the device from booting up because of a plug-in
476 event. When set, the device will boot briefly to determine why it was
477 powered on, and if it was determined because of a plug-in event
478 instead of a button press event it will shut back off.
479
Johan Jonkerf6fc8952022-04-09 18:55:02 +0200480config ROCKCHIP_STIMER
481 bool "Rockchip STIMER support"
482 default y
483 help
484 Enable Rockchip STIMER support.
485
486config ROCKCHIP_STIMER_BASE
487 hex
488 depends on ROCKCHIP_STIMER
489
Kever Yange484f772017-04-20 17:03:46 +0800490config ROCKCHIP_SPL_RESERVE_IRAM
491 hex "Size of IRAM reserved in SPL"
Tom Rinif18679c2023-08-02 11:09:43 -0400492 default 0x0
Kever Yange484f772017-04-20 17:03:46 +0800493 help
494 SPL may need reserve memory for firmware loaded by SPL, whose load
495 address is in IRAM and may overlay with SPL text area if not
496 reserved.
497
Heiko Stübner355a8802017-02-18 19:46:25 +0100498config ROCKCHIP_BROM_HELPER
499 bool
500
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200501config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
502 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
503 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
504 help
505 Some Rockchip BROM variants (e.g. on the RK3188) load the
506 first stage in segments and enter multiple times. E.g. on
507 the RK3188, the first 1KB of the first stage are loaded
508 first and entered; after returning to the BROM, the
509 remainder of the first stage is loaded, but the BROM
510 re-enters at the same address/to the same code as previously.
511
512 This enables support code in the BOOT0 hook for the SPL stage
513 to allow multiple entries.
514
Quentin Schulz95b568f2024-03-11 13:01:54 +0100515config ROCKCHIP_DISABLE_FORCE_JTAG
516 bool "Disable force_jtag feature"
517 default y
518 depends on SPL
519 help
520 Rockchip SoCs can automatically switch between jtag and sdmmc based
521 on the following rules:
522 - all the SDMMC pins including SDMMC_DET set as SDMMC function in
523 GRF,
524 - force_jtag bit in GRF is 1,
525 - SDMMC_DET is low (no card detected),
526
527 Some HW design may not route the SD card card detect to SDMMC_DET
528 pin, thus breaking the SD card support in some cases because JTAG
529 would be auto-enabled by mistake.
530
531 Also, enabling JTAG at runtime may be an undesired feature, e.g.
532 because it could be a security vulnerability.
533
534 This disables force_jtag feature, which you may want for debugging
535 purposes.
536
537 If unsure, say Y.
538
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200539config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
540 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
541 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
542 help
543 Some Rockchip BROM variants (e.g. on the RK3188) load the
544 first stage in segments and enter multiple times. E.g. on
545 the RK3188, the first 1KB of the first stage are loaded
546 first and entered; after returning to the BROM, the
547 remainder of the first stage is loaded, but the BROM
548 re-enters at the same address/to the same code as previously.
549
550 This enables support code in the BOOT0 hook for the TPL stage
551 to allow multiple entries.
552
Simon Glassb58bfe02021-08-08 12:20:09 -0600553config SPL_MMC
Philipp Tomsich798370f2017-06-29 11:21:15 +0200554 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400555
Simon Glass88315f72020-07-19 13:55:57 -0600556config ROCKCHIP_SPI_IMAGE
557 bool "Build a SPI image for rockchip"
Simon Glass88315f72020-07-19 13:55:57 -0600558 help
559 Some Rockchip SoCs support booting from SPI flash. Enable this
Quentin Schulz12df9cf2022-09-02 15:10:54 +0200560 option to produce a SPI-flash image containing U-Boot. The image
561 is built by binman. U-Boot sits near the start of the image.
Simon Glass88315f72020-07-19 13:55:57 -0600562
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300563config LNX_KRNL_IMG_TEXT_OFFSET_BASE
Simon Glass72cc5382022-10-20 18:22:39 -0600564 default TEXT_BASE
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300565
Jonas Karlmane4453632024-03-02 19:16:11 +0000566config ROCKCHIP_COMMON_STACK_ADDR
567 bool
568 depends on SPL_SHARES_INIT_SP_ADDR
569 select HAS_CUSTOM_SYS_INIT_SP_ADDR
570 imply SPL_LIBCOMMON_SUPPORT if SPL
571 imply SPL_LIBGENERIC_SUPPORT if SPL
572 imply SPL_ROCKCHIP_COMMON_BOARD if SPL
573 imply SPL_SYS_MALLOC_F if SPL
574 imply SPL_SYS_MALLOC_SIMPLE if SPL
575 imply TPL_LIBCOMMON_SUPPORT if TPL
576 imply TPL_LIBGENERIC_SUPPORT if TPL
577 imply TPL_ROCKCHIP_COMMON_BOARD if TPL
578 imply TPL_SYS_MALLOC_F if TPL
579 imply TPL_SYS_MALLOC_SIMPLE if TPL
580
Heiko Stuebnerfc367852019-07-16 22:18:21 +0200581source "arch/arm/mach-rockchip/px30/Kconfig"
huang lin1115b642015-11-17 14:20:27 +0800582source "arch/arm/mach-rockchip/rk3036/Kconfig"
Johan Jonkera289fc72022-04-16 17:09:47 +0200583source "arch/arm/mach-rockchip/rk3066/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800584source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100585source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800586source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200587source "arch/arm/mach-rockchip/rk3288/Kconfig"
Andy Yanb5e16302019-11-14 11:21:12 +0800588source "arch/arm/mach-rockchip/rk3308/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800589source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800590source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800591source "arch/arm/mach-rockchip/rk3399/Kconfig"
Joseph Chen16899892021-06-02 16:13:46 +0800592source "arch/arm/mach-rockchip/rk3568/Kconfig"
Jagan Teki8967dea2023-01-30 20:27:45 +0530593source "arch/arm/mach-rockchip/rk3588/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800594source "arch/arm/mach-rockchip/rv1108/Kconfig"
Jagan Teki249a2382022-12-14 23:21:05 +0530595source "arch/arm/mach-rockchip/rv1126/Kconfig"
Jonas Karlmane4453632024-03-02 19:16:11 +0000596
597if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR
598
599config CUSTOM_SYS_INIT_SP_ADDR
600 default 0x3f00000
601
602config SYS_MALLOC_F_LEN
603 default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
604
605config SPL_SYS_MALLOC_F_LEN
606 default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
607
608config TPL_SYS_MALLOC_F_LEN
609 default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
610
611config TEXT_BASE
612 default 0x00200000 if ARM64
613
614config SPL_TEXT_BASE
615 default 0x0 if ARM64
616
617config SPL_HAS_BSS_LINKER_SECTION
618 default y if ARM64
619
620config SPL_BSS_START_ADDR
621 default 0x3f80000
622
623config SPL_BSS_MAX_SIZE
624 default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000
625
626config SPL_STACK_R
627 default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
628
629config SPL_STACK_R_ADDR
630 default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
631
632config SPL_STACK_R_MALLOC_SIMPLE_LEN
633 default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000
634
635endif
Simon Glass2cffe662015-08-30 16:55:38 -0600636endif