Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 1 | if ARCH_ROCKCHIP |
| 2 | |
Heiko Stuebner | fc36785 | 2019-07-16 22:18:21 +0200 | [diff] [blame] | 3 | config ROCKCHIP_PX30 |
| 4 | bool "Support Rockchip PX30" |
| 5 | select ARM64 |
| 6 | select SUPPORT_SPL |
| 7 | select SUPPORT_TPL |
| 8 | select SPL |
| 9 | select TPL |
| 10 | select TPL_TINY_FRAMEWORK if TPL |
Heiko Stuebner | fc36785 | 2019-07-16 22:18:21 +0200 | [diff] [blame] | 11 | select TPL_NEEDS_SEPARATE_STACK if TPL |
| 12 | imply SPL_SEPARATE_BSS |
Simon Glass | f4d6039 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 13 | select SPL_SERIAL |
| 14 | select TPL_SERIAL |
Heiko Stuebner | fc36785 | 2019-07-16 22:18:21 +0200 | [diff] [blame] | 15 | select DEBUG_UART_BOARD_INIT |
| 16 | imply ROCKCHIP_COMMON_BOARD |
| 17 | imply SPL_ROCKCHIP_COMMON_BOARD |
| 18 | help |
| 19 | The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35 |
| 20 | including NEON and GPU, Mali-400 graphics, several DDR3 options |
| 21 | and video codec support. Peripherals include Gigabit Ethernet, |
| 22 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. |
| 23 | |
Heiko Stübner | 5c91e2b | 2016-07-16 00:17:15 +0200 | [diff] [blame] | 24 | config ROCKCHIP_RK3036 |
| 25 | bool "Support Rockchip RK3036" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 26 | select CPU_V7A |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 27 | select SUPPORT_SPL |
| 28 | select SPL |
Eddie Cai | a79b78f | 2018-01-17 09:51:41 +0800 | [diff] [blame] | 29 | imply USB_FUNCTION_ROCKUSB |
| 30 | imply CMD_ROCKUSB |
Kever Yang | 427cb67 | 2019-07-22 20:02:04 +0800 | [diff] [blame] | 31 | imply ROCKCHIP_COMMON_BOARD |
Heiko Stübner | 5c91e2b | 2016-07-16 00:17:15 +0200 | [diff] [blame] | 32 | help |
| 33 | The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 |
| 34 | including NEON and GPU, Mali-400 graphics, several DDR3 options |
| 35 | and video codec support. Peripherals include Gigabit Ethernet, |
| 36 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. |
| 37 | |
Johan Jonker | a289fc7 | 2022-04-16 17:09:47 +0200 | [diff] [blame] | 38 | config ROCKCHIP_RK3066 |
| 39 | bool "Support Rockchip RK3066" |
| 40 | select CPU_V7A |
| 41 | select SPL_BOARD_INIT if SPL |
| 42 | select SUPPORT_SPL |
| 43 | select SUPPORT_TPL |
| 44 | select SPL |
| 45 | select TPL |
| 46 | select TPL_ROCKCHIP_BACK_TO_BROM |
| 47 | select TPL_ROCKCHIP_EARLYRETURN_TO_BROM |
| 48 | imply ROCKCHIP_COMMON_BOARD |
| 49 | imply SPL_ROCKCHIP_COMMON_BOARD |
| 50 | imply SPL_SERIAL |
| 51 | imply TPL_ROCKCHIP_COMMON_BOARD |
| 52 | imply TPL_SERIAL |
| 53 | help |
| 54 | The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9 |
| 55 | including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two |
| 56 | video interfaces, several memory options and video codec support. |
| 57 | Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, |
| 58 | UART, SPI, I2C and PWMs. |
| 59 | |
Kever Yang | aa82775 | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 60 | config ROCKCHIP_RK3128 |
| 61 | bool "Support Rockchip RK3128" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 62 | select CPU_V7A |
Kever Yang | 9636272 | 2019-07-22 20:02:05 +0800 | [diff] [blame] | 63 | imply ROCKCHIP_COMMON_BOARD |
Kever Yang | aa82775 | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 64 | help |
| 65 | The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 |
| 66 | including NEON and GPU, Mali-400 graphics, several DDR3 options |
| 67 | and video codec support. Peripherals include Gigabit Ethernet, |
| 68 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. |
| 69 | |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 70 | config ROCKCHIP_RK3188 |
| 71 | bool "Support Rockchip RK3188" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 72 | select CPU_V7A |
Ley Foon Tan | 48fcc4a | 2017-05-03 17:13:32 +0800 | [diff] [blame] | 73 | select SPL_BOARD_INIT if SPL |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 74 | select SUPPORT_SPL |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 75 | select SPL |
Philipp Tomsich | 5aa3f9d | 2017-10-10 16:21:17 +0200 | [diff] [blame] | 76 | select SPL_CLK |
Philipp Tomsich | 5aa3f9d | 2017-10-10 16:21:17 +0200 | [diff] [blame] | 77 | select SPL_REGMAP |
| 78 | select SPL_SYSCON |
| 79 | select SPL_RAM |
Simon Glass | 284cb9c | 2021-07-10 21:14:31 -0600 | [diff] [blame] | 80 | select SPL_DRIVERS_MISC |
Philipp Tomsich | 16c689c | 2017-10-10 16:21:15 +0200 | [diff] [blame] | 81 | select SPL_ROCKCHIP_EARLYRETURN_TO_BROM |
Kever Yang | bd8532e | 2019-07-22 19:59:15 +0800 | [diff] [blame] | 82 | select SPL_ROCKCHIP_BACK_TO_BROM |
Heiko Stübner | 015f69a | 2017-04-06 00:19:36 +0200 | [diff] [blame] | 83 | select BOARD_LATE_INIT |
Kever Yang | bfd3f87 | 2019-07-22 20:02:09 +0800 | [diff] [blame] | 84 | imply ROCKCHIP_COMMON_BOARD |
Kever Yang | 3bd9040 | 2019-07-22 19:59:18 +0800 | [diff] [blame] | 85 | imply SPL_ROCKCHIP_COMMON_BOARD |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 86 | help |
| 87 | The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9 |
| 88 | including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two |
| 89 | video interfaces, several memory options and video codec support. |
| 90 | Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, |
| 91 | UART, SPI, I2C and PWMs. |
| 92 | |
Kever Yang | 57d4dbf | 2017-06-23 17:17:52 +0800 | [diff] [blame] | 93 | config ROCKCHIP_RK322X |
| 94 | bool "Support Rockchip RK3228/RK3229" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 95 | select CPU_V7A |
Kever Yang | 57d4dbf | 2017-06-23 17:17:52 +0800 | [diff] [blame] | 96 | select SUPPORT_SPL |
Kever Yang | aff40c6 | 2019-04-02 20:41:24 +0800 | [diff] [blame] | 97 | select SUPPORT_TPL |
Kever Yang | 57d4dbf | 2017-06-23 17:17:52 +0800 | [diff] [blame] | 98 | select SPL |
Kever Yang | aff40c6 | 2019-04-02 20:41:24 +0800 | [diff] [blame] | 99 | select SPL_DM |
| 100 | select SPL_OF_LIBFDT |
| 101 | select TPL |
| 102 | select TPL_DM |
| 103 | select TPL_OF_LIBFDT |
Kever Yang | aff40c6 | 2019-04-02 20:41:24 +0800 | [diff] [blame] | 104 | select TPL_NEEDS_SEPARATE_STACK if TPL |
Simon Glass | 284cb9c | 2021-07-10 21:14:31 -0600 | [diff] [blame] | 105 | select SPL_DRIVERS_MISC |
Kever Yang | 0b51773 | 2019-07-22 20:02:07 +0800 | [diff] [blame] | 106 | imply ROCKCHIP_COMMON_BOARD |
Simon Glass | f4d6039 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 107 | imply SPL_SERIAL |
Kever Yang | d877fd2 | 2019-07-22 19:59:20 +0800 | [diff] [blame] | 108 | imply SPL_ROCKCHIP_COMMON_BOARD |
Alex Bee | 4fe3112 | 2023-07-18 16:57:13 +0200 | [diff] [blame] | 109 | select SPL_OPTEE_IMAGE if SPL_FIT |
Simon Glass | f4d6039 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 110 | imply TPL_SERIAL |
Kever Yang | 466f3fd | 2019-07-09 22:05:56 +0800 | [diff] [blame] | 111 | imply TPL_ROCKCHIP_COMMON_BOARD |
Kever Yang | aff40c6 | 2019-04-02 20:41:24 +0800 | [diff] [blame] | 112 | select TPL_LIBCOMMON_SUPPORT |
| 113 | select TPL_LIBGENERIC_SUPPORT |
Kever Yang | 57d4dbf | 2017-06-23 17:17:52 +0800 | [diff] [blame] | 114 | help |
| 115 | The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7 |
| 116 | including NEON and GPU, Mali-400 graphics, several DDR3 options |
| 117 | and video codec support. Peripherals include Gigabit Ethernet, |
| 118 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. |
| 119 | |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 120 | config ROCKCHIP_RK3288 |
| 121 | bool "Support Rockchip RK3288" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 122 | select CPU_V7A |
John Keeping | d5cb771 | 2023-02-23 19:28:51 +0000 | [diff] [blame] | 123 | select OF_SYSTEM_SETUP |
Tom Rini | e1e8544 | 2021-08-27 21:18:30 -0400 | [diff] [blame] | 124 | select SKIP_LOWLEVEL_INIT_ONLY |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 125 | select SUPPORT_SPL |
| 126 | select SPL |
Kever Yang | f7c0a33 | 2019-07-02 11:43:05 +0800 | [diff] [blame] | 127 | select SUPPORT_TPL |
Johan Jonker | 9a26fb1 | 2023-12-27 13:06:47 +0100 | [diff] [blame] | 128 | select FDT_64BIT |
Jagan Teki | 7b7cc95 | 2020-01-23 19:42:19 +0530 | [diff] [blame] | 129 | imply PRE_CONSOLE_BUFFER |
Kever Yang | ba87501 | 2019-07-22 20:02:15 +0800 | [diff] [blame] | 130 | imply ROCKCHIP_COMMON_BOARD |
Kever Yang | aa67deb | 2019-07-22 19:59:27 +0800 | [diff] [blame] | 131 | imply SPL_ROCKCHIP_COMMON_BOARD |
Kever Yang | f7c0a33 | 2019-07-02 11:43:05 +0800 | [diff] [blame] | 132 | imply TPL_CLK |
| 133 | imply TPL_DM |
Simon Glass | 284cb9c | 2021-07-10 21:14:31 -0600 | [diff] [blame] | 134 | imply TPL_DRIVERS_MISC |
Kever Yang | f7c0a33 | 2019-07-02 11:43:05 +0800 | [diff] [blame] | 135 | imply TPL_LIBCOMMON_SUPPORT |
| 136 | imply TPL_LIBGENERIC_SUPPORT |
Kever Yang | b36e709 | 2019-07-02 11:43:06 +0800 | [diff] [blame] | 137 | imply TPL_NEEDS_SEPARATE_STACK |
Kever Yang | f7c0a33 | 2019-07-02 11:43:05 +0800 | [diff] [blame] | 138 | imply TPL_OF_CONTROL |
| 139 | imply TPL_OF_PLATDATA |
| 140 | imply TPL_RAM |
| 141 | imply TPL_REGMAP |
Kever Yang | e32f38e | 2019-07-09 22:05:57 +0800 | [diff] [blame] | 142 | imply TPL_ROCKCHIP_COMMON_BOARD |
Simon Glass | f4d6039 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 143 | imply TPL_SERIAL |
Kever Yang | f7c0a33 | 2019-07-02 11:43:05 +0800 | [diff] [blame] | 144 | imply TPL_SYSCON |
Eddie Cai | b3501fe | 2017-12-15 08:17:13 +0800 | [diff] [blame] | 145 | imply USB_FUNCTION_ROCKUSB |
| 146 | imply CMD_ROCKUSB |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 147 | help |
| 148 | The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 |
| 149 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two |
| 150 | video interfaces supporting HDMI and eDP, several DDR3 options |
| 151 | and video codec support. Peripherals include Gigabit Ethernet, |
Andreas Färber | 531e8e0 | 2016-11-02 18:03:01 +0100 | [diff] [blame] | 152 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 153 | |
Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 154 | config ROCKCHIP_RK3308 |
| 155 | bool "Support Rockchip RK3308" |
| 156 | select ARM64 |
Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 157 | select SUPPORT_SPL |
| 158 | select SUPPORT_TPL |
| 159 | select SPL |
| 160 | select SPL_ATF |
| 161 | select SPL_ATF_NO_PLATFORM_PARAM |
| 162 | select SPL_LOAD_FIT |
Jonas Karlman | a2caa16 | 2024-04-08 18:14:00 +0000 | [diff] [blame^] | 163 | imply ARMV8_CRYPTO |
| 164 | imply ARMV8_SET_SMPEN |
| 165 | imply LEGACY_IMAGE_FORMAT |
Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 166 | imply ROCKCHIP_COMMON_BOARD |
Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 167 | imply SPL_CLK |
Jonas Karlman | a2caa16 | 2024-04-08 18:14:00 +0000 | [diff] [blame^] | 168 | imply SPL_FIT_SIGNATURE |
Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 169 | imply SPL_RAM |
Jonas Karlman | 16b0f90 | 2024-04-08 18:13:59 +0000 | [diff] [blame] | 170 | imply SPL_REGMAP |
| 171 | imply SPL_ROCKCHIP_COMMON_BOARD |
Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 172 | imply SPL_SEPARATE_BSS |
Jonas Karlman | 16b0f90 | 2024-04-08 18:13:59 +0000 | [diff] [blame] | 173 | imply SPL_SERIAL |
| 174 | imply SPL_SYSCON |
Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 175 | help |
| 176 | The Rockchip RK3308 is a ARM-based Soc which embedded with quad |
| 177 | Cortex-A35 and highly integrated audio interfaces. |
| 178 | |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 179 | config ROCKCHIP_RK3328 |
| 180 | bool "Support Rockchip RK3328" |
| 181 | select ARM64 |
Kever Yang | 07be669 | 2019-06-09 00:27:15 +0300 | [diff] [blame] | 182 | select SUPPORT_SPL |
| 183 | select SPL |
Kever Yang | 6987185 | 2019-08-02 10:40:01 +0300 | [diff] [blame] | 184 | select SUPPORT_TPL |
| 185 | select TPL |
Kever Yang | 6987185 | 2019-08-02 10:40:01 +0300 | [diff] [blame] | 186 | select TPL_NEEDS_SEPARATE_STACK if TPL |
Jagan Teki | fb71c88 | 2024-01-17 13:21:52 +0530 | [diff] [blame] | 187 | imply PRE_CONSOLE_BUFFER |
Kever Yang | 205e2cc | 2019-07-22 20:02:16 +0800 | [diff] [blame] | 188 | imply ROCKCHIP_COMMON_BOARD |
YouMin Chen | b9f7df3 | 2019-11-15 11:04:44 +0800 | [diff] [blame] | 189 | imply ROCKCHIP_SDRAM_COMMON |
Kever Yang | bb4c325 | 2019-07-22 19:59:32 +0800 | [diff] [blame] | 190 | imply SPL_ROCKCHIP_COMMON_BOARD |
Simon Glass | f4d6039 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 191 | imply SPL_SERIAL |
| 192 | imply TPL_SERIAL |
Kever Yang | 07be669 | 2019-06-09 00:27:15 +0300 | [diff] [blame] | 193 | imply SPL_SEPARATE_BSS |
| 194 | select ENABLE_ARM_SOC_BOOT0_HOOK |
| 195 | select DEBUG_UART_BOARD_INIT |
| 196 | select SYS_NS16550 |
Chen-Yu Tsai | bc26147 | 2024-02-12 21:51:04 +0800 | [diff] [blame] | 197 | imply MISC |
| 198 | imply ROCKCHIP_EFUSE |
| 199 | imply MISC_INIT_R |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 200 | help |
| 201 | The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. |
| 202 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two |
| 203 | video interfaces supporting HDMI and eDP, several DDR3 options |
| 204 | and video codec support. Peripherals include Gigabit Ethernet, |
| 205 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
| 206 | |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 207 | config ROCKCHIP_RK3368 |
| 208 | bool "Support Rockchip RK3368" |
| 209 | select ARM64 |
Philipp Tomsich | 84af43e | 2017-06-11 23:46:25 +0200 | [diff] [blame] | 210 | select SUPPORT_SPL |
| 211 | select SUPPORT_TPL |
Philipp Tomsich | 01b219e | 2017-07-28 20:03:07 +0200 | [diff] [blame] | 212 | select TPL_NEEDS_SEPARATE_STACK if TPL |
Kever Yang | 35b401e | 2019-07-22 20:02:17 +0800 | [diff] [blame] | 213 | imply ROCKCHIP_COMMON_BOARD |
Kever Yang | 8bf7ed4 | 2019-07-22 19:59:34 +0800 | [diff] [blame] | 214 | imply SPL_ROCKCHIP_COMMON_BOARD |
Philipp Tomsich | 84af43e | 2017-06-11 23:46:25 +0200 | [diff] [blame] | 215 | imply SPL_SEPARATE_BSS |
Simon Glass | f4d6039 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 216 | imply SPL_SERIAL |
| 217 | imply TPL_SERIAL |
Kever Yang | 48831b2 | 2019-07-09 22:05:58 +0800 | [diff] [blame] | 218 | imply TPL_ROCKCHIP_COMMON_BOARD |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 219 | help |
Philipp Tomsich | 9f3deaf | 2017-06-10 00:47:53 +0200 | [diff] [blame] | 220 | The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised |
| 221 | into a big and little cluster with 4 cores each) Cortex-A53 including |
| 222 | AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache |
| 223 | (for the little cluster), PowerVR G6110 based graphics, one video |
| 224 | output processor supporting LVDS/HDMI/eDP, several DDR3 options and |
| 225 | video codec support. |
| 226 | |
| 227 | On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, |
| 228 | I2S, UARTs, SPI, I2C and PWMs. |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 229 | |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 230 | config ROCKCHIP_RK3399 |
| 231 | bool "Support Rockchip RK3399" |
| 232 | select ARM64 |
Kever Yang | 16efdfd | 2017-02-22 16:56:38 +0800 | [diff] [blame] | 233 | select SUPPORT_SPL |
Kever Yang | fca798d | 2018-11-09 11:18:15 +0800 | [diff] [blame] | 234 | select SUPPORT_TPL |
Kever Yang | 16efdfd | 2017-02-22 16:56:38 +0800 | [diff] [blame] | 235 | select SPL |
Jagan Teki | cd43389 | 2019-05-08 11:11:43 +0530 | [diff] [blame] | 236 | select SPL_ATF |
Jagan Teki | ce063b9 | 2019-06-21 00:25:03 +0530 | [diff] [blame] | 237 | select SPL_BOARD_INIT if SPL |
Jagan Teki | cd43389 | 2019-05-08 11:11:43 +0530 | [diff] [blame] | 238 | select SPL_LOAD_FIT |
| 239 | select SPL_CLK if SPL |
| 240 | select SPL_PINCTRL if SPL |
| 241 | select SPL_RAM if SPL |
| 242 | select SPL_REGMAP if SPL |
| 243 | select SPL_SYSCON if SPL |
Kever Yang | fca798d | 2018-11-09 11:18:15 +0800 | [diff] [blame] | 244 | select TPL_NEEDS_SEPARATE_STACK if TPL |
Kever Yang | 16efdfd | 2017-02-22 16:56:38 +0800 | [diff] [blame] | 245 | select SPL_SEPARATE_BSS |
Simon Glass | f4d6039 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 246 | select SPL_SERIAL |
Simon Glass | 284cb9c | 2021-07-10 21:14:31 -0600 | [diff] [blame] | 247 | select SPL_DRIVERS_MISC |
Jagan Teki | cd43389 | 2019-05-08 11:11:43 +0530 | [diff] [blame] | 248 | select CLK |
| 249 | select FIT |
| 250 | select PINCTRL |
| 251 | select RAM |
| 252 | select REGMAP |
| 253 | select SYSCON |
| 254 | select DM_PMIC |
| 255 | select DM_REGULATOR_FIXED |
Andy Yan | 70378cb | 2017-10-11 15:00:16 +0800 | [diff] [blame] | 256 | select BOARD_LATE_INIT |
Sughosh Ganu | c1b8e8b | 2022-11-10 14:49:15 +0530 | [diff] [blame] | 257 | imply PARTITION_TYPE_GUID |
Jagan Teki | 9249d5c | 2020-04-02 17:11:23 +0530 | [diff] [blame] | 258 | imply PRE_CONSOLE_BUFFER |
Kever Yang | 9554a4e | 2019-07-22 20:02:19 +0800 | [diff] [blame] | 259 | imply ROCKCHIP_COMMON_BOARD |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 260 | imply ROCKCHIP_SDRAM_COMMON |
Kever Yang | ff9afe4 | 2019-07-22 19:59:42 +0800 | [diff] [blame] | 261 | imply SPL_ROCKCHIP_COMMON_BOARD |
Simon Glass | f4d6039 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 262 | imply TPL_SERIAL |
Kever Yang | fca798d | 2018-11-09 11:18:15 +0800 | [diff] [blame] | 263 | imply TPL_LIBCOMMON_SUPPORT |
| 264 | imply TPL_LIBGENERIC_SUPPORT |
| 265 | imply TPL_SYS_MALLOC_SIMPLE |
Simon Glass | 284cb9c | 2021-07-10 21:14:31 -0600 | [diff] [blame] | 266 | imply TPL_DRIVERS_MISC |
Kever Yang | fca798d | 2018-11-09 11:18:15 +0800 | [diff] [blame] | 267 | imply TPL_OF_CONTROL |
| 268 | imply TPL_DM |
| 269 | imply TPL_REGMAP |
| 270 | imply TPL_SYSCON |
| 271 | imply TPL_RAM |
| 272 | imply TPL_CLK |
| 273 | imply TPL_TINY_MEMSET |
Kever Yang | 3cfbb94 | 2019-07-09 22:06:01 +0800 | [diff] [blame] | 274 | imply TPL_ROCKCHIP_COMMON_BOARD |
Jagan Teki | e704301 | 2020-01-09 14:22:19 +0530 | [diff] [blame] | 275 | imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT |
Shantur Rathore | c000989 | 2024-01-21 22:04:47 +0000 | [diff] [blame] | 276 | imply BOOTSTD_FULL |
Jagan Teki | e704301 | 2020-01-09 14:22:19 +0530 | [diff] [blame] | 277 | imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT |
Chen-Yu Tsai | 3ccaa1d | 2024-02-12 21:51:05 +0800 | [diff] [blame] | 278 | imply MISC |
| 279 | imply ROCKCHIP_EFUSE |
| 280 | imply MISC_INIT_R |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 281 | help |
| 282 | The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 |
| 283 | and quad-core Cortex-A53. |
| 284 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two |
| 285 | video interfaces supporting HDMI and eDP, several DDR3 options |
| 286 | and video codec support. Peripherals include Gigabit Ethernet, |
| 287 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
| 288 | |
Joseph Chen | 72cd879 | 2021-06-02 15:58:25 +0800 | [diff] [blame] | 289 | config ROCKCHIP_RK3568 |
| 290 | bool "Support Rockchip RK3568" |
| 291 | select ARM64 |
Nico Cheng | 00ceeb0 | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 292 | select SUPPORT_SPL |
| 293 | select SPL |
Joseph Chen | 72cd879 | 2021-06-02 15:58:25 +0800 | [diff] [blame] | 294 | select CLK |
| 295 | select PINCTRL |
| 296 | select RAM |
| 297 | select REGMAP |
| 298 | select SYSCON |
| 299 | select BOARD_LATE_INIT |
Manoj Sai | b34b19c | 2023-02-17 17:28:44 +0530 | [diff] [blame] | 300 | select DM_REGULATOR_FIXED |
Jagan Teki | ce0bbac | 2023-02-17 17:28:34 +0530 | [diff] [blame] | 301 | select DM_RESET |
Jonas Karlman | 47af53c | 2023-04-17 19:07:15 +0000 | [diff] [blame] | 302 | imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF |
Joseph Chen | 72cd879 | 2021-06-02 15:58:25 +0800 | [diff] [blame] | 303 | imply ROCKCHIP_COMMON_BOARD |
Jonas Karlman | f4d27e9 | 2023-04-17 19:07:17 +0000 | [diff] [blame] | 304 | imply OF_LIBFDT_OVERLAY |
Jonas Karlman | be56bb5 | 2023-02-22 22:44:41 +0000 | [diff] [blame] | 305 | imply ROCKCHIP_OTP |
| 306 | imply MISC_INIT_R |
Jonas Karlman | 67bbb4e | 2024-02-04 20:53:06 +0000 | [diff] [blame] | 307 | imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP |
| 308 | imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT |
Joseph Chen | 72cd879 | 2021-06-02 15:58:25 +0800 | [diff] [blame] | 309 | help |
| 310 | The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55, |
| 311 | including NEON and GPU, 512K L3 cache, Mali-G52 based graphics, |
| 312 | two video interfaces supporting HDMI and eDP, several DDR3 options |
| 313 | and video codec support. Peripherals include Gigabit Ethernet, |
| 314 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
| 315 | |
Jagan Teki | 8967dea | 2023-01-30 20:27:45 +0530 | [diff] [blame] | 316 | config ROCKCHIP_RK3588 |
| 317 | bool "Support Rockchip RK3588" |
| 318 | select ARM64 |
| 319 | select SUPPORT_SPL |
| 320 | select SPL |
| 321 | select CLK |
| 322 | select PINCTRL |
| 323 | select RAM |
| 324 | select REGMAP |
| 325 | select SYSCON |
| 326 | select BOARD_LATE_INIT |
Jonas Karlman | 9bfd651 | 2023-05-17 18:26:37 +0000 | [diff] [blame] | 327 | select DM_REGULATOR_FIXED |
| 328 | select DM_RESET |
Jonas Karlman | 47af53c | 2023-04-17 19:07:15 +0000 | [diff] [blame] | 329 | imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF |
Jagan Teki | 8967dea | 2023-01-30 20:27:45 +0530 | [diff] [blame] | 330 | imply ROCKCHIP_COMMON_BOARD |
Jonas Karlman | f4d27e9 | 2023-04-17 19:07:17 +0000 | [diff] [blame] | 331 | imply OF_LIBFDT_OVERLAY |
Jonas Karlman | eeb1917 | 2023-02-22 22:44:41 +0000 | [diff] [blame] | 332 | imply ROCKCHIP_OTP |
| 333 | imply MISC_INIT_R |
Jonas Karlman | 67bbb4e | 2024-02-04 20:53:06 +0000 | [diff] [blame] | 334 | imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP |
| 335 | imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT |
Jonas Karlman | fc805c2 | 2023-04-17 19:07:21 +0000 | [diff] [blame] | 336 | imply CLK_SCMI |
| 337 | imply SCMI_FIRMWARE |
Shantur Rathore | c000989 | 2024-01-21 22:04:47 +0000 | [diff] [blame] | 338 | imply BOOTSTD_FULL |
Jagan Teki | 8967dea | 2023-01-30 20:27:45 +0530 | [diff] [blame] | 339 | help |
| 340 | The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and |
| 341 | quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4, |
| 342 | HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1, |
| 343 | SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet, |
| 344 | SDIO3.0 I2C, UART, SPI, GPIO and PWM. |
| 345 | |
Andy Yan | 2d982da | 2017-06-01 18:00:55 +0800 | [diff] [blame] | 346 | config ROCKCHIP_RV1108 |
| 347 | bool "Support Rockchip RV1108" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 348 | select CPU_V7A |
Kever Yang | a2b336e | 2019-07-22 20:02:21 +0800 | [diff] [blame] | 349 | imply ROCKCHIP_COMMON_BOARD |
Andy Yan | 2d982da | 2017-06-01 18:00:55 +0800 | [diff] [blame] | 350 | help |
| 351 | The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 |
| 352 | and a DSP. |
| 353 | |
Jagan Teki | 249a238 | 2022-12-14 23:21:05 +0530 | [diff] [blame] | 354 | config ROCKCHIP_RV1126 |
| 355 | bool "Support Rockchip RV1126" |
| 356 | select CPU_V7A |
| 357 | select SKIP_LOWLEVEL_INIT_ONLY |
| 358 | select TPL |
| 359 | select SUPPORT_TPL |
| 360 | select TPL_NEEDS_SEPARATE_STACK |
| 361 | select TPL_ROCKCHIP_BACK_TO_BROM |
| 362 | select SPL |
| 363 | select SUPPORT_SPL |
| 364 | select SPL_STACK_R |
| 365 | select CLK |
| 366 | select FIT |
| 367 | select PINCTRL |
| 368 | select RAM |
| 369 | select ROCKCHIP_SDRAM_COMMON |
| 370 | select REGMAP |
| 371 | select SYSCON |
| 372 | select DM_PMIC |
| 373 | select DM_REGULATOR_FIXED |
| 374 | select DM_RESET |
| 375 | select REGULATOR_RK8XX |
| 376 | select PMIC_RK8XX |
| 377 | select BOARD_LATE_INIT |
| 378 | imply ROCKCHIP_COMMON_BOARD |
Tim Lunn | d0812b2 | 2024-01-24 14:26:01 +1100 | [diff] [blame] | 379 | select SPL_OPTEE_IMAGE if SPL_FIT |
Jagan Teki | d679f62 | 2023-07-29 19:11:42 +0530 | [diff] [blame] | 380 | imply OF_LIBFDT_OVERLAY |
Tim Lunn | cbfee49 | 2023-10-31 13:07:15 +1100 | [diff] [blame] | 381 | imply ROCKCHIP_OTP |
| 382 | imply MISC_INIT_R |
Jagan Teki | 249a238 | 2022-12-14 23:21:05 +0530 | [diff] [blame] | 383 | imply TPL_DM |
| 384 | imply TPL_LIBCOMMON_SUPPORT |
| 385 | imply TPL_LIBGENERIC_SUPPORT |
| 386 | imply TPL_OF_CONTROL |
| 387 | imply TPL_OF_PLATDATA |
| 388 | imply TPL_RAM |
| 389 | imply TPL_ROCKCHIP_COMMON_BOARD |
| 390 | imply TPL_SERIAL |
| 391 | imply SPL_CLK |
| 392 | imply SPL_DM |
| 393 | imply SPL_DRIVERS_MISC |
| 394 | imply SPL_LIBCOMMON_SUPPORT |
| 395 | imply SPL_LIBGENERIC_SUPPORT |
| 396 | imply SPL_OF_CONTROL |
| 397 | imply SPL_RAM |
| 398 | imply SPL_REGMAP |
| 399 | imply SPL_ROCKCHIP_COMMON_BOARD |
| 400 | imply SPL_SERIAL |
| 401 | imply SPL_SYSCON |
| 402 | |
Heiko Stuebner | 9cc8feb | 2018-10-08 13:01:56 +0200 | [diff] [blame] | 403 | config ROCKCHIP_USB_UART |
| 404 | bool "Route uart output to usb pins" |
| 405 | help |
| 406 | Rockchip SoCs have the ability to route the signals of the debug |
| 407 | uart through the d+ and d- pins of a specific usb phy to enable |
| 408 | some form of closed-case debugging. With this option supported |
| 409 | SoCs will enable this routing as a debug measure. |
| 410 | |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 411 | config SPL_ROCKCHIP_BACK_TO_BROM |
Xu Ziyuan | 5401eb8 | 2016-07-12 19:09:49 +0800 | [diff] [blame] | 412 | bool "SPL returns to bootrom" |
| 413 | default y if ROCKCHIP_RK3036 |
Heiko Stübner | 355a880 | 2017-02-18 19:46:25 +0100 | [diff] [blame] | 414 | select ROCKCHIP_BROM_HELPER |
Kever Yang | bd8532e | 2019-07-22 19:59:15 +0800 | [diff] [blame] | 415 | select SPL_BOOTROM_SUPPORT |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 416 | depends on SPL |
Xu Ziyuan | 5401eb8 | 2016-07-12 19:09:49 +0800 | [diff] [blame] | 417 | help |
| 418 | Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, |
| 419 | SPL will return to the boot rom, which will then load the U-Boot |
| 420 | binary to keep going on. |
| 421 | |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 422 | config TPL_ROCKCHIP_BACK_TO_BROM |
| 423 | bool "TPL returns to bootrom" |
Kever Yang | fca798d | 2018-11-09 11:18:15 +0800 | [diff] [blame] | 424 | default y |
Johan Jonker | a768ff5 | 2023-10-27 20:35:37 +0200 | [diff] [blame] | 425 | select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066 |
Kever Yang | bd8532e | 2019-07-22 19:59:15 +0800 | [diff] [blame] | 426 | select TPL_BOOTROM_SUPPORT |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 427 | depends on TPL |
| 428 | help |
| 429 | Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, |
| 430 | SPL will return to the boot rom, which will then load the U-Boot |
| 431 | binary to keep going on. |
| 432 | |
Kever Yang | bb33773 | 2019-07-22 20:02:01 +0800 | [diff] [blame] | 433 | config ROCKCHIP_COMMON_BOARD |
| 434 | bool "Rockchip common board file" |
| 435 | help |
| 436 | Rockchip SoCs have similar boot process, Common board file is mainly |
| 437 | in charge of common process of board_init() and board_late_init() for |
| 438 | U-Boot proper. |
| 439 | |
Kever Yang | 1d7cc72a | 2019-07-22 19:59:12 +0800 | [diff] [blame] | 440 | config SPL_ROCKCHIP_COMMON_BOARD |
| 441 | bool "Rockchip SPL common board file" |
| 442 | depends on SPL |
| 443 | help |
| 444 | Rockchip SoCs have similar boot process, SPL is mainly in charge of |
| 445 | load and boot Trust ATF/U-Boot firmware, and DRAM init if there is |
| 446 | no TPL for the board. |
| 447 | |
Kever Yang | 34ead0f | 2019-07-09 22:05:55 +0800 | [diff] [blame] | 448 | config TPL_ROCKCHIP_COMMON_BOARD |
Thomas Hebb | cfbebf8 | 2019-12-20 18:05:22 -0800 | [diff] [blame] | 449 | bool "Rockchip TPL common board file" |
Kever Yang | 34ead0f | 2019-07-09 22:05:55 +0800 | [diff] [blame] | 450 | depends on TPL |
| 451 | help |
| 452 | Rockchip SoCs have similar boot process, prefer to use TPL for DRAM |
| 453 | init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL |
| 454 | common board is a basic TPL board init which can be shared for most |
Thomas Hebb | fd37f24 | 2019-11-13 18:18:03 -0800 | [diff] [blame] | 455 | of SoCs to avoid copy-paste for different SoCs. |
Kever Yang | 34ead0f | 2019-07-09 22:05:55 +0800 | [diff] [blame] | 456 | |
Jonas Karlman | 38ad6c9 | 2023-02-25 19:01:34 +0000 | [diff] [blame] | 457 | config ROCKCHIP_EXTERNAL_TPL |
| 458 | bool "Use external TPL binary" |
Massimo Pegorer | 8c20dfa | 2023-09-09 11:33:24 +0200 | [diff] [blame] | 459 | default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588 |
Jonas Karlman | 38ad6c9 | 2023-02-25 19:01:34 +0000 | [diff] [blame] | 460 | help |
| 461 | Some Rockchip SoCs require an external TPL to initialize DRAM. |
| 462 | Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to |
| 463 | include the external TPL in the image built by binman. |
| 464 | |
Andy Yan | 70378cb | 2017-10-11 15:00:16 +0800 | [diff] [blame] | 465 | config ROCKCHIP_BOOT_MODE_REG |
| 466 | hex "Rockchip boot mode flag register address" |
Andy Yan | 70378cb | 2017-10-11 15:00:16 +0800 | [diff] [blame] | 467 | help |
Kever Yang | 9fbe17c | 2019-03-28 11:01:23 +0800 | [diff] [blame] | 468 | The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h) |
Andy Yan | 70378cb | 2017-10-11 15:00:16 +0800 | [diff] [blame] | 469 | according to the value from this register. |
| 470 | |
Chris Morgan | 7c9de74 | 2022-05-27 13:18:20 -0500 | [diff] [blame] | 471 | config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON |
| 472 | bool "Disable device boot on power plug-in" |
| 473 | depends on PMIC_RK8XX |
Chris Morgan | 7c9de74 | 2022-05-27 13:18:20 -0500 | [diff] [blame] | 474 | ---help--- |
| 475 | Say Y here to prevent the device from booting up because of a plug-in |
| 476 | event. When set, the device will boot briefly to determine why it was |
| 477 | powered on, and if it was determined because of a plug-in event |
| 478 | instead of a button press event it will shut back off. |
| 479 | |
Johan Jonker | f6fc895 | 2022-04-09 18:55:02 +0200 | [diff] [blame] | 480 | config ROCKCHIP_STIMER |
| 481 | bool "Rockchip STIMER support" |
| 482 | default y |
| 483 | help |
| 484 | Enable Rockchip STIMER support. |
| 485 | |
| 486 | config ROCKCHIP_STIMER_BASE |
| 487 | hex |
| 488 | depends on ROCKCHIP_STIMER |
| 489 | |
Kever Yang | e484f77 | 2017-04-20 17:03:46 +0800 | [diff] [blame] | 490 | config ROCKCHIP_SPL_RESERVE_IRAM |
| 491 | hex "Size of IRAM reserved in SPL" |
Tom Rini | f18679c | 2023-08-02 11:09:43 -0400 | [diff] [blame] | 492 | default 0x0 |
Kever Yang | e484f77 | 2017-04-20 17:03:46 +0800 | [diff] [blame] | 493 | help |
| 494 | SPL may need reserve memory for firmware loaded by SPL, whose load |
| 495 | address is in IRAM and may overlay with SPL text area if not |
| 496 | reserved. |
| 497 | |
Heiko Stübner | 355a880 | 2017-02-18 19:46:25 +0100 | [diff] [blame] | 498 | config ROCKCHIP_BROM_HELPER |
| 499 | bool |
| 500 | |
Philipp Tomsich | 9f1a447 | 2017-10-10 16:21:10 +0200 | [diff] [blame] | 501 | config SPL_ROCKCHIP_EARLYRETURN_TO_BROM |
| 502 | bool "SPL requires early-return (for RK3188-style BROM) to BROM" |
| 503 | depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK |
| 504 | help |
| 505 | Some Rockchip BROM variants (e.g. on the RK3188) load the |
| 506 | first stage in segments and enter multiple times. E.g. on |
| 507 | the RK3188, the first 1KB of the first stage are loaded |
| 508 | first and entered; after returning to the BROM, the |
| 509 | remainder of the first stage is loaded, but the BROM |
| 510 | re-enters at the same address/to the same code as previously. |
| 511 | |
| 512 | This enables support code in the BOOT0 hook for the SPL stage |
| 513 | to allow multiple entries. |
| 514 | |
Quentin Schulz | 95b568f | 2024-03-11 13:01:54 +0100 | [diff] [blame] | 515 | config ROCKCHIP_DISABLE_FORCE_JTAG |
| 516 | bool "Disable force_jtag feature" |
| 517 | default y |
| 518 | depends on SPL |
| 519 | help |
| 520 | Rockchip SoCs can automatically switch between jtag and sdmmc based |
| 521 | on the following rules: |
| 522 | - all the SDMMC pins including SDMMC_DET set as SDMMC function in |
| 523 | GRF, |
| 524 | - force_jtag bit in GRF is 1, |
| 525 | - SDMMC_DET is low (no card detected), |
| 526 | |
| 527 | Some HW design may not route the SD card card detect to SDMMC_DET |
| 528 | pin, thus breaking the SD card support in some cases because JTAG |
| 529 | would be auto-enabled by mistake. |
| 530 | |
| 531 | Also, enabling JTAG at runtime may be an undesired feature, e.g. |
| 532 | because it could be a security vulnerability. |
| 533 | |
| 534 | This disables force_jtag feature, which you may want for debugging |
| 535 | purposes. |
| 536 | |
| 537 | If unsure, say Y. |
| 538 | |
Philipp Tomsich | 9f1a447 | 2017-10-10 16:21:10 +0200 | [diff] [blame] | 539 | config TPL_ROCKCHIP_EARLYRETURN_TO_BROM |
| 540 | bool "TPL requires early-return (for RK3188-style BROM) to BROM" |
| 541 | depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK |
| 542 | help |
| 543 | Some Rockchip BROM variants (e.g. on the RK3188) load the |
| 544 | first stage in segments and enter multiple times. E.g. on |
| 545 | the RK3188, the first 1KB of the first stage are loaded |
| 546 | first and entered; after returning to the BROM, the |
| 547 | remainder of the first stage is loaded, but the BROM |
| 548 | re-enters at the same address/to the same code as previously. |
| 549 | |
| 550 | This enables support code in the BOOT0 hook for the TPL stage |
| 551 | to allow multiple entries. |
| 552 | |
Simon Glass | b58bfe0 | 2021-08-08 12:20:09 -0600 | [diff] [blame] | 553 | config SPL_MMC |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 554 | default y if !SPL_ROCKCHIP_BACK_TO_BROM |
Sandy Patterson | d70f0f3 | 2016-08-29 07:31:16 -0400 | [diff] [blame] | 555 | |
Simon Glass | 88315f7 | 2020-07-19 13:55:57 -0600 | [diff] [blame] | 556 | config ROCKCHIP_SPI_IMAGE |
| 557 | bool "Build a SPI image for rockchip" |
Simon Glass | 88315f7 | 2020-07-19 13:55:57 -0600 | [diff] [blame] | 558 | help |
| 559 | Some Rockchip SoCs support booting from SPI flash. Enable this |
Quentin Schulz | 12df9cf | 2022-09-02 15:10:54 +0200 | [diff] [blame] | 560 | option to produce a SPI-flash image containing U-Boot. The image |
| 561 | is built by binman. U-Boot sits near the start of the image. |
Simon Glass | 88315f7 | 2020-07-19 13:55:57 -0600 | [diff] [blame] | 562 | |
Alper Nebi Yasak | cf9159e | 2022-01-29 18:27:56 +0300 | [diff] [blame] | 563 | config LNX_KRNL_IMG_TEXT_OFFSET_BASE |
Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 564 | default TEXT_BASE |
Alper Nebi Yasak | cf9159e | 2022-01-29 18:27:56 +0300 | [diff] [blame] | 565 | |
Jonas Karlman | e445363 | 2024-03-02 19:16:11 +0000 | [diff] [blame] | 566 | config ROCKCHIP_COMMON_STACK_ADDR |
| 567 | bool |
| 568 | depends on SPL_SHARES_INIT_SP_ADDR |
| 569 | select HAS_CUSTOM_SYS_INIT_SP_ADDR |
| 570 | imply SPL_LIBCOMMON_SUPPORT if SPL |
| 571 | imply SPL_LIBGENERIC_SUPPORT if SPL |
| 572 | imply SPL_ROCKCHIP_COMMON_BOARD if SPL |
| 573 | imply SPL_SYS_MALLOC_F if SPL |
| 574 | imply SPL_SYS_MALLOC_SIMPLE if SPL |
| 575 | imply TPL_LIBCOMMON_SUPPORT if TPL |
| 576 | imply TPL_LIBGENERIC_SUPPORT if TPL |
| 577 | imply TPL_ROCKCHIP_COMMON_BOARD if TPL |
| 578 | imply TPL_SYS_MALLOC_F if TPL |
| 579 | imply TPL_SYS_MALLOC_SIMPLE if TPL |
| 580 | |
Heiko Stuebner | fc36785 | 2019-07-16 22:18:21 +0200 | [diff] [blame] | 581 | source "arch/arm/mach-rockchip/px30/Kconfig" |
huang lin | 1115b64 | 2015-11-17 14:20:27 +0800 | [diff] [blame] | 582 | source "arch/arm/mach-rockchip/rk3036/Kconfig" |
Johan Jonker | a289fc7 | 2022-04-16 17:09:47 +0200 | [diff] [blame] | 583 | source "arch/arm/mach-rockchip/rk3066/Kconfig" |
Kever Yang | aa82775 | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 584 | source "arch/arm/mach-rockchip/rk3128/Kconfig" |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 585 | source "arch/arm/mach-rockchip/rk3188/Kconfig" |
Kever Yang | a4f460d | 2017-06-23 17:17:54 +0800 | [diff] [blame] | 586 | source "arch/arm/mach-rockchip/rk322x/Kconfig" |
Heiko Stübner | 5c91e2b | 2016-07-16 00:17:15 +0200 | [diff] [blame] | 587 | source "arch/arm/mach-rockchip/rk3288/Kconfig" |
Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 588 | source "arch/arm/mach-rockchip/rk3308/Kconfig" |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 589 | source "arch/arm/mach-rockchip/rk3328/Kconfig" |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 590 | source "arch/arm/mach-rockchip/rk3368/Kconfig" |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 591 | source "arch/arm/mach-rockchip/rk3399/Kconfig" |
Joseph Chen | 1689989 | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 592 | source "arch/arm/mach-rockchip/rk3568/Kconfig" |
Jagan Teki | 8967dea | 2023-01-30 20:27:45 +0530 | [diff] [blame] | 593 | source "arch/arm/mach-rockchip/rk3588/Kconfig" |
Andy Yan | 2d982da | 2017-06-01 18:00:55 +0800 | [diff] [blame] | 594 | source "arch/arm/mach-rockchip/rv1108/Kconfig" |
Jagan Teki | 249a238 | 2022-12-14 23:21:05 +0530 | [diff] [blame] | 595 | source "arch/arm/mach-rockchip/rv1126/Kconfig" |
Jonas Karlman | e445363 | 2024-03-02 19:16:11 +0000 | [diff] [blame] | 596 | |
| 597 | if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR |
| 598 | |
| 599 | config CUSTOM_SYS_INIT_SP_ADDR |
| 600 | default 0x3f00000 |
| 601 | |
| 602 | config SYS_MALLOC_F_LEN |
| 603 | default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 |
| 604 | |
| 605 | config SPL_SYS_MALLOC_F_LEN |
| 606 | default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 |
| 607 | |
| 608 | config TPL_SYS_MALLOC_F_LEN |
| 609 | default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 |
| 610 | |
| 611 | config TEXT_BASE |
| 612 | default 0x00200000 if ARM64 |
| 613 | |
| 614 | config SPL_TEXT_BASE |
| 615 | default 0x0 if ARM64 |
| 616 | |
| 617 | config SPL_HAS_BSS_LINKER_SECTION |
| 618 | default y if ARM64 |
| 619 | |
| 620 | config SPL_BSS_START_ADDR |
| 621 | default 0x3f80000 |
| 622 | |
| 623 | config SPL_BSS_MAX_SIZE |
| 624 | default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000 |
| 625 | |
| 626 | config SPL_STACK_R |
| 627 | default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 |
| 628 | |
| 629 | config SPL_STACK_R_ADDR |
| 630 | default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 |
| 631 | |
| 632 | config SPL_STACK_R_MALLOC_SIMPLE_LEN |
| 633 | default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000 |
| 634 | |
| 635 | endif |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 636 | endif |