blob: 4a77f181021a04799e9da82cfe8843fe670eff24 [file] [log] [blame]
Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stuebnerfc367852019-07-16 22:18:21 +02003config ROCKCHIP_PX30
4 bool "Support Rockchip PX30"
5 select ARM64
6 select SUPPORT_SPL
7 select SUPPORT_TPL
8 select SPL
9 select TPL
10 select TPL_TINY_FRAMEWORK if TPL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020011 select TPL_NEEDS_SEPARATE_STACK if TPL
12 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -060013 select SPL_SERIAL
14 select TPL_SERIAL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020015 select DEBUG_UART_BOARD_INIT
16 imply ROCKCHIP_COMMON_BOARD
17 imply SPL_ROCKCHIP_COMMON_BOARD
18 help
19 The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
20 including NEON and GPU, Mali-400 graphics, several DDR3 options
21 and video codec support. Peripherals include Gigabit Ethernet,
22 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
23
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020024config ROCKCHIP_RK3036
25 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053026 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +080027 select SUPPORT_SPL
28 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +080029 imply USB_FUNCTION_ROCKUSB
30 imply CMD_ROCKUSB
Kever Yang427cb672019-07-22 20:02:04 +080031 imply ROCKCHIP_COMMON_BOARD
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020032 help
33 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
34 including NEON and GPU, Mali-400 graphics, several DDR3 options
35 and video codec support. Peripherals include Gigabit Ethernet,
36 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
37
Johan Jonkera289fc72022-04-16 17:09:47 +020038config ROCKCHIP_RK3066
39 bool "Support Rockchip RK3066"
40 select CPU_V7A
41 select SPL_BOARD_INIT if SPL
42 select SUPPORT_SPL
43 select SUPPORT_TPL
44 select SPL
45 select TPL
46 select TPL_ROCKCHIP_BACK_TO_BROM
47 select TPL_ROCKCHIP_EARLYRETURN_TO_BROM
48 imply ROCKCHIP_COMMON_BOARD
49 imply SPL_ROCKCHIP_COMMON_BOARD
50 imply SPL_SERIAL
51 imply TPL_ROCKCHIP_COMMON_BOARD
52 imply TPL_SERIAL
53 help
54 The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
55 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
56 video interfaces, several memory options and video codec support.
57 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
58 UART, SPI, I2C and PWMs.
59
Kever Yangaa827752017-11-28 16:04:16 +080060config ROCKCHIP_RK3128
61 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053062 select CPU_V7A
Kever Yang96362722019-07-22 20:02:05 +080063 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa827752017-11-28 16:04:16 +080064 help
65 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
66 including NEON and GPU, Mali-400 graphics, several DDR3 options
67 and video codec support. Peripherals include Gigabit Ethernet,
68 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
69
Heiko Stübneref6db5e2017-02-18 19:46:36 +010070config ROCKCHIP_RK3188
71 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053072 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080073 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010074 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010075 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020076 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020077 select SPL_REGMAP
78 select SPL_SYSCON
79 select SPL_RAM
Simon Glass284cb9c2021-07-10 21:14:31 -060080 select SPL_DRIVERS_MISC
Philipp Tomsich16c689c2017-10-10 16:21:15 +020081 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangbd8532e2019-07-22 19:59:15 +080082 select SPL_ROCKCHIP_BACK_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020083 select BOARD_LATE_INIT
Kever Yangbfd3f872019-07-22 20:02:09 +080084 imply ROCKCHIP_COMMON_BOARD
Kever Yang3bd90402019-07-22 19:59:18 +080085 imply SPL_ROCKCHIP_COMMON_BOARD
Heiko Stübneref6db5e2017-02-18 19:46:36 +010086 help
87 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
88 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
89 video interfaces, several memory options and video codec support.
90 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
91 UART, SPI, I2C and PWMs.
92
Kever Yang57d4dbf2017-06-23 17:17:52 +080093config ROCKCHIP_RK322X
94 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053095 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080096 select SUPPORT_SPL
Kever Yangaff40c62019-04-02 20:41:24 +080097 select SUPPORT_TPL
Kever Yang57d4dbf2017-06-23 17:17:52 +080098 select SPL
Kever Yangaff40c62019-04-02 20:41:24 +080099 select SPL_DM
100 select SPL_OF_LIBFDT
101 select TPL
102 select TPL_DM
103 select TPL_OF_LIBFDT
Kever Yangaff40c62019-04-02 20:41:24 +0800104 select TPL_NEEDS_SEPARATE_STACK if TPL
Simon Glass284cb9c2021-07-10 21:14:31 -0600105 select SPL_DRIVERS_MISC
Kever Yang0b517732019-07-22 20:02:07 +0800106 imply ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600107 imply SPL_SERIAL
Kever Yangd877fd22019-07-22 19:59:20 +0800108 imply SPL_ROCKCHIP_COMMON_BOARD
Alex Bee4fe31122023-07-18 16:57:13 +0200109 select SPL_OPTEE_IMAGE if SPL_FIT
Simon Glassf4d60392021-08-08 12:20:12 -0600110 imply TPL_SERIAL
Kever Yang466f3fd2019-07-09 22:05:56 +0800111 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +0800112 select TPL_LIBCOMMON_SUPPORT
113 select TPL_LIBGENERIC_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +0800114 help
115 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
116 including NEON and GPU, Mali-400 graphics, several DDR3 options
117 and video codec support. Peripherals include Gigabit Ethernet,
118 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
119
Simon Glass2cffe662015-08-30 16:55:38 -0600120config ROCKCHIP_RK3288
121 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530122 select CPU_V7A
John Keepingd5cb7712023-02-23 19:28:51 +0000123 select OF_SYSTEM_SETUP
Tom Rinie1e85442021-08-27 21:18:30 -0400124 select SKIP_LOWLEVEL_INIT_ONLY
Kever Yang0d3d7832016-07-19 21:16:59 +0800125 select SUPPORT_SPL
126 select SPL
Kever Yangf7c0a332019-07-02 11:43:05 +0800127 select SUPPORT_TPL
Johan Jonker9a26fb12023-12-27 13:06:47 +0100128 select FDT_64BIT
Jagan Teki7b7cc952020-01-23 19:42:19 +0530129 imply PRE_CONSOLE_BUFFER
Kever Yangba875012019-07-22 20:02:15 +0800130 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa67deb2019-07-22 19:59:27 +0800131 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +0800132 imply TPL_CLK
133 imply TPL_DM
Simon Glass284cb9c2021-07-10 21:14:31 -0600134 imply TPL_DRIVERS_MISC
Kever Yangf7c0a332019-07-02 11:43:05 +0800135 imply TPL_LIBCOMMON_SUPPORT
136 imply TPL_LIBGENERIC_SUPPORT
Kever Yangb36e7092019-07-02 11:43:06 +0800137 imply TPL_NEEDS_SEPARATE_STACK
Kever Yangf7c0a332019-07-02 11:43:05 +0800138 imply TPL_OF_CONTROL
139 imply TPL_OF_PLATDATA
140 imply TPL_RAM
141 imply TPL_REGMAP
Kever Yange32f38e2019-07-09 22:05:57 +0800142 imply TPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600143 imply TPL_SERIAL
Kever Yangf7c0a332019-07-02 11:43:05 +0800144 imply TPL_SYSCON
Eddie Caib3501fe2017-12-15 08:17:13 +0800145 imply USB_FUNCTION_ROCKUSB
146 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -0600147 help
148 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
149 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
150 video interfaces supporting HDMI and eDP, several DDR3 options
151 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +0100152 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -0600153
Andy Yanb5e16302019-11-14 11:21:12 +0800154config ROCKCHIP_RK3308
155 bool "Support Rockchip RK3308"
156 select ARM64
Andy Yanb5e16302019-11-14 11:21:12 +0800157 select SUPPORT_SPL
158 select SUPPORT_TPL
159 select SPL
160 select SPL_ATF
161 select SPL_ATF_NO_PLATFORM_PARAM
162 select SPL_LOAD_FIT
163 imply ROCKCHIP_COMMON_BOARD
Andy Yanb5e16302019-11-14 11:21:12 +0800164 imply SPL_CLK
Andy Yanb5e16302019-11-14 11:21:12 +0800165 imply SPL_RAM
Jonas Karlman16b0f902024-04-08 18:13:59 +0000166 imply SPL_REGMAP
167 imply SPL_ROCKCHIP_COMMON_BOARD
Andy Yanb5e16302019-11-14 11:21:12 +0800168 imply SPL_SEPARATE_BSS
Jonas Karlman16b0f902024-04-08 18:13:59 +0000169 imply SPL_SERIAL
170 imply SPL_SYSCON
Andy Yanb5e16302019-11-14 11:21:12 +0800171 help
172 The Rockchip RK3308 is a ARM-based Soc which embedded with quad
173 Cortex-A35 and highly integrated audio interfaces.
174
Kever Yangec02b3c2017-02-23 15:37:51 +0800175config ROCKCHIP_RK3328
176 bool "Support Rockchip RK3328"
177 select ARM64
Kever Yang07be6692019-06-09 00:27:15 +0300178 select SUPPORT_SPL
179 select SPL
Kever Yang69871852019-08-02 10:40:01 +0300180 select SUPPORT_TPL
181 select TPL
Kever Yang69871852019-08-02 10:40:01 +0300182 select TPL_NEEDS_SEPARATE_STACK if TPL
Jagan Tekifb71c882024-01-17 13:21:52 +0530183 imply PRE_CONSOLE_BUFFER
Kever Yang205e2cc2019-07-22 20:02:16 +0800184 imply ROCKCHIP_COMMON_BOARD
YouMin Chenb9f7df32019-11-15 11:04:44 +0800185 imply ROCKCHIP_SDRAM_COMMON
Kever Yangbb4c3252019-07-22 19:59:32 +0800186 imply SPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600187 imply SPL_SERIAL
188 imply TPL_SERIAL
Kever Yang07be6692019-06-09 00:27:15 +0300189 imply SPL_SEPARATE_BSS
190 select ENABLE_ARM_SOC_BOOT0_HOOK
191 select DEBUG_UART_BOARD_INIT
192 select SYS_NS16550
Chen-Yu Tsaibc261472024-02-12 21:51:04 +0800193 imply MISC
194 imply ROCKCHIP_EFUSE
195 imply MISC_INIT_R
Kever Yangec02b3c2017-02-23 15:37:51 +0800196 help
197 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
198 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
199 video interfaces supporting HDMI and eDP, several DDR3 options
200 and video codec support. Peripherals include Gigabit Ethernet,
201 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
202
Andreas Färber9e3ad682017-05-15 17:51:18 +0800203config ROCKCHIP_RK3368
204 bool "Support Rockchip RK3368"
205 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200206 select SUPPORT_SPL
207 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200208 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang35b401e2019-07-22 20:02:17 +0800209 imply ROCKCHIP_COMMON_BOARD
Kever Yang8bf7ed42019-07-22 19:59:34 +0800210 imply SPL_ROCKCHIP_COMMON_BOARD
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200211 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600212 imply SPL_SERIAL
213 imply TPL_SERIAL
Kever Yang48831b22019-07-09 22:05:58 +0800214 imply TPL_ROCKCHIP_COMMON_BOARD
Andreas Färber9e3ad682017-05-15 17:51:18 +0800215 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200216 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
217 into a big and little cluster with 4 cores each) Cortex-A53 including
218 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
219 (for the little cluster), PowerVR G6110 based graphics, one video
220 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
221 video codec support.
222
223 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
224 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800225
Kever Yang0d3d7832016-07-19 21:16:59 +0800226config ROCKCHIP_RK3399
227 bool "Support Rockchip RK3399"
228 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800229 select SUPPORT_SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800230 select SUPPORT_TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800231 select SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530232 select SPL_ATF
Jagan Tekice063b92019-06-21 00:25:03 +0530233 select SPL_BOARD_INIT if SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530234 select SPL_LOAD_FIT
235 select SPL_CLK if SPL
236 select SPL_PINCTRL if SPL
237 select SPL_RAM if SPL
238 select SPL_REGMAP if SPL
239 select SPL_SYSCON if SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800240 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800241 select SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600242 select SPL_SERIAL
Simon Glass284cb9c2021-07-10 21:14:31 -0600243 select SPL_DRIVERS_MISC
Jagan Tekicd433892019-05-08 11:11:43 +0530244 select CLK
245 select FIT
246 select PINCTRL
247 select RAM
248 select REGMAP
249 select SYSCON
250 select DM_PMIC
251 select DM_REGULATOR_FIXED
Andy Yan70378cb2017-10-11 15:00:16 +0800252 select BOARD_LATE_INIT
Sughosh Ganuc1b8e8b2022-11-10 14:49:15 +0530253 imply PARTITION_TYPE_GUID
Jagan Teki9249d5c2020-04-02 17:11:23 +0530254 imply PRE_CONSOLE_BUFFER
Kever Yang9554a4e2019-07-22 20:02:19 +0800255 imply ROCKCHIP_COMMON_BOARD
YouMin Chen23ae72e2019-11-15 11:04:45 +0800256 imply ROCKCHIP_SDRAM_COMMON
Kever Yangff9afe42019-07-22 19:59:42 +0800257 imply SPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600258 imply TPL_SERIAL
Kever Yangfca798d2018-11-09 11:18:15 +0800259 imply TPL_LIBCOMMON_SUPPORT
260 imply TPL_LIBGENERIC_SUPPORT
261 imply TPL_SYS_MALLOC_SIMPLE
Simon Glass284cb9c2021-07-10 21:14:31 -0600262 imply TPL_DRIVERS_MISC
Kever Yangfca798d2018-11-09 11:18:15 +0800263 imply TPL_OF_CONTROL
264 imply TPL_DM
265 imply TPL_REGMAP
266 imply TPL_SYSCON
267 imply TPL_RAM
268 imply TPL_CLK
269 imply TPL_TINY_MEMSET
Kever Yang3cfbb942019-07-09 22:06:01 +0800270 imply TPL_ROCKCHIP_COMMON_BOARD
Jagan Tekie7043012020-01-09 14:22:19 +0530271 imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
Shantur Rathorec0009892024-01-21 22:04:47 +0000272 imply BOOTSTD_FULL
Jagan Tekie7043012020-01-09 14:22:19 +0530273 imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
Chen-Yu Tsai3ccaa1d2024-02-12 21:51:05 +0800274 imply MISC
275 imply ROCKCHIP_EFUSE
276 imply MISC_INIT_R
Kever Yang0d3d7832016-07-19 21:16:59 +0800277 help
278 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
279 and quad-core Cortex-A53.
280 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
281 video interfaces supporting HDMI and eDP, several DDR3 options
282 and video codec support. Peripherals include Gigabit Ethernet,
283 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
284
Joseph Chen72cd8792021-06-02 15:58:25 +0800285config ROCKCHIP_RK3568
286 bool "Support Rockchip RK3568"
287 select ARM64
Nico Cheng00ceeb02021-10-26 10:42:19 +0800288 select SUPPORT_SPL
289 select SPL
Joseph Chen72cd8792021-06-02 15:58:25 +0800290 select CLK
291 select PINCTRL
292 select RAM
293 select REGMAP
294 select SYSCON
295 select BOARD_LATE_INIT
Manoj Saib34b19c2023-02-17 17:28:44 +0530296 select DM_REGULATOR_FIXED
Jagan Tekice0bbac2023-02-17 17:28:34 +0530297 select DM_RESET
Jonas Karlman47af53c2023-04-17 19:07:15 +0000298 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Joseph Chen72cd8792021-06-02 15:58:25 +0800299 imply ROCKCHIP_COMMON_BOARD
Jonas Karlmanf4d27e92023-04-17 19:07:17 +0000300 imply OF_LIBFDT_OVERLAY
Jonas Karlmanbe56bb52023-02-22 22:44:41 +0000301 imply ROCKCHIP_OTP
302 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000303 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
304 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Joseph Chen72cd8792021-06-02 15:58:25 +0800305 help
306 The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
307 including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
308 two video interfaces supporting HDMI and eDP, several DDR3 options
309 and video codec support. Peripherals include Gigabit Ethernet,
310 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
311
Jagan Teki8967dea2023-01-30 20:27:45 +0530312config ROCKCHIP_RK3588
313 bool "Support Rockchip RK3588"
314 select ARM64
315 select SUPPORT_SPL
316 select SPL
317 select CLK
318 select PINCTRL
319 select RAM
320 select REGMAP
321 select SYSCON
322 select BOARD_LATE_INIT
Jonas Karlman9bfd6512023-05-17 18:26:37 +0000323 select DM_REGULATOR_FIXED
324 select DM_RESET
Jonas Karlman47af53c2023-04-17 19:07:15 +0000325 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Jagan Teki8967dea2023-01-30 20:27:45 +0530326 imply ROCKCHIP_COMMON_BOARD
Jonas Karlmanf4d27e92023-04-17 19:07:17 +0000327 imply OF_LIBFDT_OVERLAY
Jonas Karlmaneeb19172023-02-22 22:44:41 +0000328 imply ROCKCHIP_OTP
329 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000330 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
331 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Jonas Karlmanfc805c22023-04-17 19:07:21 +0000332 imply CLK_SCMI
333 imply SCMI_FIRMWARE
Shantur Rathorec0009892024-01-21 22:04:47 +0000334 imply BOOTSTD_FULL
Jagan Teki8967dea2023-01-30 20:27:45 +0530335 help
336 The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
337 quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
338 HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1,
339 SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet,
340 SDIO3.0 I2C, UART, SPI, GPIO and PWM.
341
Andy Yan2d982da2017-06-01 18:00:55 +0800342config ROCKCHIP_RV1108
343 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530344 select CPU_V7A
Kever Yanga2b336e2019-07-22 20:02:21 +0800345 imply ROCKCHIP_COMMON_BOARD
Andy Yan2d982da2017-06-01 18:00:55 +0800346 help
347 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
348 and a DSP.
349
Jagan Teki249a2382022-12-14 23:21:05 +0530350config ROCKCHIP_RV1126
351 bool "Support Rockchip RV1126"
352 select CPU_V7A
353 select SKIP_LOWLEVEL_INIT_ONLY
354 select TPL
355 select SUPPORT_TPL
356 select TPL_NEEDS_SEPARATE_STACK
357 select TPL_ROCKCHIP_BACK_TO_BROM
358 select SPL
359 select SUPPORT_SPL
360 select SPL_STACK_R
361 select CLK
362 select FIT
363 select PINCTRL
364 select RAM
365 select ROCKCHIP_SDRAM_COMMON
366 select REGMAP
367 select SYSCON
368 select DM_PMIC
369 select DM_REGULATOR_FIXED
370 select DM_RESET
371 select REGULATOR_RK8XX
372 select PMIC_RK8XX
373 select BOARD_LATE_INIT
374 imply ROCKCHIP_COMMON_BOARD
Tim Lunnd0812b22024-01-24 14:26:01 +1100375 select SPL_OPTEE_IMAGE if SPL_FIT
Jagan Tekid679f622023-07-29 19:11:42 +0530376 imply OF_LIBFDT_OVERLAY
Tim Lunncbfee492023-10-31 13:07:15 +1100377 imply ROCKCHIP_OTP
378 imply MISC_INIT_R
Jagan Teki249a2382022-12-14 23:21:05 +0530379 imply TPL_DM
380 imply TPL_LIBCOMMON_SUPPORT
381 imply TPL_LIBGENERIC_SUPPORT
382 imply TPL_OF_CONTROL
383 imply TPL_OF_PLATDATA
384 imply TPL_RAM
385 imply TPL_ROCKCHIP_COMMON_BOARD
386 imply TPL_SERIAL
387 imply SPL_CLK
388 imply SPL_DM
389 imply SPL_DRIVERS_MISC
390 imply SPL_LIBCOMMON_SUPPORT
391 imply SPL_LIBGENERIC_SUPPORT
392 imply SPL_OF_CONTROL
393 imply SPL_RAM
394 imply SPL_REGMAP
395 imply SPL_ROCKCHIP_COMMON_BOARD
396 imply SPL_SERIAL
397 imply SPL_SYSCON
398
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200399config ROCKCHIP_USB_UART
400 bool "Route uart output to usb pins"
401 help
402 Rockchip SoCs have the ability to route the signals of the debug
403 uart through the d+ and d- pins of a specific usb phy to enable
404 some form of closed-case debugging. With this option supported
405 SoCs will enable this routing as a debug measure.
406
Philipp Tomsich798370f2017-06-29 11:21:15 +0200407config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800408 bool "SPL returns to bootrom"
409 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100410 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800411 select SPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200412 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800413 help
414 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
415 SPL will return to the boot rom, which will then load the U-Boot
416 binary to keep going on.
417
Philipp Tomsich798370f2017-06-29 11:21:15 +0200418config TPL_ROCKCHIP_BACK_TO_BROM
419 bool "TPL returns to bootrom"
Kever Yangfca798d2018-11-09 11:18:15 +0800420 default y
Johan Jonkera768ff52023-10-27 20:35:37 +0200421 select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066
Kever Yangbd8532e2019-07-22 19:59:15 +0800422 select TPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200423 depends on TPL
424 help
425 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
426 SPL will return to the boot rom, which will then load the U-Boot
427 binary to keep going on.
428
Kever Yangbb337732019-07-22 20:02:01 +0800429config ROCKCHIP_COMMON_BOARD
430 bool "Rockchip common board file"
431 help
432 Rockchip SoCs have similar boot process, Common board file is mainly
433 in charge of common process of board_init() and board_late_init() for
434 U-Boot proper.
435
Kever Yang1d7cc72a2019-07-22 19:59:12 +0800436config SPL_ROCKCHIP_COMMON_BOARD
437 bool "Rockchip SPL common board file"
438 depends on SPL
439 help
440 Rockchip SoCs have similar boot process, SPL is mainly in charge of
441 load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
442 no TPL for the board.
443
Kever Yang34ead0f2019-07-09 22:05:55 +0800444config TPL_ROCKCHIP_COMMON_BOARD
Thomas Hebbcfbebf82019-12-20 18:05:22 -0800445 bool "Rockchip TPL common board file"
Kever Yang34ead0f2019-07-09 22:05:55 +0800446 depends on TPL
447 help
448 Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
449 init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
450 common board is a basic TPL board init which can be shared for most
Thomas Hebbfd37f242019-11-13 18:18:03 -0800451 of SoCs to avoid copy-paste for different SoCs.
Kever Yang34ead0f2019-07-09 22:05:55 +0800452
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000453config ROCKCHIP_EXTERNAL_TPL
454 bool "Use external TPL binary"
Massimo Pegorer8c20dfa2023-09-09 11:33:24 +0200455 default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000456 help
457 Some Rockchip SoCs require an external TPL to initialize DRAM.
458 Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
459 include the external TPL in the image built by binman.
460
Andy Yan70378cb2017-10-11 15:00:16 +0800461config ROCKCHIP_BOOT_MODE_REG
462 hex "Rockchip boot mode flag register address"
Andy Yan70378cb2017-10-11 15:00:16 +0800463 help
Kever Yang9fbe17c2019-03-28 11:01:23 +0800464 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yan70378cb2017-10-11 15:00:16 +0800465 according to the value from this register.
466
Chris Morgan7c9de742022-05-27 13:18:20 -0500467config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON
468 bool "Disable device boot on power plug-in"
469 depends on PMIC_RK8XX
Chris Morgan7c9de742022-05-27 13:18:20 -0500470 ---help---
471 Say Y here to prevent the device from booting up because of a plug-in
472 event. When set, the device will boot briefly to determine why it was
473 powered on, and if it was determined because of a plug-in event
474 instead of a button press event it will shut back off.
475
Johan Jonkerf6fc8952022-04-09 18:55:02 +0200476config ROCKCHIP_STIMER
477 bool "Rockchip STIMER support"
478 default y
479 help
480 Enable Rockchip STIMER support.
481
482config ROCKCHIP_STIMER_BASE
483 hex
484 depends on ROCKCHIP_STIMER
485
Kever Yange484f772017-04-20 17:03:46 +0800486config ROCKCHIP_SPL_RESERVE_IRAM
487 hex "Size of IRAM reserved in SPL"
Tom Rinif18679c2023-08-02 11:09:43 -0400488 default 0x0
Kever Yange484f772017-04-20 17:03:46 +0800489 help
490 SPL may need reserve memory for firmware loaded by SPL, whose load
491 address is in IRAM and may overlay with SPL text area if not
492 reserved.
493
Heiko Stübner355a8802017-02-18 19:46:25 +0100494config ROCKCHIP_BROM_HELPER
495 bool
496
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200497config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
498 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
499 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
500 help
501 Some Rockchip BROM variants (e.g. on the RK3188) load the
502 first stage in segments and enter multiple times. E.g. on
503 the RK3188, the first 1KB of the first stage are loaded
504 first and entered; after returning to the BROM, the
505 remainder of the first stage is loaded, but the BROM
506 re-enters at the same address/to the same code as previously.
507
508 This enables support code in the BOOT0 hook for the SPL stage
509 to allow multiple entries.
510
Quentin Schulz95b568f2024-03-11 13:01:54 +0100511config ROCKCHIP_DISABLE_FORCE_JTAG
512 bool "Disable force_jtag feature"
513 default y
514 depends on SPL
515 help
516 Rockchip SoCs can automatically switch between jtag and sdmmc based
517 on the following rules:
518 - all the SDMMC pins including SDMMC_DET set as SDMMC function in
519 GRF,
520 - force_jtag bit in GRF is 1,
521 - SDMMC_DET is low (no card detected),
522
523 Some HW design may not route the SD card card detect to SDMMC_DET
524 pin, thus breaking the SD card support in some cases because JTAG
525 would be auto-enabled by mistake.
526
527 Also, enabling JTAG at runtime may be an undesired feature, e.g.
528 because it could be a security vulnerability.
529
530 This disables force_jtag feature, which you may want for debugging
531 purposes.
532
533 If unsure, say Y.
534
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200535config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
536 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
537 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
538 help
539 Some Rockchip BROM variants (e.g. on the RK3188) load the
540 first stage in segments and enter multiple times. E.g. on
541 the RK3188, the first 1KB of the first stage are loaded
542 first and entered; after returning to the BROM, the
543 remainder of the first stage is loaded, but the BROM
544 re-enters at the same address/to the same code as previously.
545
546 This enables support code in the BOOT0 hook for the TPL stage
547 to allow multiple entries.
548
Simon Glassb58bfe02021-08-08 12:20:09 -0600549config SPL_MMC
Philipp Tomsich798370f2017-06-29 11:21:15 +0200550 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400551
Simon Glass88315f72020-07-19 13:55:57 -0600552config ROCKCHIP_SPI_IMAGE
553 bool "Build a SPI image for rockchip"
Simon Glass88315f72020-07-19 13:55:57 -0600554 help
555 Some Rockchip SoCs support booting from SPI flash. Enable this
Quentin Schulz12df9cf2022-09-02 15:10:54 +0200556 option to produce a SPI-flash image containing U-Boot. The image
557 is built by binman. U-Boot sits near the start of the image.
Simon Glass88315f72020-07-19 13:55:57 -0600558
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300559config LNX_KRNL_IMG_TEXT_OFFSET_BASE
Simon Glass72cc5382022-10-20 18:22:39 -0600560 default TEXT_BASE
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300561
Jonas Karlmane4453632024-03-02 19:16:11 +0000562config ROCKCHIP_COMMON_STACK_ADDR
563 bool
564 depends on SPL_SHARES_INIT_SP_ADDR
565 select HAS_CUSTOM_SYS_INIT_SP_ADDR
566 imply SPL_LIBCOMMON_SUPPORT if SPL
567 imply SPL_LIBGENERIC_SUPPORT if SPL
568 imply SPL_ROCKCHIP_COMMON_BOARD if SPL
569 imply SPL_SYS_MALLOC_F if SPL
570 imply SPL_SYS_MALLOC_SIMPLE if SPL
571 imply TPL_LIBCOMMON_SUPPORT if TPL
572 imply TPL_LIBGENERIC_SUPPORT if TPL
573 imply TPL_ROCKCHIP_COMMON_BOARD if TPL
574 imply TPL_SYS_MALLOC_F if TPL
575 imply TPL_SYS_MALLOC_SIMPLE if TPL
576
Heiko Stuebnerfc367852019-07-16 22:18:21 +0200577source "arch/arm/mach-rockchip/px30/Kconfig"
huang lin1115b642015-11-17 14:20:27 +0800578source "arch/arm/mach-rockchip/rk3036/Kconfig"
Johan Jonkera289fc72022-04-16 17:09:47 +0200579source "arch/arm/mach-rockchip/rk3066/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800580source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100581source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800582source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200583source "arch/arm/mach-rockchip/rk3288/Kconfig"
Andy Yanb5e16302019-11-14 11:21:12 +0800584source "arch/arm/mach-rockchip/rk3308/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800585source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800586source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800587source "arch/arm/mach-rockchip/rk3399/Kconfig"
Joseph Chen16899892021-06-02 16:13:46 +0800588source "arch/arm/mach-rockchip/rk3568/Kconfig"
Jagan Teki8967dea2023-01-30 20:27:45 +0530589source "arch/arm/mach-rockchip/rk3588/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800590source "arch/arm/mach-rockchip/rv1108/Kconfig"
Jagan Teki249a2382022-12-14 23:21:05 +0530591source "arch/arm/mach-rockchip/rv1126/Kconfig"
Jonas Karlmane4453632024-03-02 19:16:11 +0000592
593if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR
594
595config CUSTOM_SYS_INIT_SP_ADDR
596 default 0x3f00000
597
598config SYS_MALLOC_F_LEN
599 default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
600
601config SPL_SYS_MALLOC_F_LEN
602 default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
603
604config TPL_SYS_MALLOC_F_LEN
605 default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
606
607config TEXT_BASE
608 default 0x00200000 if ARM64
609
610config SPL_TEXT_BASE
611 default 0x0 if ARM64
612
613config SPL_HAS_BSS_LINKER_SECTION
614 default y if ARM64
615
616config SPL_BSS_START_ADDR
617 default 0x3f80000
618
619config SPL_BSS_MAX_SIZE
620 default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000
621
622config SPL_STACK_R
623 default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
624
625config SPL_STACK_R_ADDR
626 default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
627
628config SPL_STACK_R_MALLOC_SIMPLE_LEN
629 default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000
630
631endif
Simon Glass2cffe662015-08-30 16:55:38 -0600632endif