blob: 03f6bf43fdf46e636e1f89e855664c0fc40685f3 [file] [log] [blame]
Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stuebnerfc367852019-07-16 22:18:21 +02003config ROCKCHIP_PX30
4 bool "Support Rockchip PX30"
5 select ARM64
6 select SUPPORT_SPL
7 select SUPPORT_TPL
8 select SPL
9 select TPL
10 select TPL_TINY_FRAMEWORK if TPL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020011 select TPL_NEEDS_SEPARATE_STACK if TPL
12 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -060013 select SPL_SERIAL
14 select TPL_SERIAL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020015 select DEBUG_UART_BOARD_INIT
16 imply ROCKCHIP_COMMON_BOARD
17 imply SPL_ROCKCHIP_COMMON_BOARD
18 help
19 The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
20 including NEON and GPU, Mali-400 graphics, several DDR3 options
21 and video codec support. Peripherals include Gigabit Ethernet,
22 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
23
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020024config ROCKCHIP_RK3036
25 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053026 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +080027 select SUPPORT_SPL
28 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +080029 imply USB_FUNCTION_ROCKUSB
30 imply CMD_ROCKUSB
Kever Yang427cb672019-07-22 20:02:04 +080031 imply ROCKCHIP_COMMON_BOARD
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020032 help
33 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
34 including NEON and GPU, Mali-400 graphics, several DDR3 options
35 and video codec support. Peripherals include Gigabit Ethernet,
36 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
37
Johan Jonkera289fc72022-04-16 17:09:47 +020038config ROCKCHIP_RK3066
39 bool "Support Rockchip RK3066"
40 select CPU_V7A
41 select SPL_BOARD_INIT if SPL
42 select SUPPORT_SPL
43 select SUPPORT_TPL
44 select SPL
45 select TPL
46 select TPL_ROCKCHIP_BACK_TO_BROM
47 select TPL_ROCKCHIP_EARLYRETURN_TO_BROM
48 imply ROCKCHIP_COMMON_BOARD
49 imply SPL_ROCKCHIP_COMMON_BOARD
50 imply SPL_SERIAL
51 imply TPL_ROCKCHIP_COMMON_BOARD
52 imply TPL_SERIAL
53 help
54 The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
55 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
56 video interfaces, several memory options and video codec support.
57 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
58 UART, SPI, I2C and PWMs.
59
Kever Yangaa827752017-11-28 16:04:16 +080060config ROCKCHIP_RK3128
61 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053062 select CPU_V7A
Kever Yang96362722019-07-22 20:02:05 +080063 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa827752017-11-28 16:04:16 +080064 help
65 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
66 including NEON and GPU, Mali-400 graphics, several DDR3 options
67 and video codec support. Peripherals include Gigabit Ethernet,
68 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
69
Heiko Stübneref6db5e2017-02-18 19:46:36 +010070config ROCKCHIP_RK3188
71 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053072 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080073 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010074 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010075 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020076 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020077 select SPL_REGMAP
78 select SPL_SYSCON
79 select SPL_RAM
Simon Glass284cb9c2021-07-10 21:14:31 -060080 select SPL_DRIVERS_MISC
Philipp Tomsich16c689c2017-10-10 16:21:15 +020081 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangbd8532e2019-07-22 19:59:15 +080082 select SPL_ROCKCHIP_BACK_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020083 select BOARD_LATE_INIT
Kever Yangbfd3f872019-07-22 20:02:09 +080084 imply ROCKCHIP_COMMON_BOARD
Kever Yang3bd90402019-07-22 19:59:18 +080085 imply SPL_ROCKCHIP_COMMON_BOARD
Heiko Stübneref6db5e2017-02-18 19:46:36 +010086 help
87 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
88 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
89 video interfaces, several memory options and video codec support.
90 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
91 UART, SPI, I2C and PWMs.
92
Kever Yang57d4dbf2017-06-23 17:17:52 +080093config ROCKCHIP_RK322X
94 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053095 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080096 select SUPPORT_SPL
Kever Yangaff40c62019-04-02 20:41:24 +080097 select SUPPORT_TPL
Kever Yang57d4dbf2017-06-23 17:17:52 +080098 select SPL
Kever Yangaff40c62019-04-02 20:41:24 +080099 select SPL_DM
100 select SPL_OF_LIBFDT
101 select TPL
102 select TPL_DM
103 select TPL_OF_LIBFDT
Kever Yangaff40c62019-04-02 20:41:24 +0800104 select TPL_NEEDS_SEPARATE_STACK if TPL
Simon Glass284cb9c2021-07-10 21:14:31 -0600105 select SPL_DRIVERS_MISC
Kever Yang0b517732019-07-22 20:02:07 +0800106 imply ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600107 imply SPL_SERIAL
Kever Yangd877fd22019-07-22 19:59:20 +0800108 imply SPL_ROCKCHIP_COMMON_BOARD
Alex Bee4fe31122023-07-18 16:57:13 +0200109 select SPL_OPTEE_IMAGE if SPL_FIT
Simon Glassf4d60392021-08-08 12:20:12 -0600110 imply TPL_SERIAL
Kever Yang466f3fd2019-07-09 22:05:56 +0800111 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +0800112 select TPL_LIBCOMMON_SUPPORT
113 select TPL_LIBGENERIC_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +0800114 help
115 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
116 including NEON and GPU, Mali-400 graphics, several DDR3 options
117 and video codec support. Peripherals include Gigabit Ethernet,
118 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
119
Simon Glass2cffe662015-08-30 16:55:38 -0600120config ROCKCHIP_RK3288
121 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530122 select CPU_V7A
John Keepingd5cb7712023-02-23 19:28:51 +0000123 select OF_SYSTEM_SETUP
Tom Rinie1e85442021-08-27 21:18:30 -0400124 select SKIP_LOWLEVEL_INIT_ONLY
Kever Yang0d3d7832016-07-19 21:16:59 +0800125 select SUPPORT_SPL
126 select SPL
Kever Yangf7c0a332019-07-02 11:43:05 +0800127 select SUPPORT_TPL
Johan Jonker9a26fb12023-12-27 13:06:47 +0100128 select FDT_64BIT
Jagan Teki7b7cc952020-01-23 19:42:19 +0530129 imply PRE_CONSOLE_BUFFER
Kever Yangba875012019-07-22 20:02:15 +0800130 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa67deb2019-07-22 19:59:27 +0800131 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +0800132 imply TPL_CLK
133 imply TPL_DM
Simon Glass284cb9c2021-07-10 21:14:31 -0600134 imply TPL_DRIVERS_MISC
Kever Yangf7c0a332019-07-02 11:43:05 +0800135 imply TPL_LIBCOMMON_SUPPORT
136 imply TPL_LIBGENERIC_SUPPORT
Kever Yangb36e7092019-07-02 11:43:06 +0800137 imply TPL_NEEDS_SEPARATE_STACK
Kever Yangf7c0a332019-07-02 11:43:05 +0800138 imply TPL_OF_CONTROL
139 imply TPL_OF_PLATDATA
140 imply TPL_RAM
141 imply TPL_REGMAP
Kever Yange32f38e2019-07-09 22:05:57 +0800142 imply TPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600143 imply TPL_SERIAL
Kever Yangf7c0a332019-07-02 11:43:05 +0800144 imply TPL_SYSCON
Eddie Caib3501fe2017-12-15 08:17:13 +0800145 imply USB_FUNCTION_ROCKUSB
146 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -0600147 help
148 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
149 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
150 video interfaces supporting HDMI and eDP, several DDR3 options
151 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +0100152 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -0600153
Andy Yanb5e16302019-11-14 11:21:12 +0800154config ROCKCHIP_RK3308
155 bool "Support Rockchip RK3308"
156 select ARM64
Andy Yanb5e16302019-11-14 11:21:12 +0800157 select SUPPORT_SPL
158 select SUPPORT_TPL
159 select SPL
160 select SPL_ATF
161 select SPL_ATF_NO_PLATFORM_PARAM
162 select SPL_LOAD_FIT
Jonas Karlmana2caa162024-04-08 18:14:00 +0000163 imply ARMV8_CRYPTO
164 imply ARMV8_SET_SMPEN
Jonas Karlmanfbced692024-04-08 18:14:02 +0000165 imply DM_RNG
Jonas Karlmana2caa162024-04-08 18:14:00 +0000166 imply LEGACY_IMAGE_FORMAT
Jonas Karlman1cf34dd2024-04-08 18:14:01 +0000167 imply MISC
168 imply MISC_INIT_R
Jonas Karlman0cab3c52024-05-04 19:42:53 +0000169 imply OF_UPSTREAM
Jonas Karlmanfbced692024-04-08 18:14:02 +0000170 imply RNG_ROCKCHIP
Andy Yanb5e16302019-11-14 11:21:12 +0800171 imply ROCKCHIP_COMMON_BOARD
Jonas Karlman1cf34dd2024-04-08 18:14:01 +0000172 imply ROCKCHIP_OTP
Andy Yanb5e16302019-11-14 11:21:12 +0800173 imply SPL_CLK
Jonas Karlmana499c982024-04-08 18:14:03 +0000174 imply SPL_DM_SEQ_ALIAS
Jonas Karlmana2caa162024-04-08 18:14:00 +0000175 imply SPL_FIT_SIGNATURE
Jonas Karlmana499c982024-04-08 18:14:03 +0000176 imply SPL_PINCTRL
Andy Yanb5e16302019-11-14 11:21:12 +0800177 imply SPL_RAM
Jonas Karlman16b0f902024-04-08 18:13:59 +0000178 imply SPL_REGMAP
179 imply SPL_ROCKCHIP_COMMON_BOARD
Andy Yanb5e16302019-11-14 11:21:12 +0800180 imply SPL_SEPARATE_BSS
Jonas Karlman16b0f902024-04-08 18:13:59 +0000181 imply SPL_SERIAL
182 imply SPL_SYSCON
Andy Yanb5e16302019-11-14 11:21:12 +0800183 help
184 The Rockchip RK3308 is a ARM-based Soc which embedded with quad
185 Cortex-A35 and highly integrated audio interfaces.
186
Kever Yangec02b3c2017-02-23 15:37:51 +0800187config ROCKCHIP_RK3328
188 bool "Support Rockchip RK3328"
189 select ARM64
Kever Yang07be6692019-06-09 00:27:15 +0300190 select SUPPORT_SPL
191 select SPL
Kever Yang69871852019-08-02 10:40:01 +0300192 select SUPPORT_TPL
193 select TPL
Kever Yang69871852019-08-02 10:40:01 +0300194 select TPL_NEEDS_SEPARATE_STACK if TPL
Jonas Karlman1b3d9dd2024-04-21 20:09:02 +0000195 imply ARMV8_CRYPTO
196 imply ARMV8_SET_SMPEN
Jonas Karlman86d4ebb2024-04-21 20:09:01 +0000197 imply MISC
198 imply MISC_INIT_R
Jonas Karlman1b3d9dd2024-04-21 20:09:02 +0000199 imply OF_LIVE
Jonas Karlmaned6f48e2024-05-04 19:42:55 +0000200 imply OF_UPSTREAM
Jagan Tekifb71c882024-01-17 13:21:52 +0530201 imply PRE_CONSOLE_BUFFER
Kever Yang205e2cc2019-07-22 20:02:16 +0800202 imply ROCKCHIP_COMMON_BOARD
Jonas Karlman86d4ebb2024-04-21 20:09:01 +0000203 imply ROCKCHIP_EFUSE
YouMin Chenb9f7df32019-11-15 11:04:44 +0800204 imply ROCKCHIP_SDRAM_COMMON
Kever Yangbb4c3252019-07-22 19:59:32 +0800205 imply SPL_ROCKCHIP_COMMON_BOARD
Jonas Karlman86d4ebb2024-04-21 20:09:01 +0000206 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600207 imply SPL_SERIAL
208 imply TPL_SERIAL
Kever Yangec02b3c2017-02-23 15:37:51 +0800209 help
210 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
211 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
212 video interfaces supporting HDMI and eDP, several DDR3 options
213 and video codec support. Peripherals include Gigabit Ethernet,
214 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
215
Andreas Färber9e3ad682017-05-15 17:51:18 +0800216config ROCKCHIP_RK3368
217 bool "Support Rockchip RK3368"
218 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200219 select SUPPORT_SPL
220 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200221 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang35b401e2019-07-22 20:02:17 +0800222 imply ROCKCHIP_COMMON_BOARD
Kever Yang8bf7ed42019-07-22 19:59:34 +0800223 imply SPL_ROCKCHIP_COMMON_BOARD
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200224 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600225 imply SPL_SERIAL
226 imply TPL_SERIAL
Kever Yang48831b22019-07-09 22:05:58 +0800227 imply TPL_ROCKCHIP_COMMON_BOARD
Andreas Färber9e3ad682017-05-15 17:51:18 +0800228 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200229 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
230 into a big and little cluster with 4 cores each) Cortex-A53 including
231 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
232 (for the little cluster), PowerVR G6110 based graphics, one video
233 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
234 video codec support.
235
236 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
237 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800238
Kever Yang0d3d7832016-07-19 21:16:59 +0800239config ROCKCHIP_RK3399
240 bool "Support Rockchip RK3399"
241 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800242 select SUPPORT_SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800243 select SUPPORT_TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800244 select SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530245 select SPL_ATF
Jagan Tekice063b92019-06-21 00:25:03 +0530246 select SPL_BOARD_INIT if SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530247 select SPL_LOAD_FIT
248 select SPL_CLK if SPL
249 select SPL_PINCTRL if SPL
250 select SPL_RAM if SPL
251 select SPL_REGMAP if SPL
252 select SPL_SYSCON if SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800253 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800254 select SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600255 select SPL_SERIAL
Jagan Tekicd433892019-05-08 11:11:43 +0530256 select CLK
257 select FIT
258 select PINCTRL
259 select RAM
260 select REGMAP
261 select SYSCON
262 select DM_PMIC
263 select DM_REGULATOR_FIXED
Andy Yan70378cb2017-10-11 15:00:16 +0800264 select BOARD_LATE_INIT
Jonas Karlman8b663722024-04-30 15:30:13 +0000265 imply ARMV8_CRYPTO
266 imply ARMV8_SET_SMPEN
Jonas Karlmana6389252024-04-30 15:30:12 +0000267 imply BOOTSTD_FULL
268 imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
Jonas Karlman0ad89712024-04-30 15:30:14 +0000269 imply DM_RNG
Jonas Karlman8b663722024-04-30 15:30:13 +0000270 imply LEGACY_IMAGE_FORMAT
Jonas Karlmana6389252024-04-30 15:30:12 +0000271 imply MISC
272 imply MISC_INIT_R
Jonas Karlman7f22b182024-04-30 15:30:16 +0000273 imply OF_LIBFDT_OVERLAY
Jonas Karlman8b663722024-04-30 15:30:13 +0000274 imply OF_LIVE
Jonas Karlman219b41a2024-05-04 19:42:57 +0000275 imply OF_UPSTREAM
Sughosh Ganuc1b8e8b2022-11-10 14:49:15 +0530276 imply PARTITION_TYPE_GUID
Jonas Karlman8660d332024-04-30 15:30:15 +0000277 imply PHY_GIGE if GMAC_ROCKCHIP
Jagan Teki9249d5c2020-04-02 17:11:23 +0530278 imply PRE_CONSOLE_BUFFER
Jonas Karlman0ad89712024-04-30 15:30:14 +0000279 imply RNG_ROCKCHIP
Kever Yang9554a4e2019-07-22 20:02:19 +0800280 imply ROCKCHIP_COMMON_BOARD
Jonas Karlmana6389252024-04-30 15:30:12 +0000281 imply ROCKCHIP_EFUSE
YouMin Chen23ae72e2019-11-15 11:04:45 +0800282 imply ROCKCHIP_SDRAM_COMMON
Jonas Karlman20e63412024-04-30 15:30:25 +0000283 imply SPL_DM_SEQ_ALIAS
Jonas Karlman8b663722024-04-30 15:30:13 +0000284 imply SPL_FIT_SIGNATURE
Kever Yangff9afe42019-07-22 19:59:42 +0800285 imply SPL_ROCKCHIP_COMMON_BOARD
Jonas Karlmana6389252024-04-30 15:30:12 +0000286 imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
287 imply TPL_CLK
288 imply TPL_DM
Kever Yangfca798d2018-11-09 11:18:15 +0800289 imply TPL_LIBCOMMON_SUPPORT
290 imply TPL_LIBGENERIC_SUPPORT
Kever Yangfca798d2018-11-09 11:18:15 +0800291 imply TPL_OF_CONTROL
Jonas Karlmana6389252024-04-30 15:30:12 +0000292 imply TPL_RAM
Kever Yangfca798d2018-11-09 11:18:15 +0800293 imply TPL_REGMAP
Jonas Karlmana6389252024-04-30 15:30:12 +0000294 imply TPL_ROCKCHIP_COMMON_BOARD
295 imply TPL_SERIAL
296 imply TPL_SYS_MALLOC_SIMPLE
Kever Yangfca798d2018-11-09 11:18:15 +0800297 imply TPL_SYSCON
Kever Yangfca798d2018-11-09 11:18:15 +0800298 imply TPL_TINY_MEMSET
Kever Yang0d3d7832016-07-19 21:16:59 +0800299 help
300 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
301 and quad-core Cortex-A53.
302 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
303 video interfaces supporting HDMI and eDP, several DDR3 options
304 and video codec support. Peripherals include Gigabit Ethernet,
305 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
306
Joseph Chen72cd8792021-06-02 15:58:25 +0800307config ROCKCHIP_RK3568
308 bool "Support Rockchip RK3568"
309 select ARM64
Nico Cheng00ceeb02021-10-26 10:42:19 +0800310 select SUPPORT_SPL
311 select SPL
Joseph Chen72cd8792021-06-02 15:58:25 +0800312 select CLK
313 select PINCTRL
314 select RAM
315 select REGMAP
316 select SYSCON
317 select BOARD_LATE_INIT
Manoj Saib34b19c2023-02-17 17:28:44 +0530318 select DM_REGULATOR_FIXED
Jagan Tekice0bbac2023-02-17 17:28:34 +0530319 select DM_RESET
Jonas Karlmanc1bb7122024-04-22 06:28:47 +0000320 imply BOOTSTD_FULL
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000321 imply DM_RNG
Jonas Karlmanbe56bb52023-02-22 22:44:41 +0000322 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000323 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000324 imply OF_LIBFDT_OVERLAY
Jonas Karlman737739e2024-05-04 19:43:00 +0000325 imply OF_UPSTREAM
Jonas Karlmane8b5bae2024-04-22 06:28:46 +0000326 imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000327 imply RNG_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000328 imply ROCKCHIP_COMMON_BOARD
329 imply ROCKCHIP_OTP
330 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000331 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Joseph Chen72cd8792021-06-02 15:58:25 +0800332 help
333 The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
334 including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
335 two video interfaces supporting HDMI and eDP, several DDR3 options
336 and video codec support. Peripherals include Gigabit Ethernet,
337 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
338
Jagan Teki8967dea2023-01-30 20:27:45 +0530339config ROCKCHIP_RK3588
340 bool "Support Rockchip RK3588"
341 select ARM64
342 select SUPPORT_SPL
343 select SPL
344 select CLK
345 select PINCTRL
346 select RAM
347 select REGMAP
348 select SYSCON
349 select BOARD_LATE_INIT
Jonas Karlman9bfd6512023-05-17 18:26:37 +0000350 select DM_REGULATOR_FIXED
351 select DM_RESET
Jonas Karlman0eb24592024-04-22 06:28:44 +0000352 imply BOOTSTD_FULL
353 imply CLK_SCMI
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000354 imply DM_RNG
Jonas Karlmaneeb19172023-02-22 22:44:41 +0000355 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000356 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000357 imply OF_LIBFDT_OVERLAY
Jonas Karlmane8b5bae2024-04-22 06:28:46 +0000358 imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000359 imply RNG_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000360 imply ROCKCHIP_COMMON_BOARD
361 imply ROCKCHIP_OTP
Jonas Karlmanfc805c22023-04-17 19:07:21 +0000362 imply SCMI_FIRMWARE
Jonas Karlman0eb24592024-04-22 06:28:44 +0000363 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
364 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Jagan Teki8967dea2023-01-30 20:27:45 +0530365 help
366 The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
367 quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
368 HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1,
369 SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet,
370 SDIO3.0 I2C, UART, SPI, GPIO and PWM.
371
Andy Yan2d982da2017-06-01 18:00:55 +0800372config ROCKCHIP_RV1108
373 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530374 select CPU_V7A
Kever Yanga2b336e2019-07-22 20:02:21 +0800375 imply ROCKCHIP_COMMON_BOARD
Andy Yan2d982da2017-06-01 18:00:55 +0800376 help
377 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
378 and a DSP.
379
Jagan Teki249a2382022-12-14 23:21:05 +0530380config ROCKCHIP_RV1126
381 bool "Support Rockchip RV1126"
382 select CPU_V7A
383 select SKIP_LOWLEVEL_INIT_ONLY
384 select TPL
385 select SUPPORT_TPL
386 select TPL_NEEDS_SEPARATE_STACK
387 select TPL_ROCKCHIP_BACK_TO_BROM
388 select SPL
389 select SUPPORT_SPL
390 select SPL_STACK_R
391 select CLK
392 select FIT
393 select PINCTRL
394 select RAM
395 select ROCKCHIP_SDRAM_COMMON
396 select REGMAP
397 select SYSCON
398 select DM_PMIC
399 select DM_REGULATOR_FIXED
400 select DM_RESET
401 select REGULATOR_RK8XX
402 select PMIC_RK8XX
403 select BOARD_LATE_INIT
404 imply ROCKCHIP_COMMON_BOARD
Tim Lunnd0812b22024-01-24 14:26:01 +1100405 select SPL_OPTEE_IMAGE if SPL_FIT
Jagan Tekid679f622023-07-29 19:11:42 +0530406 imply OF_LIBFDT_OVERLAY
Tim Lunncbfee492023-10-31 13:07:15 +1100407 imply ROCKCHIP_OTP
408 imply MISC_INIT_R
Jagan Teki249a2382022-12-14 23:21:05 +0530409 imply TPL_DM
410 imply TPL_LIBCOMMON_SUPPORT
411 imply TPL_LIBGENERIC_SUPPORT
412 imply TPL_OF_CONTROL
413 imply TPL_OF_PLATDATA
414 imply TPL_RAM
415 imply TPL_ROCKCHIP_COMMON_BOARD
416 imply TPL_SERIAL
417 imply SPL_CLK
418 imply SPL_DM
419 imply SPL_DRIVERS_MISC
420 imply SPL_LIBCOMMON_SUPPORT
421 imply SPL_LIBGENERIC_SUPPORT
422 imply SPL_OF_CONTROL
423 imply SPL_RAM
424 imply SPL_REGMAP
425 imply SPL_ROCKCHIP_COMMON_BOARD
426 imply SPL_SERIAL
427 imply SPL_SYSCON
428
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200429config ROCKCHIP_USB_UART
430 bool "Route uart output to usb pins"
431 help
432 Rockchip SoCs have the ability to route the signals of the debug
433 uart through the d+ and d- pins of a specific usb phy to enable
434 some form of closed-case debugging. With this option supported
435 SoCs will enable this routing as a debug measure.
436
Philipp Tomsich798370f2017-06-29 11:21:15 +0200437config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800438 bool "SPL returns to bootrom"
439 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100440 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800441 select SPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200442 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800443 help
444 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
445 SPL will return to the boot rom, which will then load the U-Boot
446 binary to keep going on.
447
Philipp Tomsich798370f2017-06-29 11:21:15 +0200448config TPL_ROCKCHIP_BACK_TO_BROM
449 bool "TPL returns to bootrom"
Kever Yangfca798d2018-11-09 11:18:15 +0800450 default y
Johan Jonkera768ff52023-10-27 20:35:37 +0200451 select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066
Kever Yangbd8532e2019-07-22 19:59:15 +0800452 select TPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200453 depends on TPL
454 help
455 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
456 SPL will return to the boot rom, which will then load the U-Boot
457 binary to keep going on.
458
Kever Yangbb337732019-07-22 20:02:01 +0800459config ROCKCHIP_COMMON_BOARD
460 bool "Rockchip common board file"
461 help
462 Rockchip SoCs have similar boot process, Common board file is mainly
463 in charge of common process of board_init() and board_late_init() for
464 U-Boot proper.
465
Kever Yang1d7cc72a2019-07-22 19:59:12 +0800466config SPL_ROCKCHIP_COMMON_BOARD
467 bool "Rockchip SPL common board file"
468 depends on SPL
469 help
470 Rockchip SoCs have similar boot process, SPL is mainly in charge of
471 load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
472 no TPL for the board.
473
Kever Yang34ead0f2019-07-09 22:05:55 +0800474config TPL_ROCKCHIP_COMMON_BOARD
Thomas Hebbcfbebf82019-12-20 18:05:22 -0800475 bool "Rockchip TPL common board file"
Kever Yang34ead0f2019-07-09 22:05:55 +0800476 depends on TPL
477 help
478 Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
479 init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
480 common board is a basic TPL board init which can be shared for most
Thomas Hebbfd37f242019-11-13 18:18:03 -0800481 of SoCs to avoid copy-paste for different SoCs.
Kever Yang34ead0f2019-07-09 22:05:55 +0800482
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000483config ROCKCHIP_EXTERNAL_TPL
484 bool "Use external TPL binary"
Massimo Pegorer8c20dfa2023-09-09 11:33:24 +0200485 default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000486 help
487 Some Rockchip SoCs require an external TPL to initialize DRAM.
488 Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
489 include the external TPL in the image built by binman.
490
Andy Yan70378cb2017-10-11 15:00:16 +0800491config ROCKCHIP_BOOT_MODE_REG
492 hex "Rockchip boot mode flag register address"
Andy Yan70378cb2017-10-11 15:00:16 +0800493 help
Kever Yang9fbe17c2019-03-28 11:01:23 +0800494 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yan70378cb2017-10-11 15:00:16 +0800495 according to the value from this register.
496
Chris Morgan7c9de742022-05-27 13:18:20 -0500497config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON
498 bool "Disable device boot on power plug-in"
499 depends on PMIC_RK8XX
Chris Morgan7c9de742022-05-27 13:18:20 -0500500 ---help---
501 Say Y here to prevent the device from booting up because of a plug-in
502 event. When set, the device will boot briefly to determine why it was
503 powered on, and if it was determined because of a plug-in event
504 instead of a button press event it will shut back off.
505
Johan Jonkerf6fc8952022-04-09 18:55:02 +0200506config ROCKCHIP_STIMER
507 bool "Rockchip STIMER support"
508 default y
509 help
510 Enable Rockchip STIMER support.
511
512config ROCKCHIP_STIMER_BASE
513 hex
514 depends on ROCKCHIP_STIMER
515
Kever Yange484f772017-04-20 17:03:46 +0800516config ROCKCHIP_SPL_RESERVE_IRAM
517 hex "Size of IRAM reserved in SPL"
Tom Rinif18679c2023-08-02 11:09:43 -0400518 default 0x0
Kever Yange484f772017-04-20 17:03:46 +0800519 help
520 SPL may need reserve memory for firmware loaded by SPL, whose load
521 address is in IRAM and may overlay with SPL text area if not
522 reserved.
523
Heiko Stübner355a8802017-02-18 19:46:25 +0100524config ROCKCHIP_BROM_HELPER
525 bool
526
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200527config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
528 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
529 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
530 help
531 Some Rockchip BROM variants (e.g. on the RK3188) load the
532 first stage in segments and enter multiple times. E.g. on
533 the RK3188, the first 1KB of the first stage are loaded
534 first and entered; after returning to the BROM, the
535 remainder of the first stage is loaded, but the BROM
536 re-enters at the same address/to the same code as previously.
537
538 This enables support code in the BOOT0 hook for the SPL stage
539 to allow multiple entries.
540
Quentin Schulz95b568f2024-03-11 13:01:54 +0100541config ROCKCHIP_DISABLE_FORCE_JTAG
542 bool "Disable force_jtag feature"
543 default y
544 depends on SPL
545 help
546 Rockchip SoCs can automatically switch between jtag and sdmmc based
547 on the following rules:
548 - all the SDMMC pins including SDMMC_DET set as SDMMC function in
549 GRF,
550 - force_jtag bit in GRF is 1,
551 - SDMMC_DET is low (no card detected),
552
553 Some HW design may not route the SD card card detect to SDMMC_DET
554 pin, thus breaking the SD card support in some cases because JTAG
555 would be auto-enabled by mistake.
556
557 Also, enabling JTAG at runtime may be an undesired feature, e.g.
558 because it could be a security vulnerability.
559
560 This disables force_jtag feature, which you may want for debugging
561 purposes.
562
563 If unsure, say Y.
564
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200565config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
566 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
567 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
568 help
569 Some Rockchip BROM variants (e.g. on the RK3188) load the
570 first stage in segments and enter multiple times. E.g. on
571 the RK3188, the first 1KB of the first stage are loaded
572 first and entered; after returning to the BROM, the
573 remainder of the first stage is loaded, but the BROM
574 re-enters at the same address/to the same code as previously.
575
576 This enables support code in the BOOT0 hook for the TPL stage
577 to allow multiple entries.
578
Simon Glassb58bfe02021-08-08 12:20:09 -0600579config SPL_MMC
Philipp Tomsich798370f2017-06-29 11:21:15 +0200580 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400581
Simon Glass88315f72020-07-19 13:55:57 -0600582config ROCKCHIP_SPI_IMAGE
583 bool "Build a SPI image for rockchip"
Simon Glass88315f72020-07-19 13:55:57 -0600584 help
585 Some Rockchip SoCs support booting from SPI flash. Enable this
Quentin Schulz12df9cf2022-09-02 15:10:54 +0200586 option to produce a SPI-flash image containing U-Boot. The image
587 is built by binman. U-Boot sits near the start of the image.
Simon Glass88315f72020-07-19 13:55:57 -0600588
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300589config LNX_KRNL_IMG_TEXT_OFFSET_BASE
Simon Glass72cc5382022-10-20 18:22:39 -0600590 default TEXT_BASE
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300591
Jonas Karlmane4453632024-03-02 19:16:11 +0000592config ROCKCHIP_COMMON_STACK_ADDR
593 bool
594 depends on SPL_SHARES_INIT_SP_ADDR
595 select HAS_CUSTOM_SYS_INIT_SP_ADDR
596 imply SPL_LIBCOMMON_SUPPORT if SPL
597 imply SPL_LIBGENERIC_SUPPORT if SPL
598 imply SPL_ROCKCHIP_COMMON_BOARD if SPL
599 imply SPL_SYS_MALLOC_F if SPL
600 imply SPL_SYS_MALLOC_SIMPLE if SPL
601 imply TPL_LIBCOMMON_SUPPORT if TPL
602 imply TPL_LIBGENERIC_SUPPORT if TPL
603 imply TPL_ROCKCHIP_COMMON_BOARD if TPL
604 imply TPL_SYS_MALLOC_F if TPL
605 imply TPL_SYS_MALLOC_SIMPLE if TPL
606
Quentin Schulzfb2d1ec2024-04-25 12:46:25 +0200607config NR_DRAM_BANKS
608 default 10 if ROCKCHIP_EXTERNAL_TPL
609
Heiko Stuebnerfc367852019-07-16 22:18:21 +0200610source "arch/arm/mach-rockchip/px30/Kconfig"
huang lin1115b642015-11-17 14:20:27 +0800611source "arch/arm/mach-rockchip/rk3036/Kconfig"
Johan Jonkera289fc72022-04-16 17:09:47 +0200612source "arch/arm/mach-rockchip/rk3066/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800613source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100614source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800615source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200616source "arch/arm/mach-rockchip/rk3288/Kconfig"
Andy Yanb5e16302019-11-14 11:21:12 +0800617source "arch/arm/mach-rockchip/rk3308/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800618source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800619source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800620source "arch/arm/mach-rockchip/rk3399/Kconfig"
Joseph Chen16899892021-06-02 16:13:46 +0800621source "arch/arm/mach-rockchip/rk3568/Kconfig"
Jagan Teki8967dea2023-01-30 20:27:45 +0530622source "arch/arm/mach-rockchip/rk3588/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800623source "arch/arm/mach-rockchip/rv1108/Kconfig"
Jagan Teki249a2382022-12-14 23:21:05 +0530624source "arch/arm/mach-rockchip/rv1126/Kconfig"
Jonas Karlmane4453632024-03-02 19:16:11 +0000625
626if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR
627
628config CUSTOM_SYS_INIT_SP_ADDR
629 default 0x3f00000
630
631config SYS_MALLOC_F_LEN
632 default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
633
634config SPL_SYS_MALLOC_F_LEN
635 default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
636
637config TPL_SYS_MALLOC_F_LEN
638 default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
639
640config TEXT_BASE
641 default 0x00200000 if ARM64
642
643config SPL_TEXT_BASE
644 default 0x0 if ARM64
645
646config SPL_HAS_BSS_LINKER_SECTION
647 default y if ARM64
648
649config SPL_BSS_START_ADDR
650 default 0x3f80000
651
652config SPL_BSS_MAX_SIZE
653 default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000
654
655config SPL_STACK_R
656 default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
657
658config SPL_STACK_R_ADDR
659 default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
660
661config SPL_STACK_R_MALLOC_SIMPLE_LEN
662 default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000
663
664endif
Simon Glass2cffe662015-08-30 16:55:38 -0600665endif