blob: fc1b638ff01d9e4886adc13c559fb64e5428e130 [file] [log] [blame]
Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stuebnerfc367852019-07-16 22:18:21 +02003config ROCKCHIP_PX30
4 bool "Support Rockchip PX30"
5 select ARM64
Quentin Schulz1e9fc7b2024-05-24 11:23:33 +02006 imply OF_UPSTREAM
Heiko Stuebnerfc367852019-07-16 22:18:21 +02007 select SUPPORT_SPL
8 select SUPPORT_TPL
9 select SPL
10 select TPL
11 select TPL_TINY_FRAMEWORK if TPL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020012 select TPL_NEEDS_SEPARATE_STACK if TPL
13 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -060014 select SPL_SERIAL
15 select TPL_SERIAL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020016 select DEBUG_UART_BOARD_INIT
17 imply ROCKCHIP_COMMON_BOARD
18 imply SPL_ROCKCHIP_COMMON_BOARD
Quentin Schulz99496082024-06-14 13:04:55 +020019 imply ARMV8_CRYPTO
20 imply ARMV8_SET_SMPEN
Heiko Stuebnerfc367852019-07-16 22:18:21 +020021 help
22 The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
23 including NEON and GPU, Mali-400 graphics, several DDR3 options
24 and video codec support. Peripherals include Gigabit Ethernet,
25 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
26
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020027config ROCKCHIP_RK3036
28 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053029 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +080030 select SUPPORT_SPL
31 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +080032 imply USB_FUNCTION_ROCKUSB
33 imply CMD_ROCKUSB
Kever Yang427cb672019-07-22 20:02:04 +080034 imply ROCKCHIP_COMMON_BOARD
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020035 help
36 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
37 including NEON and GPU, Mali-400 graphics, several DDR3 options
38 and video codec support. Peripherals include Gigabit Ethernet,
39 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
40
Johan Jonkera289fc72022-04-16 17:09:47 +020041config ROCKCHIP_RK3066
42 bool "Support Rockchip RK3066"
43 select CPU_V7A
44 select SPL_BOARD_INIT if SPL
45 select SUPPORT_SPL
46 select SUPPORT_TPL
47 select SPL
48 select TPL
49 select TPL_ROCKCHIP_BACK_TO_BROM
50 select TPL_ROCKCHIP_EARLYRETURN_TO_BROM
51 imply ROCKCHIP_COMMON_BOARD
52 imply SPL_ROCKCHIP_COMMON_BOARD
53 imply SPL_SERIAL
54 imply TPL_ROCKCHIP_COMMON_BOARD
55 imply TPL_SERIAL
56 help
57 The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
58 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
59 video interfaces, several memory options and video codec support.
60 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
61 UART, SPI, I2C and PWMs.
62
Kever Yangaa827752017-11-28 16:04:16 +080063config ROCKCHIP_RK3128
64 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053065 select CPU_V7A
Kever Yang96362722019-07-22 20:02:05 +080066 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa827752017-11-28 16:04:16 +080067 help
68 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
69 including NEON and GPU, Mali-400 graphics, several DDR3 options
70 and video codec support. Peripherals include Gigabit Ethernet,
71 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
72
Heiko Stübneref6db5e2017-02-18 19:46:36 +010073config ROCKCHIP_RK3188
74 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053075 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080076 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010077 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010078 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020079 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020080 select SPL_REGMAP
81 select SPL_SYSCON
82 select SPL_RAM
Simon Glass284cb9c2021-07-10 21:14:31 -060083 select SPL_DRIVERS_MISC
Philipp Tomsich16c689c2017-10-10 16:21:15 +020084 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangbd8532e2019-07-22 19:59:15 +080085 select SPL_ROCKCHIP_BACK_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020086 select BOARD_LATE_INIT
Kever Yangbfd3f872019-07-22 20:02:09 +080087 imply ROCKCHIP_COMMON_BOARD
Kever Yang3bd90402019-07-22 19:59:18 +080088 imply SPL_ROCKCHIP_COMMON_BOARD
Heiko Stübneref6db5e2017-02-18 19:46:36 +010089 help
90 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
91 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
92 video interfaces, several memory options and video codec support.
93 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
94 UART, SPI, I2C and PWMs.
95
Kever Yang57d4dbf2017-06-23 17:17:52 +080096config ROCKCHIP_RK322X
97 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053098 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080099 select SUPPORT_SPL
Kever Yangaff40c62019-04-02 20:41:24 +0800100 select SUPPORT_TPL
Kever Yang57d4dbf2017-06-23 17:17:52 +0800101 select SPL
Kever Yangaff40c62019-04-02 20:41:24 +0800102 select SPL_DM
103 select SPL_OF_LIBFDT
104 select TPL
105 select TPL_DM
106 select TPL_OF_LIBFDT
Kever Yangaff40c62019-04-02 20:41:24 +0800107 select TPL_NEEDS_SEPARATE_STACK if TPL
Simon Glass284cb9c2021-07-10 21:14:31 -0600108 select SPL_DRIVERS_MISC
Kever Yang0b517732019-07-22 20:02:07 +0800109 imply ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600110 imply SPL_SERIAL
Kever Yangd877fd22019-07-22 19:59:20 +0800111 imply SPL_ROCKCHIP_COMMON_BOARD
Alex Bee4fe31122023-07-18 16:57:13 +0200112 select SPL_OPTEE_IMAGE if SPL_FIT
Simon Glassf4d60392021-08-08 12:20:12 -0600113 imply TPL_SERIAL
Kever Yang466f3fd2019-07-09 22:05:56 +0800114 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +0800115 select TPL_LIBCOMMON_SUPPORT
116 select TPL_LIBGENERIC_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +0800117 help
118 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
119 including NEON and GPU, Mali-400 graphics, several DDR3 options
120 and video codec support. Peripherals include Gigabit Ethernet,
121 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
122
Simon Glass2cffe662015-08-30 16:55:38 -0600123config ROCKCHIP_RK3288
124 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530125 select CPU_V7A
John Keepingd5cb7712023-02-23 19:28:51 +0000126 select OF_SYSTEM_SETUP
Tom Rinie1e85442021-08-27 21:18:30 -0400127 select SKIP_LOWLEVEL_INIT_ONLY
Kever Yang0d3d7832016-07-19 21:16:59 +0800128 select SUPPORT_SPL
129 select SPL
Kever Yangf7c0a332019-07-02 11:43:05 +0800130 select SUPPORT_TPL
Johan Jonker9a26fb12023-12-27 13:06:47 +0100131 select FDT_64BIT
Jagan Teki7b7cc952020-01-23 19:42:19 +0530132 imply PRE_CONSOLE_BUFFER
Kever Yangba875012019-07-22 20:02:15 +0800133 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa67deb2019-07-22 19:59:27 +0800134 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +0800135 imply TPL_CLK
136 imply TPL_DM
Simon Glass284cb9c2021-07-10 21:14:31 -0600137 imply TPL_DRIVERS_MISC
Kever Yangf7c0a332019-07-02 11:43:05 +0800138 imply TPL_LIBCOMMON_SUPPORT
139 imply TPL_LIBGENERIC_SUPPORT
Kever Yangb36e7092019-07-02 11:43:06 +0800140 imply TPL_NEEDS_SEPARATE_STACK
Kever Yangf7c0a332019-07-02 11:43:05 +0800141 imply TPL_OF_CONTROL
142 imply TPL_OF_PLATDATA
143 imply TPL_RAM
144 imply TPL_REGMAP
Kever Yange32f38e2019-07-09 22:05:57 +0800145 imply TPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600146 imply TPL_SERIAL
Kever Yangf7c0a332019-07-02 11:43:05 +0800147 imply TPL_SYSCON
Eddie Caib3501fe2017-12-15 08:17:13 +0800148 imply USB_FUNCTION_ROCKUSB
149 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -0600150 help
151 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
152 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
153 video interfaces supporting HDMI and eDP, several DDR3 options
154 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +0100155 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -0600156
Andy Yanb5e16302019-11-14 11:21:12 +0800157config ROCKCHIP_RK3308
158 bool "Support Rockchip RK3308"
159 select ARM64
Andy Yanb5e16302019-11-14 11:21:12 +0800160 select SUPPORT_SPL
161 select SUPPORT_TPL
162 select SPL
163 select SPL_ATF
164 select SPL_ATF_NO_PLATFORM_PARAM
165 select SPL_LOAD_FIT
Jonas Karlmana2caa162024-04-08 18:14:00 +0000166 imply ARMV8_CRYPTO
167 imply ARMV8_SET_SMPEN
Jonas Karlmanfbced692024-04-08 18:14:02 +0000168 imply DM_RNG
Jonas Karlmana2caa162024-04-08 18:14:00 +0000169 imply LEGACY_IMAGE_FORMAT
Jonas Karlman1cf34dd2024-04-08 18:14:01 +0000170 imply MISC
171 imply MISC_INIT_R
FUKAUMI Naokif429bb92024-07-17 13:47:26 +0900172 imply OF_LIBFDT_OVERLAY
Jonas Karlman0cab3c52024-05-04 19:42:53 +0000173 imply OF_UPSTREAM
Jonas Karlmanfbced692024-04-08 18:14:02 +0000174 imply RNG_ROCKCHIP
Andy Yanb5e16302019-11-14 11:21:12 +0800175 imply ROCKCHIP_COMMON_BOARD
Jonas Karlman1cf34dd2024-04-08 18:14:01 +0000176 imply ROCKCHIP_OTP
Andy Yanb5e16302019-11-14 11:21:12 +0800177 imply SPL_CLK
Jonas Karlmana499c982024-04-08 18:14:03 +0000178 imply SPL_DM_SEQ_ALIAS
Jonas Karlmana2caa162024-04-08 18:14:00 +0000179 imply SPL_FIT_SIGNATURE
Jonas Karlmana499c982024-04-08 18:14:03 +0000180 imply SPL_PINCTRL
Andy Yanb5e16302019-11-14 11:21:12 +0800181 imply SPL_RAM
Jonas Karlman16b0f902024-04-08 18:13:59 +0000182 imply SPL_REGMAP
183 imply SPL_ROCKCHIP_COMMON_BOARD
Andy Yanb5e16302019-11-14 11:21:12 +0800184 imply SPL_SEPARATE_BSS
Jonas Karlman16b0f902024-04-08 18:13:59 +0000185 imply SPL_SERIAL
186 imply SPL_SYSCON
Andy Yanb5e16302019-11-14 11:21:12 +0800187 help
188 The Rockchip RK3308 is a ARM-based Soc which embedded with quad
189 Cortex-A35 and highly integrated audio interfaces.
190
Kever Yangec02b3c2017-02-23 15:37:51 +0800191config ROCKCHIP_RK3328
192 bool "Support Rockchip RK3328"
193 select ARM64
Kever Yang07be6692019-06-09 00:27:15 +0300194 select SUPPORT_SPL
195 select SPL
Kever Yang69871852019-08-02 10:40:01 +0300196 select SUPPORT_TPL
197 select TPL
Kever Yang69871852019-08-02 10:40:01 +0300198 select TPL_NEEDS_SEPARATE_STACK if TPL
Jonas Karlman1b3d9dd2024-04-21 20:09:02 +0000199 imply ARMV8_CRYPTO
200 imply ARMV8_SET_SMPEN
Jonas Karlman86d4ebb2024-04-21 20:09:01 +0000201 imply MISC
202 imply MISC_INIT_R
FUKAUMI Naokif429bb92024-07-17 13:47:26 +0900203 imply OF_LIBFDT_OVERLAY
Jonas Karlman1b3d9dd2024-04-21 20:09:02 +0000204 imply OF_LIVE
Jonas Karlmaned6f48e2024-05-04 19:42:55 +0000205 imply OF_UPSTREAM
Jagan Tekifb71c882024-01-17 13:21:52 +0530206 imply PRE_CONSOLE_BUFFER
Kever Yang205e2cc2019-07-22 20:02:16 +0800207 imply ROCKCHIP_COMMON_BOARD
Jonas Karlman86d4ebb2024-04-21 20:09:01 +0000208 imply ROCKCHIP_EFUSE
YouMin Chenb9f7df32019-11-15 11:04:44 +0800209 imply ROCKCHIP_SDRAM_COMMON
Kever Yangbb4c3252019-07-22 19:59:32 +0800210 imply SPL_ROCKCHIP_COMMON_BOARD
Jonas Karlman86d4ebb2024-04-21 20:09:01 +0000211 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600212 imply SPL_SERIAL
213 imply TPL_SERIAL
Kever Yangec02b3c2017-02-23 15:37:51 +0800214 help
215 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
216 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
217 video interfaces supporting HDMI and eDP, several DDR3 options
218 and video codec support. Peripherals include Gigabit Ethernet,
219 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
220
Andreas Färber9e3ad682017-05-15 17:51:18 +0800221config ROCKCHIP_RK3368
222 bool "Support Rockchip RK3368"
223 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200224 select SUPPORT_SPL
225 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200226 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang35b401e2019-07-22 20:02:17 +0800227 imply ROCKCHIP_COMMON_BOARD
Kever Yang8bf7ed42019-07-22 19:59:34 +0800228 imply SPL_ROCKCHIP_COMMON_BOARD
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200229 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600230 imply SPL_SERIAL
231 imply TPL_SERIAL
Kever Yang48831b22019-07-09 22:05:58 +0800232 imply TPL_ROCKCHIP_COMMON_BOARD
Andreas Färber9e3ad682017-05-15 17:51:18 +0800233 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200234 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
235 into a big and little cluster with 4 cores each) Cortex-A53 including
236 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
237 (for the little cluster), PowerVR G6110 based graphics, one video
238 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
239 video codec support.
240
241 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
242 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800243
Kever Yang0d3d7832016-07-19 21:16:59 +0800244config ROCKCHIP_RK3399
245 bool "Support Rockchip RK3399"
246 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800247 select SUPPORT_SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800248 select SUPPORT_TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800249 select SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530250 select SPL_ATF
Jagan Tekice063b92019-06-21 00:25:03 +0530251 select SPL_BOARD_INIT if SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530252 select SPL_LOAD_FIT
253 select SPL_CLK if SPL
254 select SPL_PINCTRL if SPL
255 select SPL_RAM if SPL
256 select SPL_REGMAP if SPL
257 select SPL_SYSCON if SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800258 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800259 select SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600260 select SPL_SERIAL
Jagan Tekicd433892019-05-08 11:11:43 +0530261 select CLK
262 select FIT
263 select PINCTRL
264 select RAM
265 select REGMAP
266 select SYSCON
267 select DM_PMIC
268 select DM_REGULATOR_FIXED
Andy Yan70378cb2017-10-11 15:00:16 +0800269 select BOARD_LATE_INIT
Jonas Karlman8b663722024-04-30 15:30:13 +0000270 imply ARMV8_CRYPTO
271 imply ARMV8_SET_SMPEN
Jonas Karlmana6389252024-04-30 15:30:12 +0000272 imply BOOTSTD_FULL
273 imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
Jonas Karlman0ad89712024-04-30 15:30:14 +0000274 imply DM_RNG
Jonas Karlman8b663722024-04-30 15:30:13 +0000275 imply LEGACY_IMAGE_FORMAT
Jonas Karlmana6389252024-04-30 15:30:12 +0000276 imply MISC
277 imply MISC_INIT_R
Jonas Karlman7f22b182024-04-30 15:30:16 +0000278 imply OF_LIBFDT_OVERLAY
Jonas Karlman8b663722024-04-30 15:30:13 +0000279 imply OF_LIVE
Jonas Karlman219b41a2024-05-04 19:42:57 +0000280 imply OF_UPSTREAM
Sughosh Ganuc1b8e8b2022-11-10 14:49:15 +0530281 imply PARTITION_TYPE_GUID
Jonas Karlman8660d332024-04-30 15:30:15 +0000282 imply PHY_GIGE if GMAC_ROCKCHIP
Jagan Teki9249d5c2020-04-02 17:11:23 +0530283 imply PRE_CONSOLE_BUFFER
Jonas Karlman0ad89712024-04-30 15:30:14 +0000284 imply RNG_ROCKCHIP
Kever Yang9554a4e2019-07-22 20:02:19 +0800285 imply ROCKCHIP_COMMON_BOARD
Jonas Karlmana6389252024-04-30 15:30:12 +0000286 imply ROCKCHIP_EFUSE
YouMin Chen23ae72e2019-11-15 11:04:45 +0800287 imply ROCKCHIP_SDRAM_COMMON
Jonas Karlman20e63412024-04-30 15:30:25 +0000288 imply SPL_DM_SEQ_ALIAS
Jonas Karlman8b663722024-04-30 15:30:13 +0000289 imply SPL_FIT_SIGNATURE
Kever Yangff9afe42019-07-22 19:59:42 +0800290 imply SPL_ROCKCHIP_COMMON_BOARD
Jonas Karlmana6389252024-04-30 15:30:12 +0000291 imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
292 imply TPL_CLK
293 imply TPL_DM
Kever Yangfca798d2018-11-09 11:18:15 +0800294 imply TPL_LIBCOMMON_SUPPORT
295 imply TPL_LIBGENERIC_SUPPORT
Kever Yangfca798d2018-11-09 11:18:15 +0800296 imply TPL_OF_CONTROL
Jonas Karlmana6389252024-04-30 15:30:12 +0000297 imply TPL_RAM
Kever Yangfca798d2018-11-09 11:18:15 +0800298 imply TPL_REGMAP
Jonas Karlmana6389252024-04-30 15:30:12 +0000299 imply TPL_ROCKCHIP_COMMON_BOARD
300 imply TPL_SERIAL
301 imply TPL_SYS_MALLOC_SIMPLE
Kever Yangfca798d2018-11-09 11:18:15 +0800302 imply TPL_SYSCON
Kever Yangfca798d2018-11-09 11:18:15 +0800303 imply TPL_TINY_MEMSET
Kever Yang0d3d7832016-07-19 21:16:59 +0800304 help
305 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
306 and quad-core Cortex-A53.
307 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
308 video interfaces supporting HDMI and eDP, several DDR3 options
309 and video codec support. Peripherals include Gigabit Ethernet,
310 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
311
Joseph Chen72cd8792021-06-02 15:58:25 +0800312config ROCKCHIP_RK3568
313 bool "Support Rockchip RK3568"
314 select ARM64
Nico Cheng00ceeb02021-10-26 10:42:19 +0800315 select SUPPORT_SPL
316 select SPL
Joseph Chen72cd8792021-06-02 15:58:25 +0800317 select CLK
318 select PINCTRL
319 select RAM
320 select REGMAP
321 select SYSCON
322 select BOARD_LATE_INIT
Manoj Saib34b19c2023-02-17 17:28:44 +0530323 select DM_REGULATOR_FIXED
Jagan Tekice0bbac2023-02-17 17:28:34 +0530324 select DM_RESET
Jonas Karlmanc1bb7122024-04-22 06:28:47 +0000325 imply BOOTSTD_FULL
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000326 imply DM_RNG
Jonas Karlmanbe56bb52023-02-22 22:44:41 +0000327 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000328 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000329 imply OF_LIBFDT_OVERLAY
Jonas Karlman737739e2024-05-04 19:43:00 +0000330 imply OF_UPSTREAM
Jonas Karlmane8b5bae2024-04-22 06:28:46 +0000331 imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000332 imply RNG_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000333 imply ROCKCHIP_COMMON_BOARD
334 imply ROCKCHIP_OTP
335 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000336 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Joseph Chen72cd8792021-06-02 15:58:25 +0800337 help
338 The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
339 including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
340 two video interfaces supporting HDMI and eDP, several DDR3 options
341 and video codec support. Peripherals include Gigabit Ethernet,
342 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
343
Jagan Teki8967dea2023-01-30 20:27:45 +0530344config ROCKCHIP_RK3588
345 bool "Support Rockchip RK3588"
346 select ARM64
347 select SUPPORT_SPL
348 select SPL
349 select CLK
350 select PINCTRL
351 select RAM
352 select REGMAP
353 select SYSCON
354 select BOARD_LATE_INIT
Jonas Karlman9bfd6512023-05-17 18:26:37 +0000355 select DM_REGULATOR_FIXED
356 select DM_RESET
Jonas Karlman0eb24592024-04-22 06:28:44 +0000357 imply BOOTSTD_FULL
358 imply CLK_SCMI
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000359 imply DM_RNG
Jonas Karlmaneeb19172023-02-22 22:44:41 +0000360 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000361 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000362 imply OF_LIBFDT_OVERLAY
Jonas Karlman45be8102024-05-04 19:43:07 +0000363 imply OF_UPSTREAM
Jonas Karlmane8b5bae2024-04-22 06:28:46 +0000364 imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000365 imply RNG_ROCKCHIP
Jonas Karlman0eb24592024-04-22 06:28:44 +0000366 imply ROCKCHIP_COMMON_BOARD
367 imply ROCKCHIP_OTP
Jonas Karlmanfc805c22023-04-17 19:07:21 +0000368 imply SCMI_FIRMWARE
Jonas Karlman0eb24592024-04-22 06:28:44 +0000369 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
370 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Jagan Teki8967dea2023-01-30 20:27:45 +0530371 help
372 The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
373 quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
374 HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1,
375 SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet,
376 SDIO3.0 I2C, UART, SPI, GPIO and PWM.
377
Andy Yan2d982da2017-06-01 18:00:55 +0800378config ROCKCHIP_RV1108
379 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530380 select CPU_V7A
Kever Yanga2b336e2019-07-22 20:02:21 +0800381 imply ROCKCHIP_COMMON_BOARD
Fabio Estevam09df3632024-04-24 11:18:41 -0300382 imply OF_UPSTREAM
Andy Yan2d982da2017-06-01 18:00:55 +0800383 help
384 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
385 and a DSP.
386
Jagan Teki249a2382022-12-14 23:21:05 +0530387config ROCKCHIP_RV1126
388 bool "Support Rockchip RV1126"
389 select CPU_V7A
390 select SKIP_LOWLEVEL_INIT_ONLY
391 select TPL
392 select SUPPORT_TPL
393 select TPL_NEEDS_SEPARATE_STACK
394 select TPL_ROCKCHIP_BACK_TO_BROM
395 select SPL
396 select SUPPORT_SPL
397 select SPL_STACK_R
398 select CLK
399 select FIT
400 select PINCTRL
401 select RAM
402 select ROCKCHIP_SDRAM_COMMON
403 select REGMAP
404 select SYSCON
405 select DM_PMIC
406 select DM_REGULATOR_FIXED
407 select DM_RESET
408 select REGULATOR_RK8XX
409 select PMIC_RK8XX
410 select BOARD_LATE_INIT
411 imply ROCKCHIP_COMMON_BOARD
Tim Lunnd0812b22024-01-24 14:26:01 +1100412 select SPL_OPTEE_IMAGE if SPL_FIT
Jagan Tekid679f622023-07-29 19:11:42 +0530413 imply OF_LIBFDT_OVERLAY
Tim Lunncbfee492023-10-31 13:07:15 +1100414 imply ROCKCHIP_OTP
415 imply MISC_INIT_R
Jagan Teki249a2382022-12-14 23:21:05 +0530416 imply TPL_DM
417 imply TPL_LIBCOMMON_SUPPORT
418 imply TPL_LIBGENERIC_SUPPORT
419 imply TPL_OF_CONTROL
420 imply TPL_OF_PLATDATA
421 imply TPL_RAM
422 imply TPL_ROCKCHIP_COMMON_BOARD
423 imply TPL_SERIAL
424 imply SPL_CLK
425 imply SPL_DM
426 imply SPL_DRIVERS_MISC
427 imply SPL_LIBCOMMON_SUPPORT
428 imply SPL_LIBGENERIC_SUPPORT
429 imply SPL_OF_CONTROL
430 imply SPL_RAM
431 imply SPL_REGMAP
432 imply SPL_ROCKCHIP_COMMON_BOARD
433 imply SPL_SERIAL
434 imply SPL_SYSCON
Anand Moon00c92fe2024-05-14 09:35:22 +0530435 imply OF_UPSTREAM
Jagan Teki249a2382022-12-14 23:21:05 +0530436
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200437config ROCKCHIP_USB_UART
438 bool "Route uart output to usb pins"
439 help
440 Rockchip SoCs have the ability to route the signals of the debug
441 uart through the d+ and d- pins of a specific usb phy to enable
442 some form of closed-case debugging. With this option supported
443 SoCs will enable this routing as a debug measure.
444
Philipp Tomsich798370f2017-06-29 11:21:15 +0200445config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800446 bool "SPL returns to bootrom"
447 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100448 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800449 select SPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200450 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800451 help
452 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
453 SPL will return to the boot rom, which will then load the U-Boot
454 binary to keep going on.
455
Philipp Tomsich798370f2017-06-29 11:21:15 +0200456config TPL_ROCKCHIP_BACK_TO_BROM
457 bool "TPL returns to bootrom"
Kever Yangfca798d2018-11-09 11:18:15 +0800458 default y
Johan Jonkera768ff52023-10-27 20:35:37 +0200459 select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066
Kever Yangbd8532e2019-07-22 19:59:15 +0800460 select TPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200461 depends on TPL
462 help
463 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
464 SPL will return to the boot rom, which will then load the U-Boot
465 binary to keep going on.
466
Kever Yangbb337732019-07-22 20:02:01 +0800467config ROCKCHIP_COMMON_BOARD
468 bool "Rockchip common board file"
469 help
470 Rockchip SoCs have similar boot process, Common board file is mainly
471 in charge of common process of board_init() and board_late_init() for
472 U-Boot proper.
473
Kever Yang1d7cc72a2019-07-22 19:59:12 +0800474config SPL_ROCKCHIP_COMMON_BOARD
475 bool "Rockchip SPL common board file"
476 depends on SPL
477 help
478 Rockchip SoCs have similar boot process, SPL is mainly in charge of
479 load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
480 no TPL for the board.
481
Kever Yang34ead0f2019-07-09 22:05:55 +0800482config TPL_ROCKCHIP_COMMON_BOARD
Thomas Hebbcfbebf82019-12-20 18:05:22 -0800483 bool "Rockchip TPL common board file"
Kever Yang34ead0f2019-07-09 22:05:55 +0800484 depends on TPL
485 help
486 Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
487 init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
488 common board is a basic TPL board init which can be shared for most
Thomas Hebbfd37f242019-11-13 18:18:03 -0800489 of SoCs to avoid copy-paste for different SoCs.
Kever Yang34ead0f2019-07-09 22:05:55 +0800490
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000491config ROCKCHIP_EXTERNAL_TPL
492 bool "Use external TPL binary"
Massimo Pegorer8c20dfa2023-09-09 11:33:24 +0200493 default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000494 help
495 Some Rockchip SoCs require an external TPL to initialize DRAM.
496 Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
497 include the external TPL in the image built by binman.
498
Andy Yan70378cb2017-10-11 15:00:16 +0800499config ROCKCHIP_BOOT_MODE_REG
500 hex "Rockchip boot mode flag register address"
Andy Yan70378cb2017-10-11 15:00:16 +0800501 help
Kever Yang9fbe17c2019-03-28 11:01:23 +0800502 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yan70378cb2017-10-11 15:00:16 +0800503 according to the value from this register.
504
Chris Morgan7c9de742022-05-27 13:18:20 -0500505config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON
506 bool "Disable device boot on power plug-in"
507 depends on PMIC_RK8XX
Chris Morgan7c9de742022-05-27 13:18:20 -0500508 ---help---
509 Say Y here to prevent the device from booting up because of a plug-in
510 event. When set, the device will boot briefly to determine why it was
511 powered on, and if it was determined because of a plug-in event
512 instead of a button press event it will shut back off.
513
Johan Jonkerf6fc8952022-04-09 18:55:02 +0200514config ROCKCHIP_STIMER
515 bool "Rockchip STIMER support"
516 default y
517 help
518 Enable Rockchip STIMER support.
519
520config ROCKCHIP_STIMER_BASE
521 hex
522 depends on ROCKCHIP_STIMER
523
Kever Yange484f772017-04-20 17:03:46 +0800524config ROCKCHIP_SPL_RESERVE_IRAM
525 hex "Size of IRAM reserved in SPL"
Tom Rinif18679c2023-08-02 11:09:43 -0400526 default 0x0
Kever Yange484f772017-04-20 17:03:46 +0800527 help
528 SPL may need reserve memory for firmware loaded by SPL, whose load
529 address is in IRAM and may overlay with SPL text area if not
530 reserved.
531
Heiko Stübner355a8802017-02-18 19:46:25 +0100532config ROCKCHIP_BROM_HELPER
533 bool
534
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200535config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
536 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
537 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
538 help
539 Some Rockchip BROM variants (e.g. on the RK3188) load the
540 first stage in segments and enter multiple times. E.g. on
541 the RK3188, the first 1KB of the first stage are loaded
542 first and entered; after returning to the BROM, the
543 remainder of the first stage is loaded, but the BROM
544 re-enters at the same address/to the same code as previously.
545
546 This enables support code in the BOOT0 hook for the SPL stage
547 to allow multiple entries.
548
Quentin Schulz95b568f2024-03-11 13:01:54 +0100549config ROCKCHIP_DISABLE_FORCE_JTAG
550 bool "Disable force_jtag feature"
551 default y
552 depends on SPL
553 help
554 Rockchip SoCs can automatically switch between jtag and sdmmc based
555 on the following rules:
556 - all the SDMMC pins including SDMMC_DET set as SDMMC function in
557 GRF,
558 - force_jtag bit in GRF is 1,
559 - SDMMC_DET is low (no card detected),
560
561 Some HW design may not route the SD card card detect to SDMMC_DET
562 pin, thus breaking the SD card support in some cases because JTAG
563 would be auto-enabled by mistake.
564
565 Also, enabling JTAG at runtime may be an undesired feature, e.g.
566 because it could be a security vulnerability.
567
568 This disables force_jtag feature, which you may want for debugging
569 purposes.
570
571 If unsure, say Y.
572
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200573config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
574 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
575 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
576 help
577 Some Rockchip BROM variants (e.g. on the RK3188) load the
578 first stage in segments and enter multiple times. E.g. on
579 the RK3188, the first 1KB of the first stage are loaded
580 first and entered; after returning to the BROM, the
581 remainder of the first stage is loaded, but the BROM
582 re-enters at the same address/to the same code as previously.
583
584 This enables support code in the BOOT0 hook for the TPL stage
585 to allow multiple entries.
586
Simon Glassb58bfe02021-08-08 12:20:09 -0600587config SPL_MMC
Philipp Tomsich798370f2017-06-29 11:21:15 +0200588 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400589
Simon Glass88315f72020-07-19 13:55:57 -0600590config ROCKCHIP_SPI_IMAGE
591 bool "Build a SPI image for rockchip"
Simon Glass88315f72020-07-19 13:55:57 -0600592 help
593 Some Rockchip SoCs support booting from SPI flash. Enable this
Quentin Schulz12df9cf2022-09-02 15:10:54 +0200594 option to produce a SPI-flash image containing U-Boot. The image
595 is built by binman. U-Boot sits near the start of the image.
Simon Glass88315f72020-07-19 13:55:57 -0600596
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300597config LNX_KRNL_IMG_TEXT_OFFSET_BASE
Simon Glass72cc5382022-10-20 18:22:39 -0600598 default TEXT_BASE
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300599
Jonas Karlmane4453632024-03-02 19:16:11 +0000600config ROCKCHIP_COMMON_STACK_ADDR
601 bool
602 depends on SPL_SHARES_INIT_SP_ADDR
603 select HAS_CUSTOM_SYS_INIT_SP_ADDR
604 imply SPL_LIBCOMMON_SUPPORT if SPL
605 imply SPL_LIBGENERIC_SUPPORT if SPL
606 imply SPL_ROCKCHIP_COMMON_BOARD if SPL
607 imply SPL_SYS_MALLOC_F if SPL
608 imply SPL_SYS_MALLOC_SIMPLE if SPL
609 imply TPL_LIBCOMMON_SUPPORT if TPL
610 imply TPL_LIBGENERIC_SUPPORT if TPL
611 imply TPL_ROCKCHIP_COMMON_BOARD if TPL
612 imply TPL_SYS_MALLOC_F if TPL
613 imply TPL_SYS_MALLOC_SIMPLE if TPL
614
Quentin Schulzfb2d1ec2024-04-25 12:46:25 +0200615config NR_DRAM_BANKS
616 default 10 if ROCKCHIP_EXTERNAL_TPL
617
Heiko Stuebnerfc367852019-07-16 22:18:21 +0200618source "arch/arm/mach-rockchip/px30/Kconfig"
huang lin1115b642015-11-17 14:20:27 +0800619source "arch/arm/mach-rockchip/rk3036/Kconfig"
Johan Jonkera289fc72022-04-16 17:09:47 +0200620source "arch/arm/mach-rockchip/rk3066/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800621source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100622source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800623source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200624source "arch/arm/mach-rockchip/rk3288/Kconfig"
Andy Yanb5e16302019-11-14 11:21:12 +0800625source "arch/arm/mach-rockchip/rk3308/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800626source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800627source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800628source "arch/arm/mach-rockchip/rk3399/Kconfig"
Joseph Chen16899892021-06-02 16:13:46 +0800629source "arch/arm/mach-rockchip/rk3568/Kconfig"
Jagan Teki8967dea2023-01-30 20:27:45 +0530630source "arch/arm/mach-rockchip/rk3588/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800631source "arch/arm/mach-rockchip/rv1108/Kconfig"
Jagan Teki249a2382022-12-14 23:21:05 +0530632source "arch/arm/mach-rockchip/rv1126/Kconfig"
Jonas Karlmane4453632024-03-02 19:16:11 +0000633
634if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR
635
636config CUSTOM_SYS_INIT_SP_ADDR
637 default 0x3f00000
638
639config SYS_MALLOC_F_LEN
640 default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
641
642config SPL_SYS_MALLOC_F_LEN
643 default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
644
645config TPL_SYS_MALLOC_F_LEN
646 default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
647
648config TEXT_BASE
649 default 0x00200000 if ARM64
650
651config SPL_TEXT_BASE
652 default 0x0 if ARM64
653
654config SPL_HAS_BSS_LINKER_SECTION
655 default y if ARM64
656
657config SPL_BSS_START_ADDR
658 default 0x3f80000
659
660config SPL_BSS_MAX_SIZE
661 default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000
662
663config SPL_STACK_R
664 default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
665
666config SPL_STACK_R_ADDR
667 default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
668
669config SPL_STACK_R_MALLOC_SIMPLE_LEN
670 default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000
671
672endif
Simon Glass2cffe662015-08-30 16:55:38 -0600673endif