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Paul Beesleyfc9ee362019-03-07 15:47:15 +00001Porting Guide
2=============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Douglas Raillardd7c21b72017-06-28 15:23:03 +01004Introduction
5------------
6
Dan Handley610e7e12018-03-01 18:44:00 +00007Porting Trusted Firmware-A (TF-A) to a new platform involves making some
Douglas Raillardd7c21b72017-06-28 15:23:03 +01008mandatory and optional modifications for both the cold and warm boot paths.
9Modifications consist of:
10
11- Implementing a platform-specific function or variable,
12- Setting up the execution context in a certain way, or
13- Defining certain constants (for example #defines).
14
15The platform-specific functions and variables are declared in
Paul Beesleyf8640672019-04-12 14:19:42 +010016``include/plat/common/platform.h``. The firmware provides a default
Sandrine Bailleux7a53a912023-02-08 13:55:51 +010017implementation of variables and functions to fulfill the optional requirements
18in order to ease the porting effort. Each platform port can use them as is or
19provide their own implementation if the default implementation is inadequate.
20
21 .. note::
22
23 TF-A historically provided default implementations of platform interfaces
24 as *weak* functions. This practice is now discouraged and new platform
25 interfaces as they get introduced in the code base should be *strongly*
26 defined. We intend to convert existing weak functions over time. Until
27 then, you will find references to *weak* functions in this document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010028
Sandrine Bailleux2cea7942023-04-04 16:36:08 +020029Please review the :ref:`Threat Model` documents as part of the porting
30effort. Some platform interfaces play a key role in mitigating against some of
31the threats. Failing to fulfill these expectations could undermine the security
32guarantees offered by TF-A. These platform responsibilities are highlighted in
33the threat assessment section, under the "`Mitigations implemented?`" box for
34each threat.
35
Douglas Raillardd7c21b72017-06-28 15:23:03 +010036Some modifications are common to all Boot Loader (BL) stages. Section 2
37discusses these in detail. The subsequent sections discuss the remaining
38modifications for each BL stage in detail.
39
Sandrine Bailleuxdad35612022-11-08 13:36:42 +010040Please refer to the :ref:`Platform Ports Policy` for the policy regarding
41compatibility and deprecation of these porting interfaces.
Soby Mathew02bdbb92018-09-26 11:17:23 +010042
Antonio Nino Diaz645feb42019-02-13 14:07:38 +000043Only Arm development platforms (such as FVP and Juno) may use the
44functions/definitions in ``include/plat/arm/common/`` and the corresponding
45source files in ``plat/arm/common/``. This is done so that there are no
46dependencies between platforms maintained by different people/companies. If you
47want to use any of the functionality present in ``plat/arm`` files, please
Sandrine Bailleux8a1c0d62023-02-08 14:01:18 +010048propose a patch that moves the code to ``plat/common`` so that it can be
Antonio Nino Diaz645feb42019-02-13 14:07:38 +000049discussed.
50
Douglas Raillardd7c21b72017-06-28 15:23:03 +010051Common modifications
52--------------------
53
54This section covers the modifications that should be made by the platform for
55each BL stage to correctly port the firmware stack. They are categorized as
56either mandatory or optional.
57
58Common mandatory modifications
59------------------------------
60
61A platform port must enable the Memory Management Unit (MMU) as well as the
62instruction and data caches for each BL stage. Setting up the translation
63tables is the responsibility of the platform port because memory maps differ
Sandrine Bailleux6d981f72023-02-08 14:02:45 +010064across platforms. A memory translation library (see ``lib/xlat_tables_v2/``) is
Sandrine Bailleux1861b7a2017-07-20 16:11:01 +010065provided to help in this setup.
66
67Note that although this library supports non-identity mappings, this is intended
68only for re-mapping peripheral physical addresses and allows platforms with high
69I/O addresses to reduce their virtual address space. All other addresses
70corresponding to code and data must currently use an identity mapping.
71
Dan Handley610e7e12018-03-01 18:44:00 +000072Also, the only translation granule size supported in TF-A is 4KB, as various
73parts of the code assume that is the case. It is not possible to switch to
7416 KB or 64 KB granule sizes at the moment.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010075
Dan Handley610e7e12018-03-01 18:44:00 +000076In Arm standard platforms, each BL stage configures the MMU in the
Douglas Raillardd7c21b72017-06-28 15:23:03 +010077platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses
78an identity mapping for all addresses.
79
80If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a
81block of identity mapped secure memory with Device-nGnRE attributes aligned to
82page boundary (4K) for each BL stage. All sections which allocate coherent
Chris Kay33bfc5e2023-02-14 11:30:04 +000083memory are grouped under ``.coherent_ram``. For ex: Bakery locks are placed in a
84section identified by name ``.bakery_lock`` inside ``.coherent_ram`` so that its
Douglas Raillardd7c21b72017-06-28 15:23:03 +010085possible for the firmware to place variables in it using the following C code
86directive:
87
88::
89
Chris Kay33bfc5e2023-02-14 11:30:04 +000090 __section(".bakery_lock")
Douglas Raillardd7c21b72017-06-28 15:23:03 +010091
92Or alternatively the following assembler code directive:
93
94::
95
Chris Kay33bfc5e2023-02-14 11:30:04 +000096 .section .bakery_lock
Douglas Raillardd7c21b72017-06-28 15:23:03 +010097
Chris Kay33bfc5e2023-02-14 11:30:04 +000098The ``.coherent_ram`` section is a sum of all sections like ``.bakery_lock`` which are
Douglas Raillardd7c21b72017-06-28 15:23:03 +010099used to allocate any data structures that are accessed both when a CPU is
100executing with its MMU and caches enabled, and when it's running with its MMU
101and caches disabled. Examples are given below.
102
103The following variables, functions and constants must be defined by the platform
104for the firmware to work correctly.
105
Javier Almansa Sobrino37bf69c2022-04-07 18:26:49 +0100106.. _platform_def_mandatory:
107
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100108File : platform_def.h [mandatory]
109~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100110
111Each platform must ensure that a header file of this name is in the system
Antonio Nino Diaz50a4d1a2019-02-01 12:22:22 +0000112include path with the following constants defined. This will require updating
113the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100114
Paul Beesleyf8640672019-04-12 14:19:42 +0100115Platform ports may optionally use the file ``include/plat/common/common_def.h``,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100116which provides typical values for some of the constants below. These values are
117likely to be suitable for all platform ports.
118
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100119- **#define : PLATFORM_LINKER_FORMAT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100120
121 Defines the linker format used by the platform, for example
122 ``elf64-littleaarch64``.
123
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100124- **#define : PLATFORM_LINKER_ARCH**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100125
126 Defines the processor architecture for the linker by the platform, for
127 example ``aarch64``.
128
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100129- **#define : PLATFORM_STACK_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100130
131 Defines the normal stack memory available to each CPU. This constant is used
Paul Beesleyf8640672019-04-12 14:19:42 +0100132 by ``plat/common/aarch64/platform_mp_stack.S`` and
133 ``plat/common/aarch64/platform_up_stack.S``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100134
David Horstmann051fd6d2020-11-12 15:19:04 +0000135- **#define : CACHE_WRITEBACK_GRANULE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100136
Max Yufa0b4e82022-09-08 23:21:21 +0000137 Defines the size in bytes of the largest cache line across all the cache
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100138 levels in the platform.
139
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100140- **#define : FIRMWARE_WELCOME_STR**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100141
142 Defines the character string printed by BL1 upon entry into the ``bl1_main()``
143 function.
144
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100145- **#define : PLATFORM_CORE_COUNT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100146
147 Defines the total number of CPUs implemented by the platform across all
148 clusters in the system.
149
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100150- **#define : PLAT_NUM_PWR_DOMAINS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100151
152 Defines the total number of nodes in the power domain topology
153 tree at all the power domain levels used by the platform.
154 This macro is used by the PSCI implementation to allocate
155 data structures to represent power domain topology.
156
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100157- **#define : PLAT_MAX_PWR_LVL**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100158
159 Defines the maximum power domain level that the power management operations
160 should apply to. More often, but not always, the power domain level
161 corresponds to affinity level. This macro allows the PSCI implementation
162 to know the highest power domain level that it should consider for power
163 management operations in the system that the platform implements. For
164 example, the Base AEM FVP implements two clusters with a configurable
165 number of CPUs and it reports the maximum power domain level as 1.
166
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100167- **#define : PLAT_MAX_OFF_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100168
169 Defines the local power state corresponding to the deepest power down
170 possible at every power domain level in the platform. The local power
171 states for each level may be sparsely allocated between 0 and this value
172 with 0 being reserved for the RUN state. The PSCI implementation uses this
173 value to initialize the local power states of the power domain nodes and
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100174 to specify the requested power state for a PSCI_CPU_OFF call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100175
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100176- **#define : PLAT_MAX_RET_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100177
178 Defines the local power state corresponding to the deepest retention state
179 possible at every power domain level in the platform. This macro should be
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100180 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100181 PSCI implementation to distinguish between retention and power down local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100182 power states within PSCI_CPU_SUSPEND call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100183
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100184- **#define : PLAT_MAX_PWR_LVL_STATES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100185
186 Defines the maximum number of local power states per power domain level
187 that the platform supports. The default value of this macro is 2 since
188 most platforms just support a maximum of two local power states at each
189 power domain level (power-down and retention). If the platform needs to
190 account for more local power states, then it must redefine this macro.
191
192 Currently, this macro is used by the Generic PSCI implementation to size
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100193 the array used for PSCI_STAT_COUNT/RESIDENCY accounting.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100194
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100195- **#define : BL1_RO_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100196
197 Defines the base address in secure ROM where BL1 originally lives. Must be
198 aligned on a page-size boundary.
199
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100200- **#define : BL1_RO_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100201
202 Defines the maximum address in secure ROM that BL1's actual content (i.e.
203 excluding any data section allocated at runtime) can occupy.
204
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100205- **#define : BL1_RW_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100206
207 Defines the base address in secure RAM where BL1's read-write data will live
208 at runtime. Must be aligned on a page-size boundary.
209
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100210- **#define : BL1_RW_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100211
212 Defines the maximum address in secure RAM that BL1's read-write data can
213 occupy at runtime.
214
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100215- **#define : BL2_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100216
217 Defines the base address in secure RAM where BL1 loads the BL2 binary image.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000218 Must be aligned on a page-size boundary. This constant is not applicable
219 when BL2_IN_XIP_MEM is set to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100220
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100221- **#define : BL2_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100222
223 Defines the maximum address in secure RAM that the BL2 image can occupy.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000224 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'.
225
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100226- **#define : BL2_RO_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000227
228 Defines the base address in secure XIP memory where BL2 RO section originally
229 lives. Must be aligned on a page-size boundary. This constant is only needed
230 when BL2_IN_XIP_MEM is set to '1'.
231
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100232- **#define : BL2_RO_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000233
234 Defines the maximum address in secure XIP memory that BL2's actual content
235 (i.e. excluding any data section allocated at runtime) can occupy. This
236 constant is only needed when BL2_IN_XIP_MEM is set to '1'.
237
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100238- **#define : BL2_RW_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000239
240 Defines the base address in secure RAM where BL2's read-write data will live
241 at runtime. Must be aligned on a page-size boundary. This constant is only
242 needed when BL2_IN_XIP_MEM is set to '1'.
243
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100244- **#define : BL2_RW_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000245
246 Defines the maximum address in secure RAM that BL2's read-write data can
247 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set
248 to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100249
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100250- **#define : BL31_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100251
252 Defines the base address in secure RAM where BL2 loads the BL31 binary
253 image. Must be aligned on a page-size boundary.
254
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100255- **#define : BL31_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100256
257 Defines the maximum address in secure RAM that the BL31 image can occupy.
258
Tamas Bana7bf68d2024-02-21 13:55:31 +0100259- **#define : PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE**
Tamas Ban1d3354e2022-09-16 14:09:30 +0200260
Tamas Bana7bf68d2024-02-21 13:55:31 +0100261 Defines the maximum message size between AP and RSE. Need to define if
262 platform supports RSE.
Tamas Ban1d3354e2022-09-16 14:09:30 +0200263
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100264For every image, the platform must define individual identifiers that will be
265used by BL1 or BL2 to load the corresponding image into memory from non-volatile
266storage. For the sake of performance, integer numbers will be used as
267identifiers. The platform will use those identifiers to return the relevant
268information about the image to be loaded (file handler, load address,
269authentication information, etc.). The following image identifiers are
270mandatory:
271
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100272- **#define : BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100273
274 BL2 image identifier, used by BL1 to load BL2.
275
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100276- **#define : BL31_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100277
278 BL31 image identifier, used by BL2 to load BL31.
279
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100280- **#define : BL33_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100281
282 BL33 image identifier, used by BL2 to load BL33.
283
284If Trusted Board Boot is enabled, the following certificate identifiers must
285also be defined:
286
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100287- **#define : TRUSTED_BOOT_FW_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100288
289 BL2 content certificate identifier, used by BL1 to load the BL2 content
290 certificate.
291
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100292- **#define : TRUSTED_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100293
294 Trusted key certificate identifier, used by BL2 to load the trusted key
295 certificate.
296
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100297- **#define : SOC_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100298
299 BL31 key certificate identifier, used by BL2 to load the BL31 key
300 certificate.
301
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100302- **#define : SOC_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100303
304 BL31 content certificate identifier, used by BL2 to load the BL31 content
305 certificate.
306
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100307- **#define : NON_TRUSTED_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100308
309 BL33 key certificate identifier, used by BL2 to load the BL33 key
310 certificate.
311
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100312- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100313
314 BL33 content certificate identifier, used by BL2 to load the BL33 content
315 certificate.
316
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100317- **#define : FWU_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100318
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100319 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100320 FWU content certificate.
321
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100322If the AP Firmware Updater Configuration image, BL2U is used, the following
323must also be defined:
324
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100325- **#define : BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100326
327 Defines the base address in secure memory where BL1 copies the BL2U binary
328 image. Must be aligned on a page-size boundary.
329
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100330- **#define : BL2U_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100331
332 Defines the maximum address in secure memory that the BL2U image can occupy.
333
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100334- **#define : BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100335
336 BL2U image identifier, used by BL1 to fetch an image descriptor
337 corresponding to BL2U.
338
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100339If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100340must also be defined:
341
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100342- **#define : SCP_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100343
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100344 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor
345 corresponding to SCP_BL2U.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000346
347 .. note::
348 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100349
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100350If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100351also be defined:
352
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100353- **#define : NS_BL1U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100354
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100355 Defines the base address in non-secure ROM where NS_BL1U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100356 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000357
358 .. note::
359 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100360
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100361- **#define : NS_BL1U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100362
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100363 NS_BL1U image identifier, used by BL1 to fetch an image descriptor
364 corresponding to NS_BL1U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100365
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100366If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100367be defined:
368
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100369- **#define : NS_BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100370
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100371 Defines the base address in non-secure memory where NS_BL2U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100372 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000373
374 .. note::
375 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100376
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100377- **#define : NS_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100378
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100379 NS_BL2U image identifier, used by BL1 to fetch an image descriptor
380 corresponding to NS_BL2U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100381
382For the the Firmware update capability of TRUSTED BOARD BOOT, the following
383macros may also be defined:
384
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100385- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100386
387 Total number of images that can be loaded simultaneously. If the platform
388 doesn't specify any value, it defaults to 10.
389
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100390If a SCP_BL2 image is supported by the platform, the following constants must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100391also be defined:
392
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100393- **#define : SCP_BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100394
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100395 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000396 from platform storage before being transferred to the SCP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100397
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100398- **#define : SCP_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100399
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100400 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100401 certificate (mandatory when Trusted Board Boot is enabled).
402
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100403- **#define : SCP_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100404
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100405 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100406 content certificate (mandatory when Trusted Board Boot is enabled).
407
408If a BL32 image is supported by the platform, the following constants must
409also be defined:
410
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100411- **#define : BL32_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100412
413 BL32 image identifier, used by BL2 to load BL32.
414
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100415- **#define : TRUSTED_OS_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100416
417 BL32 key certificate identifier, used by BL2 to load the BL32 key
418 certificate (mandatory when Trusted Board Boot is enabled).
419
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100420- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100421
422 BL32 content certificate identifier, used by BL2 to load the BL32 content
423 certificate (mandatory when Trusted Board Boot is enabled).
424
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100425- **#define : BL32_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100426
427 Defines the base address in secure memory where BL2 loads the BL32 binary
428 image. Must be aligned on a page-size boundary.
429
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100430- **#define : BL32_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100431
432 Defines the maximum address that the BL32 image can occupy.
433
434If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the
435platform, the following constants must also be defined:
436
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100437- **#define : TSP_SEC_MEM_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100438
439 Defines the base address of the secure memory used by the TSP image on the
440 platform. This must be at the same address or below ``BL32_BASE``.
441
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100442- **#define : TSP_SEC_MEM_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100443
444 Defines the size of the secure memory used by the BL32 image on the
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000445 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully
446 accommodate the memory required by the BL32 image, defined by ``BL32_BASE``
447 and ``BL32_LIMIT``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100448
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100449- **#define : TSP_IRQ_SEC_PHY_TIMER**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100450
451 Defines the ID of the secure physical generic timer interrupt used by the
452 TSP's interrupt handling code.
453
454If the platform port uses the translation table library code, the following
455constants must also be defined:
456
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100457- **#define : PLAT_XLAT_TABLES_DYNAMIC**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100458
459 Optional flag that can be set per-image to enable the dynamic allocation of
460 regions even when the MMU is enabled. If not defined, only static
461 functionality will be available, if defined and set to 1 it will also
462 include the dynamic functionality.
463
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100464- **#define : MAX_XLAT_TABLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100465
466 Defines the maximum number of translation tables that are allocated by the
467 translation table library code. To minimize the amount of runtime memory
468 used, choose the smallest value needed to map the required virtual addresses
469 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL
470 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions
471 as well.
472
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100473- **#define : MAX_MMAP_REGIONS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100474
475 Defines the maximum number of regions that are allocated by the translation
476 table library code. A region consists of physical base address, virtual base
477 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
478 defined in the ``mmap_region_t`` structure. The platform defines the regions
479 that should be mapped. Then, the translation table library will create the
480 corresponding tables and descriptors at runtime. To minimize the amount of
481 runtime memory used, choose the smallest value needed to register the
482 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is
483 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate
484 the dynamic regions as well.
485
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100486- **#define : PLAT_VIRT_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100487
488 Defines the total size of the virtual address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000489 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100490
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100491- **#define : PLAT_PHY_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100492
493 Defines the total size of the physical address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000494 for a 32 bit physical address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100495
496If the platform port uses the IO storage framework, the following constants
497must also be defined:
498
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100499- **#define : MAX_IO_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100500
501 Defines the maximum number of registered IO devices. Attempting to register
502 more devices than this value using ``io_register_device()`` will fail with
503 -ENOMEM.
504
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100505- **#define : MAX_IO_HANDLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100506
507 Defines the maximum number of open IO handles. Attempting to open more IO
508 entities than this value using ``io_open()`` will fail with -ENOMEM.
509
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100510- **#define : MAX_IO_BLOCK_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100511
512 Defines the maximum number of registered IO block devices. Attempting to
513 register more devices this value using ``io_dev_open()`` will fail
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100514 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100515 With this macro, multiple block devices could be supported at the same
516 time.
517
518If the platform needs to allocate data within the per-cpu data framework in
519BL31, it should define the following macro. Currently this is only required if
520the platform decides not to use the coherent memory section by undefining the
521``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
522required memory within the the per-cpu data to minimize wastage.
523
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100524- **#define : PLAT_PCPU_DATA_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100525
526 Defines the memory (in bytes) to be reserved within the per-cpu data
527 structure for use by the platform layer.
528
529The following constants are optional. They should be defined when the platform
Dan Handley610e7e12018-03-01 18:44:00 +0000530memory layout implies some image overlaying like in Arm standard platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100531
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100532- **#define : BL31_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100533
534 Defines the maximum address in secure RAM that the BL31's progbits sections
535 can occupy.
536
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100537- **#define : TSP_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100538
539 Defines the maximum address that the TSP's progbits sections can occupy.
540
Wing Li2c556f32022-09-14 13:18:17 -0700541If the platform supports OS-initiated mode, i.e. the build option
542``PSCI_OS_INIT_MODE`` is enabled, and if the platform's maximum power domain
543level for PSCI_CPU_SUSPEND differs from ``PLAT_MAX_PWR_LVL``, the following
544constant must be defined.
545
546- **#define : PLAT_MAX_CPU_SUSPEND_PWR_LVL**
547
548 Defines the maximum power domain level that PSCI_CPU_SUSPEND should apply to.
549
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100550If the platform port uses the PL061 GPIO driver, the following constant may
551optionally be defined:
552
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100553- **PLAT_PL061_MAX_GPIOS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100554 Maximum number of GPIOs required by the platform. This allows control how
555 much memory is allocated for PL061 GPIO controllers. The default value is
556
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100557 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100558
559If the platform port uses the partition driver, the following constant may
560optionally be defined:
561
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100562- **PLAT_PARTITION_MAX_ENTRIES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100563 Maximum number of partition entries required by the platform. This allows
564 control how much memory is allocated for partition entries. The default
565 value is 128.
Paul Beesleyf8640672019-04-12 14:19:42 +0100566 For example, define the build flag in ``platform.mk``:
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100567 PLAT_PARTITION_MAX_ENTRIES := 12
568 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100569
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800570- **PLAT_PARTITION_BLOCK_SIZE**
571 The size of partition block. It could be either 512 bytes or 4096 bytes.
572 The default value is 512.
Paul Beesleyf2ec7142019-10-04 16:17:46 +0000573 For example, define the build flag in ``platform.mk``:
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800574 PLAT_PARTITION_BLOCK_SIZE := 4096
575 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE))
576
Rob Hughes7a354bd2023-02-20 12:03:52 +0000577If the platform port uses the Arm® Ethos™-N NPU driver, the following
578configuration must be performed:
579
580- The NPU SiP service handler must be hooked up. This consists of both the
581 initial setup (``ethosn_smc_setup``) and the handler itself
582 (``ethosn_smc_handler``)
583
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100584If the platform port uses the Arm® Ethos™-N NPU driver with TZMP1 support
Rob Hughes7a354bd2023-02-20 12:03:52 +0000585enabled, the following constants and configuration must also be defined:
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100586
Rajasekaran Kalidoss46359002023-05-09 12:28:07 +0200587- **ETHOSN_NPU_PROT_FW_NSAID**
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100588
589 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to
590 access the protected memory that contains the NPU's firmware.
591
Rajasekaran Kalidoss46359002023-05-09 12:28:07 +0200592- **ETHOSN_NPU_PROT_DATA_RW_NSAID**
Mikael Olsson80b61f52023-03-14 18:29:06 +0100593
594 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
595 read/write access to the protected memory that contains inference data.
596
Rajasekaran Kalidoss46359002023-05-09 12:28:07 +0200597- **ETHOSN_NPU_PROT_DATA_RO_NSAID**
Mikael Olsson80b61f52023-03-14 18:29:06 +0100598
599 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
600 read-only access to the protected memory that contains inference data.
601
Rajasekaran Kalidoss46359002023-05-09 12:28:07 +0200602- **ETHOSN_NPU_NS_RW_DATA_NSAID**
Mikael Olsson80b61f52023-03-14 18:29:06 +0100603
604 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
605 read/write access to the non-protected memory.
606
Rajasekaran Kalidoss46359002023-05-09 12:28:07 +0200607- **ETHOSN_NPU_NS_RO_DATA_NSAID**
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100608
Mikael Olsson80b61f52023-03-14 18:29:06 +0100609 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
610 read-only access to the non-protected memory.
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100611
Rajasekaran Kalidoss46359002023-05-09 12:28:07 +0200612- **ETHOSN_NPU_FW_IMAGE_BASE** and **ETHOSN_NPU_FW_IMAGE_LIMIT**
Rob Hughes9a2177a2023-01-17 16:10:26 +0000613
Rob Hughes7a354bd2023-02-20 12:03:52 +0000614 Defines the physical address range that the NPU's firmware will be loaded
615 into and executed from.
616
617- Configure the platforms TrustZone Controller (TZC) with appropriate regions
618 of protected memory. At minimum this must include a region for the NPU's
619 firmware code and a region for protected inference data, and these must be
620 accessible using the NSAIDs defined above.
621
622- Include the NPU firmware and certificates in the FIP.
623
624- Provide FCONF entries to configure the image source for the NPU firmware
625 and certificates.
Rob Hughes9a2177a2023-01-17 16:10:26 +0000626
627- Add MMU mappings such that:
628
629 - BL2 can write the NPU firmware into the region defined by
Rajasekaran Kalidoss46359002023-05-09 12:28:07 +0200630 ``ETHOSN_NPU_FW_IMAGE_BASE`` and ``ETHOSN_NPU_FW_IMAGE_LIMIT``
Rob Hughes9a2177a2023-01-17 16:10:26 +0000631 - BL31 (SiP service) can read the NPU firmware from the same region
632
Rajasekaran Kalidoss46359002023-05-09 12:28:07 +0200633- Add the firmware image ID ``ETHOSN_NPU_FW_IMAGE_ID`` to the list of images
Rob Hughes7a354bd2023-02-20 12:03:52 +0000634 loaded by BL2.
Rob Hughes9a2177a2023-01-17 16:10:26 +0000635
636Please see the reference implementation code for the Juno platform as an example.
637
638
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100639The following constant is optional. It should be defined to override the default
640behaviour of the ``assert()`` function (for example, to save memory).
641
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100642- **PLAT_LOG_LEVEL_ASSERT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100643 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``,
644 ``assert()`` prints the name of the file, the line number and the asserted
645 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file
646 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it
647 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't
648 defined, it defaults to ``LOG_LEVEL``.
649
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +0100650If the platform port uses the DRTM feature, the following constants must be
651defined:
652
653- **#define : PLAT_DRTM_EVENT_LOG_MAX_SIZE**
654
655 Maximum Event Log size used by the platform. Platform can decide the maximum
656 size of the Event Log buffer, depending upon the highest hash algorithm
657 chosen and the number of components selected to measure during the DRTM
658 execution flow.
659
660- **#define : PLAT_DRTM_MMAP_ENTRIES**
661
662 Number of the MMAP entries used by the DRTM implementation to calculate the
663 size of address map region of the platform.
664
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100665File : plat_macros.S [mandatory]
666~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100667
668Each platform must ensure a file of this name is in the system include path with
Dan Handley610e7e12018-03-01 18:44:00 +0000669the following macro defined. In the Arm development platforms, this file is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100670found in ``plat/arm/board/<plat_name>/include/plat_macros.S``.
671
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100672- **Macro : plat_crash_print_regs**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100673
674 This macro allows the crash reporting routine to print relevant platform
675 registers in case of an unhandled exception in BL31. This aids in debugging
676 and this macro can be defined to be empty in case register reporting is not
677 desired.
678
679 For instance, GIC or interconnect registers may be helpful for
680 troubleshooting.
681
682Handling Reset
683--------------
684
685BL1 by default implements the reset vector where execution starts from a cold
686or warm boot. BL31 can be optionally set as a reset vector using the
687``RESET_TO_BL31`` make variable.
688
689For each CPU, the reset vector code is responsible for the following tasks:
690
691#. Distinguishing between a cold boot and a warm boot.
692
693#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
694 the CPU is placed in a platform-specific state until the primary CPU
695 performs the necessary steps to remove it from this state.
696
697#. In the case of a warm boot, ensuring that the CPU jumps to a platform-
698 specific address in the BL31 image in the same processor mode as it was
699 when released from reset.
700
701The following functions need to be implemented by the platform port to enable
702reset vector code to perform the above tasks.
703
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100704Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0]
705~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100706
707::
708
709 Argument : void
710 Return : uintptr_t
711
712This function is called with the MMU and caches disabled
713(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for
714distinguishing between a warm and cold reset for the current CPU using
715platform-specific means. If it's a warm reset, then it returns the warm
716reset entrypoint point provided to ``plat_setup_psci_ops()`` during
717BL31 initialization. If it's a cold reset then this function must return zero.
718
719This function does not follow the Procedure Call Standard used by the
Dan Handley610e7e12018-03-01 18:44:00 +0000720Application Binary Interface for the Arm 64-bit architecture. The caller should
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100721not assume that callee saved registers are preserved across a call to this
722function.
723
724This function fulfills requirement 1 and 3 listed above.
725
726Note that for platforms that support programming the reset address, it is
727expected that a CPU will start executing code directly at the right address,
728both on a cold and warm reset. In this case, there is no need to identify the
729type of reset nor to query the warm reset entrypoint. Therefore, implementing
730this function is not required on such platforms.
731
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100732Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
733~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100734
735::
736
737 Argument : void
738
739This function is called with the MMU and data caches disabled. It is responsible
740for placing the executing secondary CPU in a platform-specific state until the
741primary CPU performs the necessary actions to bring it out of that state and
742allow entry into the OS. This function must not return.
743
Dan Handley610e7e12018-03-01 18:44:00 +0000744In the Arm FVP port, when using the normal boot flow, each secondary CPU powers
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100745itself off. The primary CPU is responsible for powering up the secondary CPUs
746when normal world software requires them. When booting an EL3 payload instead,
747they stay powered on and are put in a holding pen until their mailbox gets
748populated.
749
750This function fulfills requirement 2 above.
751
752Note that for platforms that can't release secondary CPUs out of reset, only the
753primary CPU will execute the cold boot code. Therefore, implementing this
754function is not required on such platforms.
755
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100756Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
757~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100758
759::
760
761 Argument : void
762 Return : unsigned int
763
764This function identifies whether the current CPU is the primary CPU or a
765secondary CPU. A return value of zero indicates that the CPU is not the
766primary CPU, while a non-zero return value indicates that the CPU is the
767primary CPU.
768
769Note that for platforms that can't release secondary CPUs out of reset, only the
770primary CPU will execute the cold boot code. Therefore, there is no need to
771distinguish between primary and secondary CPUs and implementing this function is
772not required.
773
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100774Function : platform_mem_init() [mandatory]
775~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100776
777::
778
779 Argument : void
780 Return : void
781
782This function is called before any access to data is made by the firmware, in
783order to carry out any essential memory initialization.
784
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100785Function: plat_get_rotpk_info()
786~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100787
788::
789
790 Argument : void *, void **, unsigned int *, unsigned int *
791 Return : int
792
793This function is mandatory when Trusted Board Boot is enabled. It returns a
794pointer to the ROTPK stored in the platform (or a hash of it) and its length.
795The ROTPK must be encoded in DER format according to the following ASN.1
796structure:
797
798::
799
800 AlgorithmIdentifier ::= SEQUENCE {
801 algorithm OBJECT IDENTIFIER,
802 parameters ANY DEFINED BY algorithm OPTIONAL
803 }
804
805 SubjectPublicKeyInfo ::= SEQUENCE {
806 algorithm AlgorithmIdentifier,
807 subjectPublicKey BIT STRING
808 }
809
810In case the function returns a hash of the key:
811
812::
813
814 DigestInfo ::= SEQUENCE {
815 digestAlgorithm AlgorithmIdentifier,
816 digest OCTET STRING
817 }
818
819The function returns 0 on success. Any other value is treated as error by the
820Trusted Board Boot. The function also reports extra information related
821to the ROTPK in the flags parameter:
822
823::
824
825 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a
826 hash.
827 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK
828 verification while the platform ROTPK is not deployed.
829 When this flag is set, the function does not need to
830 return a platform ROTPK, and the authentication
831 framework uses the ROTPK in the certificate without
832 verifying it against the platform value. This flag
833 must not be used in a deployed production environment.
834
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100835Function: plat_get_nv_ctr()
836~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100837
838::
839
840 Argument : void *, unsigned int *
841 Return : int
842
843This function is mandatory when Trusted Board Boot is enabled. It returns the
844non-volatile counter value stored in the platform in the second argument. The
845cookie in the first argument may be used to select the counter in case the
846platform provides more than one (for example, on platforms that use the default
847TBBR CoT, the cookie will correspond to the OID values defined in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100848TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100849
850The function returns 0 on success. Any other value means the counter value could
851not be retrieved from the platform.
852
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100853Function: plat_set_nv_ctr()
854~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100855
856::
857
858 Argument : void *, unsigned int
859 Return : int
860
861This function is mandatory when Trusted Board Boot is enabled. It sets a new
862counter value in the platform. The cookie in the first argument may be used to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100863select the counter (as explained in plat_get_nv_ctr()). The second argument is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100864the updated counter value to be written to the NV counter.
865
866The function returns 0 on success. Any other value means the counter value could
867not be updated.
868
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100869Function: plat_set_nv_ctr2()
870~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100871
872::
873
874 Argument : void *, const auth_img_desc_t *, unsigned int
875 Return : int
876
877This function is optional when Trusted Board Boot is enabled. If this
878interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The
879first argument passed is a cookie and is typically used to
880differentiate between a Non Trusted NV Counter and a Trusted NV
881Counter. The second argument is a pointer to an authentication image
882descriptor and may be used to decide if the counter is allowed to be
883updated or not. The third argument is the updated counter value to
884be written to the NV counter.
885
886The function returns 0 on success. Any other value means the counter value
887either could not be updated or the authentication image descriptor indicates
888that it is not allowed to be updated.
889
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +0100890Dynamic Root of Trust for Measurement support (in BL31)
891-------------------------------------------------------
892
893The functions mentioned in this section are mandatory, when platform enables
894DRTM_SUPPORT build flag.
895
896Function : plat_get_addr_mmap()
897~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
898
899::
900
901 Argument : void
902 Return : const mmap_region_t *
903
904This function is used to return the address of the platform *address-map* table,
905which describes the regions of normal memory, memory mapped I/O
906and non-volatile memory.
907
908Function : plat_has_non_host_platforms()
909~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
910
911::
912
913 Argument : void
914 Return : bool
915
916This function returns *true* if the platform has any trusted devices capable of
917DMA, otherwise returns *false*.
918
919Function : plat_has_unmanaged_dma_peripherals()
920~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
921
922::
923
924 Argument : void
925 Return : bool
926
927This function returns *true* if platform uses peripherals whose DMA is not
928managed by an SMMU, otherwise returns *false*.
929
930Note -
931If the platform has peripherals that are not managed by the SMMU, then the
932platform should investigate such peripherals to determine whether they can
933be trusted, and such peripherals should be moved under "Non-host platforms"
934if they can be trusted.
935
936Function : plat_get_total_num_smmus()
937~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
938
939::
940
941 Argument : void
942 Return : unsigned int
943
944This function returns the total number of SMMUs in the platform.
945
946Function : plat_enumerate_smmus()
947~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
948::
949
950
951 Argument : void
952 Return : const uintptr_t *, size_t
953
954This function returns an array of SMMU addresses and the actual number of SMMUs
955reported by the platform.
956
957Function : plat_drtm_get_dma_prot_features()
958~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
959
960::
961
962 Argument : void
963 Return : const plat_drtm_dma_prot_features_t*
964
965This function returns the address of plat_drtm_dma_prot_features_t structure
966containing the maximum number of protected regions and bitmap with the types
967of DMA protection supported by the platform.
968For more details see section 3.3 Table 6 of `DRTM`_ specification.
969
970Function : plat_drtm_dma_prot_get_max_table_bytes()
971~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
972
973::
974
975 Argument : void
976 Return : uint64_t
977
978This function returns the maximum size of DMA protected regions table in
979bytes.
980
981Function : plat_drtm_get_tpm_features()
982~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
983
984::
985
986 Argument : void
987 Return : const plat_drtm_tpm_features_t*
988
989This function returns the address of *plat_drtm_tpm_features_t* structure
990containing PCR usage schema, TPM-based hash, and firmware hash algorithm
991supported by the platform.
992
993Function : plat_drtm_get_min_size_normal_world_dce()
994~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
995
996::
997
998 Argument : void
999 Return : uint64_t
1000
1001This function returns the size normal-world DCE of the platform.
1002
1003Function : plat_drtm_get_imp_def_dlme_region_size()
1004~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1005
1006::
1007
1008 Argument : void
1009 Return : uint64_t
1010
1011This function returns the size of implementation defined DLME region
1012of the platform.
1013
1014Function : plat_drtm_get_tcb_hash_table_size()
1015~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1016
1017::
1018
1019 Argument : void
1020 Return : uint64_t
1021
1022This function returns the size of TCB hash table of the platform.
1023
1024Function : plat_drtm_get_tcb_hash_features()
1025~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1026
1027::
1028
1029 Argument : void
1030 Return : uint64_t
1031
1032This function returns the Maximum number of TCB hashes recorded by the
1033platform.
1034For more details see section 3.3 Table 6 of `DRTM`_ specification.
1035
1036Function : plat_drtm_validate_ns_region()
1037~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1038
1039::
1040
1041 Argument : uintptr_t, uintptr_t
1042 Return : int
1043
1044This function validates that given region is within the Non-Secure region
1045of DRAM. This function takes a region start address and size an input
1046arguments, and returns 0 on success and -1 on failure.
1047
1048Function : plat_set_drtm_error()
1049~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1050
1051::
1052
1053 Argument : uint64_t
1054 Return : int
1055
1056This function writes a 64 bit error code received as input into
1057non-volatile storage and returns 0 on success and -1 on failure.
1058
1059Function : plat_get_drtm_error()
1060~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1061
1062::
1063
1064 Argument : uint64_t*
1065 Return : int
1066
1067This function reads a 64 bit error code from the non-volatile storage
1068into the received address, and returns 0 on success and -1 on failure.
1069
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001070Common mandatory function modifications
1071---------------------------------------
1072
1073The following functions are mandatory functions which need to be implemented
1074by the platform port.
1075
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001076Function : plat_my_core_pos()
1077~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001078
1079::
1080
1081 Argument : void
1082 Return : unsigned int
1083
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001084This function returns the index of the calling CPU which is used as a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001085CPU-specific linear index into blocks of memory (for example while allocating
1086per-CPU stacks). This function will be invoked very early in the
1087initialization sequence which mandates that this function should be
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001088implemented in assembly and should not rely on the availability of a C
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001089runtime environment. This function can clobber x0 - x8 and must preserve
1090x9 - x29.
1091
1092This function plays a crucial role in the power domain topology framework in
Paul Beesleyf8640672019-04-12 14:19:42 +01001093PSCI and details of this can be found in
1094:ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001095
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001096Function : plat_core_pos_by_mpidr()
1097~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001098
1099::
1100
1101 Argument : u_register_t
1102 Return : int
1103
1104This function validates the ``MPIDR`` of a CPU and converts it to an index,
1105which can be used as a CPU-specific linear index into blocks of memory. In
1106case the ``MPIDR`` is invalid, this function returns -1. This function will only
1107be invoked by BL31 after the power domain topology is initialized and can
Dan Handley610e7e12018-03-01 18:44:00 +00001108utilize the C runtime environment. For further details about how TF-A
1109represents the power domain topology and how this relates to the linear CPU
Paul Beesleyf8640672019-04-12 14:19:42 +01001110index, please refer :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001111
Ambroise Vincentd207f562019-04-10 12:50:27 +01001112Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1]
1113~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1114
1115::
1116
1117 Arguments : void **heap_addr, size_t *heap_size
1118 Return : int
1119
1120This function is invoked during Mbed TLS library initialisation to get a heap,
1121by means of a starting address and a size. This heap will then be used
1122internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS
1123must be able to provide a heap to it.
1124
1125A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in
1126which a heap is statically reserved during compile time inside every image
1127(i.e. every BL stage) that utilises Mbed TLS. In this default implementation,
1128the function simply returns the address and size of this "pre-allocated" heap.
1129For a platform to use this default implementation, only a call to the helper
1130from inside plat_get_mbedtls_heap() body is enough and nothing else is needed.
1131
1132However, by writting their own implementation, platforms have the potential to
1133optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is
1134shared between BL1 and BL2 stages and, thus, the necessary space is not reserved
1135twice.
1136
1137On success the function should return 0 and a negative error code otherwise.
1138
Sumit Gargc0c369c2019-11-15 18:47:53 +05301139Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1]
1140~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1141
1142::
1143
1144 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key,
1145 size_t *key_len, unsigned int *flags, const uint8_t *img_id,
1146 size_t img_id_len
1147 Return : int
1148
1149This function provides a symmetric key (either SSK or BSSK depending on
1150fw_enc_status) which is invoked during runtime decryption of encrypted
1151firmware images. `plat/common/plat_bl_common.c` provides a dummy weak
1152implementation for testing purposes which must be overridden by the platform
1153trying to implement a real world firmware encryption use-case.
1154
1155It also allows the platform to pass symmetric key identifier rather than
1156actual symmetric key which is useful in cases where the crypto backend provides
1157secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER``
1158flag must be set in ``flags``.
1159
1160In addition to above a platform may also choose to provide an image specific
1161symmetric key/identifier using img_id.
1162
1163On success the function should return 0 and a negative error code otherwise.
1164
Manish Pandey34a305e2021-10-21 21:53:49 +01001165Note that this API depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +05301166
Manish V Badarkheda87af12021-06-20 21:14:46 +01001167Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1]
1168~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1169
1170::
1171
Sughosh Ganuf40154f2021-11-17 17:08:10 +05301172 Argument : const struct fwu_metadata *metadata
Manish V Badarkheda87af12021-06-20 21:14:46 +01001173 Return : void
1174
1175This function is mandatory when PSA_FWU_SUPPORT is enabled.
1176It provides a means to retrieve image specification (offset in
1177non-volatile storage and length) of active/updated images using the passed
1178FWU metadata, and update I/O policies of active/updated images using retrieved
1179image specification information.
1180Further I/O layer operations such as I/O open, I/O read, etc. on these
1181images rely on this function call.
1182
1183In Arm platforms, this function is used to set an I/O policy of the FIP image,
1184container of all active/updated secure and non-secure images.
1185
1186Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1]
1187~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1188
1189::
1190
1191 Argument : unsigned int image_id, uintptr_t *dev_handle,
1192 uintptr_t *image_spec
1193 Return : int
1194
1195This function is mandatory when PSA_FWU_SUPPORT is enabled. It is
1196responsible for setting up the platform I/O policy of the requested metadata
1197image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will
1198be used to load this image from the platform's non-volatile storage.
1199
1200FWU metadata can not be always stored as a raw image in non-volatile storage
1201to define its image specification (offset in non-volatile storage and length)
1202statically in I/O policy.
1203For example, the FWU metadata image is stored as a partition inside the GUID
1204partition table image. Its specification is defined in the partition table
1205that needs to be parsed dynamically.
1206This function provides a means to retrieve such dynamic information to set
1207the I/O policy of the FWU metadata image.
1208Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata
1209image relies on this function call.
1210
1211It returns '0' on success, otherwise a negative error value on error.
1212Alongside, returns device handle and image specification from the I/O policy
1213of the requested FWU metadata image.
1214
Sughosh Ganu4e336a62021-12-01 15:53:32 +05301215Function : plat_fwu_get_boot_idx() [when PSA_FWU_SUPPORT == 1]
1216~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1217
1218::
1219
1220 Argument : void
1221 Return : uint32_t
1222
1223This function is mandatory when PSA_FWU_SUPPORT is enabled. It provides the
1224means to retrieve the boot index value from the platform. The boot index is the
1225bank from which the platform has booted the firmware images.
1226
1227By default, the platform will read the metadata structure and try to boot from
1228the active bank. If the platform fails to boot from the active bank due to
1229reasons like an Authentication failure, or on crossing a set number of watchdog
1230resets while booting from the active bank, the platform can then switch to boot
1231from a different bank. This function then returns the bank that the platform
1232should boot its images from.
1233
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001234Common optional modifications
1235-----------------------------
1236
1237The following are helper functions implemented by the firmware that perform
1238common platform-specific tasks. A platform may choose to override these
1239definitions.
1240
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001241Function : plat_set_my_stack()
1242~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001243
1244::
1245
1246 Argument : void
1247 Return : void
1248
1249This function sets the current stack pointer to the normal memory stack that
1250has been allocated for the current CPU. For BL images that only require a
1251stack for the primary CPU, the UP version of the function is used. The size
1252of the stack allocated to each CPU is specified by the platform defined
1253constant ``PLATFORM_STACK_SIZE``.
1254
1255Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +01001256provided in ``plat/common/aarch64/platform_up_stack.S`` and
1257``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001258
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001259Function : plat_get_my_stack()
1260~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001261
1262::
1263
1264 Argument : void
1265 Return : uintptr_t
1266
1267This function returns the base address of the normal memory stack that
1268has been allocated for the current CPU. For BL images that only require a
1269stack for the primary CPU, the UP version of the function is used. The size
1270of the stack allocated to each CPU is specified by the platform defined
1271constant ``PLATFORM_STACK_SIZE``.
1272
1273Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +01001274provided in ``plat/common/aarch64/platform_up_stack.S`` and
1275``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001276
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001277Function : plat_report_exception()
1278~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001279
1280::
1281
1282 Argument : unsigned int
1283 Return : void
1284
1285A platform may need to report various information about its status when an
1286exception is taken, for example the current exception level, the CPU security
1287state (secure/non-secure), the exception type, and so on. This function is
1288called in the following circumstances:
1289
1290- In BL1, whenever an exception is taken.
1291- In BL2, whenever an exception is taken.
1292
1293The default implementation doesn't do anything, to avoid making assumptions
1294about the way the platform displays its status information.
1295
1296For AArch64, this function receives the exception type as its argument.
1297Possible values for exceptions types are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +01001298``include/common/bl_common.h`` header file. Note that these constants are not
Dan Handley610e7e12018-03-01 18:44:00 +00001299related to any architectural exception code; they are just a TF-A convention.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001300
1301For AArch32, this function receives the exception mode as its argument.
1302Possible values for exception modes are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +01001303``include/lib/aarch32/arch.h`` header file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001304
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001305Function : plat_reset_handler()
1306~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001307
1308::
1309
1310 Argument : void
1311 Return : void
1312
1313A platform may need to do additional initialization after reset. This function
Paul Beesleyf2ec7142019-10-04 16:17:46 +00001314allows the platform to do the platform specific initializations. Platform
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001315specific errata workarounds could also be implemented here. The API should
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001316preserve the values of callee saved registers x19 to x29.
1317
1318The default implementation doesn't do anything. If a platform needs to override
Paul Beesleyf8640672019-04-12 14:19:42 +01001319the default implementation, refer to the :ref:`Firmware Design` for general
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001320guidelines.
1321
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001322Function : plat_disable_acp()
1323~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001324
1325::
1326
1327 Argument : void
1328 Return : void
1329
John Tsichritzis6dda9762018-07-23 09:18:04 +01001330This API allows a platform to disable the Accelerator Coherency Port (if
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001331present) during a cluster power down sequence. The default weak implementation
John Tsichritzis6dda9762018-07-23 09:18:04 +01001332doesn't do anything. Since this API is called during the power down sequence,
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001333it has restrictions for stack usage and it can use the registers x0 - x17 as
1334scratch registers. It should preserve the value in x18 register as it is used
1335by the caller to store the return address.
1336
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001337Function : plat_error_handler()
1338~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001339
1340::
1341
1342 Argument : int
1343 Return : void
1344
1345This API is called when the generic code encounters an error situation from
1346which it cannot continue. It allows the platform to perform error reporting or
1347recovery actions (for example, reset the system). This function must not return.
1348
1349The parameter indicates the type of error using standard codes from ``errno.h``.
1350Possible errors reported by the generic code are:
1351
1352- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted
1353 Board Boot is enabled)
1354- ``-ENOENT``: the requested image or certificate could not be found or an IO
1355 error was detected
Dan Handley610e7e12018-03-01 18:44:00 +00001356- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this
1357 error is usually an indication of an incorrect array size
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001358
1359The default implementation simply spins.
1360
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001361Function : plat_panic_handler()
1362~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001363
1364::
1365
1366 Argument : void
1367 Return : void
1368
1369This API is called when the generic code encounters an unexpected error
1370situation from which it cannot recover. This function must not return,
1371and must be implemented in assembly because it may be called before the C
1372environment is initialized.
1373
Paul Beesleyba3ed402019-03-13 16:20:44 +00001374.. note::
1375 The address from where it was called is stored in x30 (Link Register).
1376 The default implementation simply spins.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001377
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +01001378Function : plat_system_reset()
1379~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1380
1381::
1382
1383 Argument : void
1384 Return : void
1385
1386This function is used by the platform to resets the system. It can be used
1387in any specific use-case where system needs to be resetted. For example,
1388in case of DRTM implementation this function reset the system after
1389writing the DRTM error code in the non-volatile storage. This function
1390never returns. Failure in reset results in panic.
1391
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001392Function : plat_get_bl_image_load_info()
1393~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001394
1395::
1396
1397 Argument : void
1398 Return : bl_load_info_t *
1399
1400This function returns pointer to the list of images that the platform has
Soby Mathew97b1bff2018-09-27 16:46:41 +01001401populated to load. This function is invoked in BL2 to load the
1402BL3xx images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001403
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001404Function : plat_get_next_bl_params()
1405~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001406
1407::
1408
1409 Argument : void
1410 Return : bl_params_t *
1411
1412This function returns a pointer to the shared memory that the platform has
Dan Handley610e7e12018-03-01 18:44:00 +00001413kept aside to pass TF-A related information that next BL image needs. This
Soby Mathew97b1bff2018-09-27 16:46:41 +01001414function is invoked in BL2 to pass this information to the next BL
1415image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001416
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001417Function : plat_get_stack_protector_canary()
1418~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001419
1420::
1421
1422 Argument : void
1423 Return : u_register_t
1424
1425This function returns a random value that is used to initialize the canary used
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001426when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001427value will weaken the protection as the attacker could easily write the right
1428value as part of the attack most of the time. Therefore, it should return a
1429true random number.
1430
Paul Beesleyba3ed402019-03-13 16:20:44 +00001431.. warning::
1432 For the protection to be effective, the global data need to be placed at
1433 a lower address than the stack bases. Failure to do so would allow an
1434 attacker to overwrite the canary as part of the stack buffer overflow attack.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001435
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001436Function : plat_flush_next_bl_params()
1437~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001438
1439::
1440
1441 Argument : void
1442 Return : void
1443
1444This function flushes to main memory all the image params that are passed to
Soby Mathew97b1bff2018-09-27 16:46:41 +01001445next image. This function is invoked in BL2 to flush this information
1446to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001447
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001448Function : plat_log_get_prefix()
1449~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewaaf15f52017-09-04 11:49:29 +01001450
1451::
1452
1453 Argument : unsigned int
1454 Return : const char *
1455
1456This function defines the prefix string corresponding to the `log_level` to be
Dan Handley610e7e12018-03-01 18:44:00 +00001457prepended to all the log output from TF-A. The `log_level` (argument) will
1458correspond to one of the standard log levels defined in debug.h. The platform
1459can override the common implementation to define a different prefix string for
John Tsichritzis30f89642018-06-07 16:31:34 +01001460the log output. The implementation should be robust to future changes that
Dan Handley610e7e12018-03-01 18:44:00 +00001461increase the number of log levels.
Soby Mathewaaf15f52017-09-04 11:49:29 +01001462
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001463Function : plat_get_soc_version()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001464~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001465
1466::
1467
1468 Argument : void
1469 Return : int32_t
1470
1471This function returns soc version which mainly consist of below fields
1472
1473::
1474
1475 soc_version[30:24] = JEP-106 continuation code for the SiP
1476 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001477 soc_version[15:0] = Implementation defined SoC ID
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001478
1479Function : plat_get_soc_revision()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001480~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001481
1482::
1483
1484 Argument : void
1485 Return : int32_t
1486
1487This function returns soc revision in below format
1488
1489::
1490
1491 soc_revision[0:30] = SOC revision of specific SOC
1492
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001493Function : plat_is_smccc_feature_available()
1494~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1495
1496::
1497
1498 Argument : u_register_t
1499 Return : int32_t
1500
1501This function returns SMC_ARCH_CALL_SUCCESS if the platform supports
1502the SMCCC function specified in the argument; otherwise returns
1503SMC_ARCH_CALL_NOT_SUPPORTED.
1504
Okash Khawaja037b56e2022-11-04 12:38:01 +00001505Function : plat_can_cmo()
1506~~~~~~~~~~~~~~~~~~~~~~~~~
1507
1508::
1509
1510 Argument : void
1511 Return : uint64_t
1512
1513When CONDITIONAL_CMO flag is enabled:
1514
1515- This function indicates whether cache management operations should be
1516 performed. It returns 0 if CMOs should be skipped and non-zero
1517 otherwise.
Okash Khawaja94532202022-11-14 12:50:30 +00001518- The function must not clobber x1, x2 and x3. It's also not safe to rely on
1519 stack. Otherwise obey AAPCS.
Okash Khawaja037b56e2022-11-04 12:38:01 +00001520
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001521Modifications specific to a Boot Loader stage
1522---------------------------------------------
1523
1524Boot Loader Stage 1 (BL1)
1525-------------------------
1526
1527BL1 implements the reset vector where execution starts from after a cold or
1528warm boot. For each CPU, BL1 is responsible for the following tasks:
1529
1530#. Handling the reset as described in section 2.2
1531
1532#. In the case of a cold boot and the CPU being the primary CPU, ensuring that
1533 only this CPU executes the remaining BL1 code, including loading and passing
1534 control to the BL2 stage.
1535
1536#. Identifying and starting the Firmware Update process (if required).
1537
1538#. Loading the BL2 image from non-volatile storage into secure memory at the
1539 address specified by the platform defined constant ``BL2_BASE``.
1540
1541#. Populating a ``meminfo`` structure with the following information in memory,
1542 accessible by BL2 immediately upon entry.
1543
1544 ::
1545
1546 meminfo.total_base = Base address of secure RAM visible to BL2
1547 meminfo.total_size = Size of secure RAM visible to BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001548
Soby Mathew97b1bff2018-09-27 16:46:41 +01001549 By default, BL1 places this ``meminfo`` structure at the end of secure
1550 memory visible to BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001551
Soby Mathewb1bf0442018-02-16 14:52:52 +00001552 It is possible for the platform to decide where it wants to place the
1553 ``meminfo`` structure for BL2 or restrict the amount of memory visible to
1554 BL2 by overriding the weak default implementation of
1555 ``bl1_plat_handle_post_image_load`` API.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001556
1557The following functions need to be implemented by the platform port to enable
1558BL1 to perform the above tasks.
1559
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001560Function : bl1_early_platform_setup() [mandatory]
1561~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001562
1563::
1564
1565 Argument : void
1566 Return : void
1567
1568This function executes with the MMU and data caches disabled. It is only called
1569by the primary CPU.
1570
Dan Handley610e7e12018-03-01 18:44:00 +00001571On Arm standard platforms, this function:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001572
1573- Enables a secure instance of SP805 to act as the Trusted Watchdog.
1574
1575- Initializes a UART (PL011 console), which enables access to the ``printf``
1576 family of functions in BL1.
1577
1578- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to
1579 the CCI slave interface corresponding to the cluster that includes the
1580 primary CPU.
1581
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001582Function : bl1_plat_arch_setup() [mandatory]
1583~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001584
1585::
1586
1587 Argument : void
1588 Return : void
1589
1590This function performs any platform-specific and architectural setup that the
1591platform requires. Platform-specific setup might include configuration of
1592memory controllers and the interconnect.
1593
Dan Handley610e7e12018-03-01 18:44:00 +00001594In Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001595
1596This function helps fulfill requirement 2 above.
1597
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001598Function : bl1_platform_setup() [mandatory]
1599~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001600
1601::
1602
1603 Argument : void
1604 Return : void
1605
1606This function executes with the MMU and data caches enabled. It is responsible
1607for performing any remaining platform-specific setup that can occur after the
1608MMU and data cache have been enabled.
1609
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001610if support for multiple boot sources is required, it initializes the boot
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001611sequence used by plat_try_next_boot_source().
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001612
Dan Handley610e7e12018-03-01 18:44:00 +00001613In Arm standard platforms, this function initializes the storage abstraction
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001614layer used to load the next bootloader image.
1615
1616This function helps fulfill requirement 4 above.
1617
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001618Function : bl1_plat_sec_mem_layout() [mandatory]
1619~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001620
1621::
1622
1623 Argument : void
1624 Return : meminfo *
1625
1626This function should only be called on the cold boot path. It executes with the
1627MMU and data caches enabled. The pointer returned by this function must point to
1628a ``meminfo`` structure containing the extents and availability of secure RAM for
1629the BL1 stage.
1630
1631::
1632
1633 meminfo.total_base = Base address of secure RAM visible to BL1
1634 meminfo.total_size = Size of secure RAM visible to BL1
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001635
1636This information is used by BL1 to load the BL2 image in secure RAM. BL1 also
1637populates a similar structure to tell BL2 the extents of memory available for
1638its own use.
1639
1640This function helps fulfill requirements 4 and 5 above.
1641
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001642Function : bl1_plat_prepare_exit() [optional]
1643~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001644
1645::
1646
1647 Argument : entry_point_info_t *
1648 Return : void
1649
1650This function is called prior to exiting BL1 in response to the
1651``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform
1652platform specific clean up or bookkeeping operations before transferring
1653control to the next image. It receives the address of the ``entry_point_info_t``
1654structure passed from BL2. This function runs with MMU disabled.
1655
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001656Function : bl1_plat_set_ep_info() [optional]
1657~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001658
1659::
1660
1661 Argument : unsigned int image_id, entry_point_info_t *ep_info
1662 Return : void
1663
1664This function allows platforms to override ``ep_info`` for the given ``image_id``.
1665
1666The default implementation just returns.
1667
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001668Function : bl1_plat_get_next_image_id() [optional]
1669~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001670
1671::
1672
1673 Argument : void
1674 Return : unsigned int
1675
1676This and the following function must be overridden to enable the FWU feature.
1677
1678BL1 calls this function after platform setup to identify the next image to be
1679loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds
1680with the normal boot sequence, which loads and executes BL2. If the platform
1681returns a different image id, BL1 assumes that Firmware Update is required.
1682
Dan Handley610e7e12018-03-01 18:44:00 +00001683The default implementation always returns ``BL2_IMAGE_ID``. The Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001684platforms override this function to detect if firmware update is required, and
1685if so, return the first image in the firmware update process.
1686
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001687Function : bl1_plat_get_image_desc() [optional]
1688~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001689
1690::
1691
1692 Argument : unsigned int image_id
1693 Return : image_desc_t *
1694
1695BL1 calls this function to get the image descriptor information ``image_desc_t``
1696for the provided ``image_id`` from the platform.
1697
Dan Handley610e7e12018-03-01 18:44:00 +00001698The default implementation always returns a common BL2 image descriptor. Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001699standard platforms return an image descriptor corresponding to BL2 or one of
1700the firmware update images defined in the Trusted Board Boot Requirements
1701specification.
1702
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001703Function : bl1_plat_handle_pre_image_load() [optional]
1704~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001705
1706::
1707
Soby Mathew2f38ce32018-02-08 17:45:12 +00001708 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001709 Return : int
1710
1711This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001712corresponding to ``image_id``. This function is invoked in BL1, both in cold
1713boot and FWU code path, before loading the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001714
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001715Function : bl1_plat_handle_post_image_load() [optional]
1716~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001717
1718::
1719
Soby Mathew2f38ce32018-02-08 17:45:12 +00001720 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001721 Return : int
1722
1723This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001724corresponding to ``image_id``. This function is invoked in BL1, both in cold
1725boot and FWU code path, after loading and authenticating the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001726
Soby Mathewb1bf0442018-02-16 14:52:52 +00001727The default weak implementation of this function calculates the amount of
1728Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t``
1729structure at the beginning of this free memory and populates it. The address
1730of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint
1731information to BL2.
1732
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001733Function : bl1_plat_fwu_done() [optional]
1734~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001735
1736::
1737
1738 Argument : unsigned int image_id, uintptr_t image_src,
1739 unsigned int image_size
1740 Return : void
1741
1742BL1 calls this function when the FWU process is complete. It must not return.
1743The platform may override this function to take platform specific action, for
1744example to initiate the normal boot flow.
1745
1746The default implementation spins forever.
1747
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001748Function : bl1_plat_mem_check() [mandatory]
1749~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001750
1751::
1752
1753 Argument : uintptr_t mem_base, unsigned int mem_size,
1754 unsigned int flags
1755 Return : int
1756
1757BL1 calls this function while handling FWU related SMCs, more specifically when
1758copying or authenticating an image. Its responsibility is to ensure that the
1759region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and
1760that this memory corresponds to either a secure or non-secure memory region as
1761indicated by the security state of the ``flags`` argument.
1762
1763This function can safely assume that the value resulting from the addition of
1764``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not
1765overflow.
1766
1767This function must return 0 on success, a non-null error code otherwise.
1768
1769The default implementation of this function asserts therefore platforms must
1770override it when using the FWU feature.
1771
1772Boot Loader Stage 2 (BL2)
1773-------------------------
1774
1775The BL2 stage is executed only by the primary CPU, which is determined in BL1
1776using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at
Soby Mathew97b1bff2018-09-27 16:46:41 +01001777``BL2_BASE``. BL2 executes in Secure EL1 and and invokes
1778``plat_get_bl_image_load_info()`` to retrieve the list of images to load from
1779non-volatile storage to secure/non-secure RAM. After all the images are loaded
1780then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable
1781images to be passed to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001782
1783The following functions must be implemented by the platform port to enable BL2
1784to perform the above tasks.
1785
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001786Function : bl2_early_platform_setup2() [mandatory]
1787~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001788
1789::
1790
Soby Mathew97b1bff2018-09-27 16:46:41 +01001791 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001792 Return : void
1793
1794This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001795by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments
1796are platform specific.
1797
1798On Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001799
Manish V Badarkhe81414512020-06-24 15:58:38 +01001800 arg0 - Points to load address of FW_CONFIG
Soby Mathew97b1bff2018-09-27 16:46:41 +01001801
1802 arg1 - ``meminfo`` structure populated by BL1. The platform copies
1803 the contents of ``meminfo`` as it may be subsequently overwritten by BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001804
Dan Handley610e7e12018-03-01 18:44:00 +00001805On Arm standard platforms, this function also:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001806
1807- Initializes a UART (PL011 console), which enables access to the ``printf``
1808 family of functions in BL2.
1809
1810- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001811 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1812 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001813
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001814Function : bl2_plat_arch_setup() [mandatory]
1815~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001816
1817::
1818
1819 Argument : void
1820 Return : void
1821
1822This function executes with the MMU and data caches disabled. It is only called
1823by the primary CPU.
1824
1825The purpose of this function is to perform any architectural initialization
1826that varies across platforms.
1827
Dan Handley610e7e12018-03-01 18:44:00 +00001828On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001829
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001830Function : bl2_platform_setup() [mandatory]
1831~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001832
1833::
1834
1835 Argument : void
1836 Return : void
1837
1838This function may execute with the MMU and data caches enabled if the platform
1839port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only
1840called by the primary CPU.
1841
1842The purpose of this function is to perform any platform initialization
1843specific to BL2.
1844
Dan Handley610e7e12018-03-01 18:44:00 +00001845In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001846configuration of the TrustZone controller to allow non-secure masters access
1847to most of DRAM. Part of DRAM is reserved for secure world use.
1848
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001849Function : bl2_plat_handle_pre_image_load() [optional]
1850~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001851
1852::
1853
1854 Argument : unsigned int
1855 Return : int
1856
1857This function can be used by the platforms to update/use image information
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001858for given ``image_id``. This function is currently invoked in BL2 before
Soby Mathew97b1bff2018-09-27 16:46:41 +01001859loading each image.
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001860
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001861Function : bl2_plat_handle_post_image_load() [optional]
1862~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001863
1864::
1865
1866 Argument : unsigned int
1867 Return : int
1868
1869This function can be used by the platforms to update/use image information
1870for given ``image_id``. This function is currently invoked in BL2 after
Soby Mathew97b1bff2018-09-27 16:46:41 +01001871loading each image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001872
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001873Function : bl2_plat_preload_setup [optional]
1874~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001875
1876::
John Tsichritzisee10e792018-06-06 09:38:10 +01001877
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001878 Argument : void
1879 Return : void
1880
1881This optional function performs any BL2 platform initialization
1882required before image loading, that is not done later in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001883bl2_platform_setup(). Specifically, if support for multiple
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001884boot sources is required, it initializes the boot sequence used by
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001885plat_try_next_boot_source().
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001886
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001887Function : plat_try_next_boot_source() [optional]
1888~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001889
1890::
John Tsichritzisee10e792018-06-06 09:38:10 +01001891
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001892 Argument : void
1893 Return : int
1894
1895This optional function passes to the next boot source in the redundancy
1896sequence.
1897
1898This function moves the current boot redundancy source to the next
1899element in the boot sequence. If there are no more boot sources then it
1900must return 0, otherwise it must return 1. The default implementation
1901of this always returns 0.
1902
Roberto Vargasb1584272017-11-20 13:36:10 +00001903Boot Loader Stage 2 (BL2) at EL3
1904--------------------------------
1905
Dan Handley610e7e12018-03-01 18:44:00 +00001906When the platform has a non-TF-A Boot ROM it is desirable to jump
1907directly to BL2 instead of TF-A BL1. In this case BL2 is expected to
Paul Beesleyf8640672019-04-12 14:19:42 +01001908execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design`
1909document for more information.
Roberto Vargasb1584272017-11-20 13:36:10 +00001910
1911All mandatory functions of BL2 must be implemented, except the functions
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001912bl2_early_platform_setup and bl2_el3_plat_arch_setup, because
1913their work is done now by bl2_el3_early_platform_setup and
1914bl2_el3_plat_arch_setup. These functions should generally implement
1915the bl1_plat_xxx() and bl2_plat_xxx() functionality combined.
Roberto Vargasb1584272017-11-20 13:36:10 +00001916
1917
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001918Function : bl2_el3_early_platform_setup() [mandatory]
1919~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001920
1921::
John Tsichritzisee10e792018-06-06 09:38:10 +01001922
Roberto Vargasb1584272017-11-20 13:36:10 +00001923 Argument : u_register_t, u_register_t, u_register_t, u_register_t
1924 Return : void
1925
1926This function executes with the MMU and data caches disabled. It is only called
1927by the primary CPU. This function receives four parameters which can be used
1928by the platform to pass any needed information from the Boot ROM to BL2.
1929
Dan Handley610e7e12018-03-01 18:44:00 +00001930On Arm standard platforms, this function does the following:
Roberto Vargasb1584272017-11-20 13:36:10 +00001931
1932- Initializes a UART (PL011 console), which enables access to the ``printf``
1933 family of functions in BL2.
1934
1935- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001936 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1937 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Roberto Vargasb1584272017-11-20 13:36:10 +00001938
1939- Initializes the private variables that define the memory layout used.
1940
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001941Function : bl2_el3_plat_arch_setup() [mandatory]
1942~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001943
1944::
John Tsichritzisee10e792018-06-06 09:38:10 +01001945
Roberto Vargasb1584272017-11-20 13:36:10 +00001946 Argument : void
1947 Return : void
1948
1949This function executes with the MMU and data caches disabled. It is only called
1950by the primary CPU.
1951
1952The purpose of this function is to perform any architectural initialization
1953that varies across platforms.
1954
Dan Handley610e7e12018-03-01 18:44:00 +00001955On Arm standard platforms, this function enables the MMU.
Roberto Vargasb1584272017-11-20 13:36:10 +00001956
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001957Function : bl2_el3_plat_prepare_exit() [optional]
1958~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001959
1960::
John Tsichritzisee10e792018-06-06 09:38:10 +01001961
Roberto Vargasb1584272017-11-20 13:36:10 +00001962 Argument : void
1963 Return : void
1964
1965This function is called prior to exiting BL2 and run the next image.
1966It should be used to perform platform specific clean up or bookkeeping
1967operations before transferring control to the next image. This function
1968runs with MMU disabled.
1969
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001970FWU Boot Loader Stage 2 (BL2U)
1971------------------------------
1972
1973The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU
1974process and is executed only by the primary CPU. BL1 passes control to BL2U at
1975``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for:
1976
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001977#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure
1978 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1.
1979 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U
1980 should be copied from. Subsequent handling of the SCP_BL2U image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001981 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function.
1982 If ``SCP_BL2U_BASE`` is not defined then this step is not performed.
1983
1984#. Any platform specific setup required to perform the FWU process. For
Dan Handley610e7e12018-03-01 18:44:00 +00001985 example, Arm standard platforms initialize the TZC controller so that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001986 normal world can access DDR memory.
1987
1988The following functions must be implemented by the platform port to enable
1989BL2U to perform the tasks mentioned above.
1990
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001991Function : bl2u_early_platform_setup() [mandatory]
1992~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001993
1994::
1995
1996 Argument : meminfo *mem_info, void *plat_info
1997 Return : void
1998
1999This function executes with the MMU and data caches disabled. It is only
2000called by the primary CPU. The arguments to this function is the address
2001of the ``meminfo`` structure and platform specific info provided by BL1.
2002
2003The platform may copy the contents of the ``mem_info`` and ``plat_info`` into
2004private storage as the original memory may be subsequently overwritten by BL2U.
2005
Dan Handley610e7e12018-03-01 18:44:00 +00002006On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002007to extract SCP_BL2U image information, which is then copied into a private
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002008variable.
2009
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002010Function : bl2u_plat_arch_setup() [mandatory]
2011~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002012
2013::
2014
2015 Argument : void
2016 Return : void
2017
2018This function executes with the MMU and data caches disabled. It is only
2019called by the primary CPU.
2020
2021The purpose of this function is to perform any architectural initialization
2022that varies across platforms, for example enabling the MMU (since the memory
2023map differs across platforms).
2024
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002025Function : bl2u_platform_setup() [mandatory]
2026~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002027
2028::
2029
2030 Argument : void
2031 Return : void
2032
2033This function may execute with the MMU and data caches enabled if the platform
2034port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only
2035called by the primary CPU.
2036
2037The purpose of this function is to perform any platform initialization
2038specific to BL2U.
2039
Dan Handley610e7e12018-03-01 18:44:00 +00002040In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002041configuration of the TrustZone controller to allow non-secure masters access
2042to most of DRAM. Part of DRAM is reserved for secure world use.
2043
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002044Function : bl2u_plat_handle_scp_bl2u() [optional]
2045~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002046
2047::
2048
2049 Argument : void
2050 Return : int
2051
2052This function is used to perform any platform-specific actions required to
2053handle the SCP firmware. Typically it transfers the image into SCP memory using
2054a platform-specific protocol and waits until SCP executes it and signals to the
2055Application Processor (AP) for BL2U execution to continue.
2056
2057This function returns 0 on success, a negative error code otherwise.
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002058This function is included if SCP_BL2U_BASE is defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002059
2060Boot Loader Stage 3-1 (BL31)
2061----------------------------
2062
2063During cold boot, the BL31 stage is executed only by the primary CPU. This is
2064determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes
2065control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all
2066CPUs. BL31 executes at EL3 and is responsible for:
2067
2068#. Re-initializing all architectural and platform state. Although BL1 performs
2069 some of this initialization, BL31 remains resident in EL3 and must ensure
2070 that EL3 architectural and platform state is completely initialized. It
2071 should make no assumptions about the system state when it receives control.
2072
2073#. Passing control to a normal world BL image, pre-loaded at a platform-
Soby Mathew97b1bff2018-09-27 16:46:41 +01002074 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list
2075 populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002076
2077#. Providing runtime firmware services. Currently, BL31 only implements a
2078 subset of the Power State Coordination Interface (PSCI) API as a runtime
Boyan Karatotev907d38b2022-11-22 12:01:09 +00002079 service. See :ref:`psci_in_bl31` below for details of porting the PSCI
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002080 implementation.
2081
2082#. Optionally passing control to the BL32 image, pre-loaded at a platform-
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002083 specific address by BL2. BL31 exports a set of APIs that allow runtime
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002084 services to specify the security state in which the next image should be
Soby Mathew97b1bff2018-09-27 16:46:41 +01002085 executed and run the corresponding image. On ARM platforms, BL31 uses the
2086 ``bl_params`` list populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002087
2088If BL31 is a reset vector, It also needs to handle the reset as specified in
2089section 2.2 before the tasks described above.
2090
2091The following functions must be implemented by the platform port to enable BL31
2092to perform the above tasks.
2093
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002094Function : bl31_early_platform_setup2() [mandatory]
2095~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002096
2097::
2098
Soby Mathew97b1bff2018-09-27 16:46:41 +01002099 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002100 Return : void
2101
2102This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01002103by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are
2104platform specific.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002105
Soby Mathew97b1bff2018-09-27 16:46:41 +01002106In Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002107
Soby Mathew97b1bff2018-09-27 16:46:41 +01002108 arg0 - The pointer to the head of `bl_params_t` list
2109 which is list of executable images following BL31,
2110
2111 arg1 - Points to load address of SOC_FW_CONFIG if present
Mikael Olsson0232da22021-02-12 17:30:16 +01002112 except in case of Arm FVP and Juno platform.
Manish V Badarkhe81414512020-06-24 15:58:38 +01002113
Mikael Olsson0232da22021-02-12 17:30:16 +01002114 In case of Arm FVP and Juno platform, points to load address
Manish V Badarkhe81414512020-06-24 15:58:38 +01002115 of FW_CONFIG.
Soby Mathew97b1bff2018-09-27 16:46:41 +01002116
2117 arg2 - Points to load address of HW_CONFIG if present
2118
2119 arg3 - A special value to verify platform parameters from BL2 to BL31. Not
2120 used in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002121
Soby Mathew97b1bff2018-09-27 16:46:41 +01002122The function runs through the `bl_param_t` list and extracts the entry point
2123information for BL32 and BL33. It also performs the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002124
2125- Initialize a UART (PL011 console), which enables access to the ``printf``
2126 family of functions in BL31.
2127
2128- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the
2129 CCI slave interface corresponding to the cluster that includes the primary
2130 CPU.
2131
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002132Function : bl31_plat_arch_setup() [mandatory]
2133~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002134
2135::
2136
2137 Argument : void
2138 Return : void
2139
2140This function executes with the MMU and data caches disabled. It is only called
2141by the primary CPU.
2142
2143The purpose of this function is to perform any architectural initialization
2144that varies across platforms.
2145
Dan Handley610e7e12018-03-01 18:44:00 +00002146On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002147
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002148Function : bl31_platform_setup() [mandatory]
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002149~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2150
2151::
2152
2153 Argument : void
2154 Return : void
2155
2156This function may execute with the MMU and data caches enabled if the platform
2157port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only
2158called by the primary CPU.
2159
2160The purpose of this function is to complete platform initialization so that both
2161BL31 runtime services and normal world software can function correctly.
2162
Dan Handley610e7e12018-03-01 18:44:00 +00002163On Arm standard platforms, this function does the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002164
2165- Initialize the generic interrupt controller.
2166
2167 Depending on the GIC driver selected by the platform, the appropriate GICv2
2168 or GICv3 initialization will be done, which mainly consists of:
2169
2170 - Enable secure interrupts in the GIC CPU interface.
2171 - Disable the legacy interrupt bypass mechanism.
2172 - Configure the priority mask register to allow interrupts of all priorities
2173 to be signaled to the CPU interface.
2174 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure.
2175 - Target all secure SPIs to CPU0.
2176 - Enable these secure interrupts in the GIC distributor.
2177 - Configure all other interrupts as non-secure.
2178 - Enable signaling of secure interrupts in the GIC distributor.
2179
2180- Enable system-level implementation of the generic timer counter through the
2181 memory mapped interface.
2182
2183- Grant access to the system counter timer module
2184
2185- Initialize the power controller device.
2186
2187 In particular, initialise the locks that prevent concurrent accesses to the
2188 power controller device.
2189
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002190Function : bl31_plat_runtime_setup() [optional]
2191~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002192
2193::
2194
2195 Argument : void
2196 Return : void
2197
2198The purpose of this function is allow the platform to perform any BL31 runtime
2199setup just prior to BL31 exit during cold boot. The default weak
Julius Werneraae9bb12017-09-18 16:49:48 -07002200implementation of this function will invoke ``console_switch_state()`` to switch
2201console output to consoles marked for use in the ``runtime`` state.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002202
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002203Function : bl31_plat_get_next_image_ep_info() [mandatory]
2204~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002205
2206::
2207
Sandrine Bailleux842117d2018-05-14 14:25:47 +02002208 Argument : uint32_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002209 Return : entry_point_info *
2210
2211This function may execute with the MMU and data caches enabled if the platform
2212port does the necessary initializations in ``bl31_plat_arch_setup()``.
2213
2214This function is called by ``bl31_main()`` to retrieve information provided by
2215BL2 for the next image in the security state specified by the argument. BL31
2216uses this information to pass control to that image in the specified security
2217state. This function must return a pointer to the ``entry_point_info`` structure
2218(that was copied during ``bl31_early_platform_setup()``) if the image exists. It
2219should return NULL otherwise.
2220
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002221Function : plat_rmmd_get_cca_attest_token() [mandatory when ENABLE_RME == 1]
Soby Mathew294e1cf2022-03-22 16:19:39 +00002222~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2223
2224::
2225
2226 Argument : uintptr_t, size_t *, uintptr_t, size_t
2227 Return : int
2228
2229This function returns the Platform attestation token.
2230
2231The parameters of the function are:
2232
2233 arg0 - A pointer to the buffer where the Platform token should be copied by
2234 this function. The buffer must be big enough to hold the Platform
2235 token.
2236
2237 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
2238 function returns the platform token length in this parameter.
2239
2240 arg2 - A pointer to the buffer where the challenge object is stored.
2241
2242 arg3 - The length of the challenge object in bytes. Possible values are 32,
2243 48 and 64.
2244
2245The function returns 0 on success, -EINVAL on failure.
2246
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002247Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1]
2248~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewf05d93a2022-03-22 16:21:19 +00002249
2250::
2251
2252 Argument : uintptr_t, size_t *, unsigned int
2253 Return : int
2254
2255This function returns the delegated realm attestation key which will be used to
2256sign Realm attestation token. The API currently only supports P-384 ECC curve
2257key.
2258
2259The parameters of the function are:
2260
2261 arg0 - A pointer to the buffer where the attestation key should be copied
2262 by this function. The buffer must be big enough to hold the
2263 attestation key.
2264
2265 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
2266 function returns the attestation key length in this parameter.
2267
2268 arg2 - The type of the elliptic curve to which the requested attestation key
2269 belongs.
2270
2271The function returns 0 on success, -EINVAL on failure.
2272
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002273Function : plat_rmmd_get_el3_rmm_shared_mem() [when ENABLE_RME == 1]
2274~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2275
2276::
2277
2278 Argument : uintptr_t *
2279 Return : size_t
2280
2281This function returns the size of the shared area between EL3 and RMM (or 0 on
2282failure). A pointer to the shared area (or a NULL pointer on failure) is stored
2283in the pointer passed as argument.
2284
Javier Almansa Sobrino4165e842022-04-25 17:18:15 +01002285Function : plat_rmmd_load_manifest() [when ENABLE_RME == 1]
2286~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2287
2288::
2289
2290 Arguments : rmm_manifest_t *manifest
2291 Return : int
2292
2293When ENABLE_RME is enabled, this function populates a boot manifest for the
2294RMM image and stores it in the area specified by manifest.
2295
2296When ENABLE_RME is disabled, this function is not used.
2297
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01002298Function : bl31_plat_enable_mmu [optional]
2299~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2300
2301::
2302
2303 Argument : uint32_t
2304 Return : void
2305
2306This function enables the MMU. The boot code calls this function with MMU and
2307caches disabled. This function should program necessary registers to enable
2308translation, and upon return, the MMU on the calling PE must be enabled.
2309
2310The function must honor flags passed in the first argument. These flags are
2311defined by the translation library, and can be found in the file
2312``include/lib/xlat_tables/xlat_mmu_helpers.h``.
2313
2314On DynamIQ systems, this function must not use stack while enabling MMU, which
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002315is how the function in xlat table library version 2 is implemented.
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01002316
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002317Function : plat_init_apkey [optional]
2318~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002319
2320::
2321
2322 Argument : void
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002323 Return : uint128_t
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002324
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002325This function returns the 128-bit value which can be used to program ARMv8.3
2326pointer authentication keys.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002327
2328The value should be obtained from a reliable source of randomness.
2329
2330This function is only needed if ARMv8.3 pointer authentication is used in the
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002331Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002332
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002333Function : plat_get_syscnt_freq2() [mandatory]
2334~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002335
2336::
2337
2338 Argument : void
2339 Return : unsigned int
2340
2341This function is used by the architecture setup code to retrieve the counter
2342frequency for the CPU's generic timer. This value will be programmed into the
Dan Handley610e7e12018-03-01 18:44:00 +00002343``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002344of the system counter, which is retrieved from the first entry in the frequency
2345modes table.
2346
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002347#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]
2348~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002349
2350When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in
2351bytes) aligned to the cache line boundary that should be allocated per-cpu to
2352accommodate all the bakery locks.
2353
2354If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker
Chris Kay33bfc5e2023-02-14 11:30:04 +00002355calculates the size of the ``.bakery_lock`` input section, aligns it to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002356nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT``
2357and stores the result in a linker symbol. This constant prevents a platform
2358from relying on the linker and provide a more efficient mechanism for
2359accessing per-cpu bakery lock information.
2360
2361If this constant is defined and its value is not equal to the value
2362calculated by the linker then a link time assertion is raised. A compile time
2363assertion is raised if the value of the constant is not aligned to the cache
2364line boundary.
2365
Paul Beesleyf8640672019-04-12 14:19:42 +01002366.. _porting_guide_sdei_requirements:
2367
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002368SDEI porting requirements
2369~~~~~~~~~~~~~~~~~~~~~~~~~
2370
Paul Beesley606d8072019-03-13 13:58:02 +00002371The |SDEI| dispatcher requires the platform to provide the following macros
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002372and functions, of which some are optional, and some others mandatory.
2373
2374Macros
2375......
2376
2377Macro: PLAT_SDEI_NORMAL_PRI [mandatory]
2378^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2379
2380This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00002381Normal |SDEI| events on the platform. This must have a higher value
2382(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002383
2384Macro: PLAT_SDEI_CRITICAL_PRI [mandatory]
2385^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2386
2387This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00002388Critical |SDEI| events on the platform. This must have a lower value
2389(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002390
Paul Beesley606d8072019-03-13 13:58:02 +00002391**Note**: |SDEI| exception priorities must be the lowest among Secure
2392priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must
2393be higher than Normal |SDEI| priority.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002394
2395Functions
2396.........
2397
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002398Function: int plat_sdei_validate_entry_point() [optional]
2399^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002400
2401::
2402
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002403 Argument: uintptr_t ep, unsigned int client_mode
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002404 Return: int
2405
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002406This function validates the entry point address of the event handler provided by
2407the client for both event registration and *Complete and Resume* |SDEI| calls.
2408The function ensures that the address is valid in the client translation regime.
2409
2410The second argument is the exception level that the client is executing in. It
2411can be Non-Secure EL1 or Non-Secure EL2.
2412
2413The function must return ``0`` for successful validation, or ``-1`` upon failure.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002414
Dan Handley610e7e12018-03-01 18:44:00 +00002415The default implementation always returns ``0``. On Arm platforms, this function
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002416translates the entry point address within the client translation regime and
2417further ensures that the resulting physical address is located in Non-secure
2418DRAM.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002419
2420Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional]
2421^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2422
2423::
2424
2425 Argument: uint64_t
2426 Argument: unsigned int
2427 Return: void
2428
Paul Beesley606d8072019-03-13 13:58:02 +00002429|SDEI| specification requires that a PE comes out of reset with the events
2430masked. The client therefore is expected to call ``PE_UNMASK`` to unmask
2431|SDEI| events on the PE. No |SDEI| events can be dispatched until such
2432time.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002433
Paul Beesley606d8072019-03-13 13:58:02 +00002434Should a PE receive an interrupt that was bound to an |SDEI| event while the
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002435events are masked on the PE, the dispatcher implementation invokes the function
2436``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the
2437interrupt and the interrupt ID are passed as parameters.
2438
2439The default implementation only prints out a warning message.
2440
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -05002441.. _porting_guide_trng_requirements:
2442
2443TRNG porting requirements
2444~~~~~~~~~~~~~~~~~~~~~~~~~
2445
2446The |TRNG| backend requires the platform to provide the following values
2447and mandatory functions.
2448
2449Values
2450......
2451
2452value: uuid_t plat_trng_uuid [mandatory]
2453^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2454
2455This value must be defined to the UUID of the TRNG backend that is specific to
Jayanth Dodderi Chidanand7c7faff2022-10-11 17:16:07 +01002456the hardware after ``plat_entropy_setup`` function is called. This value must
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -05002457conform to the SMCCC calling convention; The most significant 32 bits of the
2458UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in
2459w0 indicates failure to get a TRNG source.
2460
2461Functions
2462.........
2463
2464Function: void plat_entropy_setup(void) [mandatory]
2465^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2466
2467::
2468
2469 Argument: none
2470 Return: none
2471
2472This function is expected to do platform-specific initialization of any TRNG
2473hardware. This may include generating a UUID from a hardware-specific seed.
2474
2475Function: bool plat_get_entropy(uint64_t \*out) [mandatory]
2476^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2477
2478::
2479
2480 Argument: uint64_t *
2481 Return: bool
2482 Out : when the return value is true, the entropy has been written into the
2483 storage pointed to
2484
2485This function writes entropy into storage provided by the caller. If no entropy
2486is available, it must return false and the storage must not be written.
2487
Boyan Karatotev907d38b2022-11-22 12:01:09 +00002488.. _psci_in_bl31:
2489
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002490Power State Coordination Interface (in BL31)
2491--------------------------------------------
2492
Dan Handley610e7e12018-03-01 18:44:00 +00002493The TF-A implementation of the PSCI API is based around the concept of a
2494*power domain*. A *power domain* is a CPU or a logical group of CPUs which
2495share some state on which power management operations can be performed as
2496specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is
2497a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The
2498*power domains* are arranged in a hierarchical tree structure and each
2499*power domain* can be identified in a system by the cpu index of any CPU that
2500is part of that domain and a *power domain level*. A processing element (for
2501example, a CPU) is at level 0. If the *power domain* node above a CPU is a
2502logical grouping of CPUs that share some state, then level 1 is that group of
2503CPUs (for example, a cluster), and level 2 is a group of clusters (for
2504example, the system). More details on the power domain topology and its
Paul Beesleyf8640672019-04-12 14:19:42 +01002505organization can be found in :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002506
2507BL31's platform initialization code exports a pointer to the platform-specific
2508power management operations required for the PSCI implementation to function
2509correctly. This information is populated in the ``plat_psci_ops`` structure. The
2510PSCI implementation calls members of the ``plat_psci_ops`` structure for performing
2511power management operations on the power domains. For example, the target
2512CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()``
2513handler (if present) is called for the CPU power domain.
2514
2515The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to
2516describe composite power states specific to a platform. The PSCI implementation
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00002517defines a generic representation of the power-state parameter, which is an
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002518array of local power states where each index corresponds to a power domain
2519level. Each entry contains the local power state the power domain at that power
2520level could enter. It depends on the ``validate_power_state()`` handler to
2521convert the power-state parameter (possibly encoding a composite power state)
2522passed in a PSCI ``CPU_SUSPEND`` call to this representation.
2523
2524The following functions form part of platform port of PSCI functionality.
2525
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002526Function : plat_psci_stat_accounting_start() [optional]
2527~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002528
2529::
2530
2531 Argument : const psci_power_state_t *
2532 Return : void
2533
2534This is an optional hook that platforms can implement for residency statistics
2535accounting before entering a low power state. The ``pwr_domain_state`` field of
2536``state_info`` (first argument) can be inspected if stat accounting is done
2537differently at CPU level versus higher levels. As an example, if the element at
2538index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2539state, special hardware logic may be programmed in order to keep track of the
2540residency statistics. For higher levels (array indices > 0), the residency
2541statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2542default implementation will use PMF to capture timestamps.
2543
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002544Function : plat_psci_stat_accounting_stop() [optional]
2545~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002546
2547::
2548
2549 Argument : const psci_power_state_t *
2550 Return : void
2551
2552This is an optional hook that platforms can implement for residency statistics
2553accounting after exiting from a low power state. The ``pwr_domain_state`` field
2554of ``state_info`` (first argument) can be inspected if stat accounting is done
2555differently at CPU level versus higher levels. As an example, if the element at
2556index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2557state, special hardware logic may be programmed in order to keep track of the
2558residency statistics. For higher levels (array indices > 0), the residency
2559statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2560default implementation will use PMF to capture timestamps.
2561
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002562Function : plat_psci_stat_get_residency() [optional]
2563~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002564
2565::
2566
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -06002567 Argument : unsigned int, const psci_power_state_t *, unsigned int
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002568 Return : u_register_t
2569
2570This is an optional interface that is is invoked after resuming from a low power
2571state and provides the time spent resident in that low power state by the power
2572domain at a particular power domain level. When a CPU wakes up from suspend,
2573all its parent power domain levels are also woken up. The generic PSCI code
2574invokes this function for each parent power domain that is resumed and it
2575identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second
2576argument) describes the low power state that the power domain has resumed from.
2577The current CPU is the first CPU in the power domain to resume from the low
2578power state and the ``last_cpu_idx`` (third parameter) is the index of the last
2579CPU in the power domain to suspend and may be needed to calculate the residency
2580for that power domain.
2581
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002582Function : plat_get_target_pwr_state() [optional]
2583~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002584
2585::
2586
2587 Argument : unsigned int, const plat_local_state_t *, unsigned int
2588 Return : plat_local_state_t
2589
2590The PSCI generic code uses this function to let the platform participate in
2591state coordination during a power management operation. The function is passed
2592a pointer to an array of platform specific local power state ``states`` (second
2593argument) which contains the requested power state for each CPU at a particular
2594power domain level ``lvl`` (first argument) within the power domain. The function
2595is expected to traverse this array of upto ``ncpus`` (third argument) and return
2596a coordinated target power state by the comparing all the requested power
2597states. The target power state should not be deeper than any of the requested
2598power states.
2599
2600A weak definition of this API is provided by default wherein it assumes
2601that the platform assigns a local state value in order of increasing depth
2602of the power state i.e. for two power states X & Y, if X < Y
2603then X represents a shallower power state than Y. As a result, the
2604coordinated target local power state for a power domain will be the minimum
2605of the requested local power state values.
2606
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002607Function : plat_get_power_domain_tree_desc() [mandatory]
2608~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002609
2610::
2611
2612 Argument : void
2613 Return : const unsigned char *
2614
2615This function returns a pointer to the byte array containing the power domain
2616topology tree description. The format and method to construct this array are
Paul Beesleyf8640672019-04-12 14:19:42 +01002617described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI
2618initialization code requires this array to be described by the platform, either
2619statically or dynamically, to initialize the power domain topology tree. In case
2620the array is populated dynamically, then plat_core_pos_by_mpidr() and
2621plat_my_core_pos() should also be implemented suitably so that the topology tree
2622description matches the CPU indices returned by these APIs. These APIs together
2623form the platform interface for the PSCI topology framework.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002624
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002625Function : plat_setup_psci_ops() [mandatory]
2626~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002627
2628::
2629
2630 Argument : uintptr_t, const plat_psci_ops **
2631 Return : int
2632
2633This function may execute with the MMU and data caches enabled if the platform
2634port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
2635called by the primary CPU.
2636
2637This function is called by PSCI initialization code. Its purpose is to let
2638the platform layer know about the warm boot entrypoint through the
2639``sec_entrypoint`` (first argument) and to export handler routines for
2640platform-specific psci power management actions by populating the passed
2641pointer with a pointer to BL31's private ``plat_psci_ops`` structure.
2642
2643A description of each member of this structure is given below. Please refer to
Dan Handley610e7e12018-03-01 18:44:00 +00002644the Arm FVP specific implementation of these handlers in
Paul Beesleyf8640672019-04-12 14:19:42 +01002645``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002646platform wants to support, the associated operation or operations in this
2647structure must be provided and implemented (Refer section 4 of
Paul Beesleyf8640672019-04-12 14:19:42 +01002648:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI
Dan Handley610e7e12018-03-01 18:44:00 +00002649function in a platform port, the operation should be removed from this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002650structure instead of providing an empty implementation.
2651
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002652plat_psci_ops.cpu_standby()
2653...........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002654
2655Perform the platform-specific actions to enter the standby state for a cpu
2656indicated by the passed argument. This provides a fast path for CPU standby
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002657wherein overheads of PSCI state management and lock acquisition is avoided.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002658For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation,
2659the suspend state type specified in the ``power-state`` parameter should be
2660STANDBY and the target power domain level specified should be the CPU. The
2661handler should put the CPU into a low power retention state (usually by
2662issuing a wfi instruction) and ensure that it can be woken up from that
2663state by a normal interrupt. The generic code expects the handler to succeed.
2664
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002665plat_psci_ops.pwr_domain_on()
2666.............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002667
2668Perform the platform specific actions to power on a CPU, specified
2669by the ``MPIDR`` (first argument). The generic code expects the platform to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002670return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002671
Varun Wadekar77dd4f12023-04-25 14:03:27 +01002672plat_psci_ops.pwr_domain_off_early() [optional]
2673...............................................
2674
2675This optional function performs the platform specific actions to check if
2676powering off the calling CPU and its higher parent power domain levels as
2677indicated by the ``target_state`` (first argument) is possible or allowed.
2678
2679The ``target_state`` encodes the platform coordinated target local power states
2680for the CPU power domain and its parent power domain levels.
2681
2682For this handler, the local power state for the CPU power domain will be a
2683power down state where as it could be either power down, retention or run state
2684for the higher power domain levels depending on the result of state
2685coordination. The generic code expects PSCI_E_DENIED return code if the
2686platform thinks that CPU_OFF should not proceed on the calling CPU.
2687
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002688plat_psci_ops.pwr_domain_off()
2689..............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002690
2691Perform the platform specific actions to prepare to power off the calling CPU
2692and its higher parent power domain levels as indicated by the ``target_state``
2693(first argument). It is called by the PSCI ``CPU_OFF`` API implementation.
2694
2695The ``target_state`` encodes the platform coordinated target local power states
2696for the CPU power domain and its parent power domain levels. The handler
2697needs to perform power management operation corresponding to the local state
2698at each power level.
2699
2700For this handler, the local power state for the CPU power domain will be a
2701power down state where as it could be either power down, retention or run state
2702for the higher power domain levels depending on the result of state
2703coordination. The generic code expects the handler to succeed.
2704
Wing Lic0dc6392023-05-04 08:31:19 -07002705plat_psci_ops.pwr_domain_validate_suspend() [optional]
2706......................................................
2707
2708This is an optional function that is only compiled into the build if the build
2709option ``PSCI_OS_INIT_MODE`` is enabled.
2710
2711If implemented, this function allows the platform to perform platform specific
2712validations based on hardware states. The generic code expects this function to
2713return PSCI_E_SUCCESS on success, or either PSCI_E_DENIED or
2714PSCI_E_INVALID_PARAMS as appropriate for any invalid requests.
2715
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002716plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]
2717...........................................................
Varun Wadekarae87f4b2017-07-10 16:02:05 -07002718
2719This optional function may be used as a performance optimization to replace
2720or complement pwr_domain_suspend() on some platforms. Its calling semantics
2721are identical to pwr_domain_suspend(), except the PSCI implementation only
2722calls this function when suspending to a power down state, and it guarantees
2723that data caches are enabled.
2724
2725When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches
2726before calling pwr_domain_suspend(). If the target_state corresponds to a
2727power down state and it is safe to perform some or all of the platform
2728specific actions in that function with data caches enabled, it may be more
2729efficient to move those actions to this function. When HW_ASSISTED_COHERENCY
2730= 1, data caches remain enabled throughout, and so there is no advantage to
2731moving platform specific actions to this function.
2732
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002733plat_psci_ops.pwr_domain_suspend()
2734..................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002735
2736Perform the platform specific actions to prepare to suspend the calling
2737CPU and its higher parent power domain levels as indicated by the
2738``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND``
2739API implementation.
2740
2741The ``target_state`` has a similar meaning as described in
2742the ``pwr_domain_off()`` operation. It encodes the platform coordinated
2743target local power states for the CPU power domain and its parent
2744power domain levels. The handler needs to perform power management operation
2745corresponding to the local state at each power level. The generic code
2746expects the handler to succeed.
2747
Douglas Raillarda84996b2017-08-02 16:57:32 +01002748The difference between turning a power domain off versus suspending it is that
2749in the former case, the power domain is expected to re-initialize its state
2750when it is next powered on (see ``pwr_domain_on_finish()``). In the latter
2751case, the power domain is expected to save enough state so that it can resume
2752execution by restoring this state when its powered on (see
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002753``pwr_domain_suspend_finish()``).
2754
Douglas Raillarda84996b2017-08-02 16:57:32 +01002755When suspending a core, the platform can also choose to power off the GICv3
2756Redistributor and ITS through an implementation-defined sequence. To achieve
2757this safely, the ITS context must be saved first. The architectural part is
2758implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed
2759sequence is implementation defined and it is therefore the responsibility of
2760the platform code to implement the necessary sequence. Then the GIC
2761Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper.
2762Powering off the Redistributor requires the implementation to support it and it
2763is the responsibility of the platform code to execute the right implementation
2764defined sequence.
2765
2766When a system suspend is requested, the platform can also make use of the
2767``gicv3_distif_save()`` helper to save the context of the GIC Distributor after
2768it has saved the context of the Redistributors and ITS of all the cores in the
2769system. The context of the Distributor can be large and may require it to be
2770allocated in a special area if it cannot fit in the platform's global static
2771data, for example in DRAM. The Distributor can then be powered down using an
2772implementation-defined sequence.
2773
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002774plat_psci_ops.pwr_domain_pwr_down_wfi()
2775.......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002776
2777This is an optional function and, if implemented, is expected to perform
2778platform specific actions including the ``wfi`` invocation which allows the
2779CPU to powerdown. Since this function is invoked outside the PSCI locks,
2780the actions performed in this hook must be local to the CPU or the platform
2781must ensure that races between multiple CPUs cannot occur.
2782
2783The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()``
2784operation and it encodes the platform coordinated target local power states for
2785the CPU power domain and its parent power domain levels. This function must
Boyan Karatotev43771f32022-10-05 13:41:56 +01002786not return back to the caller (by calling wfi in an infinite loop to ensure
2787some CPUs power down mitigations work properly).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002788
2789If this function is not implemented by the platform, PSCI generic
2790implementation invokes ``psci_power_down_wfi()`` for power down.
2791
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002792plat_psci_ops.pwr_domain_on_finish()
2793....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002794
2795This function is called by the PSCI implementation after the calling CPU is
2796powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
2797It performs the platform-specific setup required to initialize enough state for
2798this CPU to enter the normal world and also provide secure runtime firmware
2799services.
2800
2801The ``target_state`` (first argument) is the prior state of the power domains
2802immediately before the CPU was turned on. It indicates which power domains
2803above the CPU might require initialization due to having previously been in
2804low power states. The generic code expects the handler to succeed.
2805
Madhukar Pappireddy33bd5142019-08-12 18:31:33 -05002806plat_psci_ops.pwr_domain_on_finish_late() [optional]
2807...........................................................
2808
2809This optional function is called by the PSCI implementation after the calling
2810CPU is fully powered on with respective data caches enabled. The calling CPU and
2811the associated cluster are guaranteed to be participating in coherency. This
2812function gives the flexibility to perform any platform-specific actions safely,
2813such as initialization or modification of shared data structures, without the
2814overhead of explicit cache maintainace operations.
2815
2816The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()``
2817operation. The generic code expects the handler to succeed.
2818
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002819plat_psci_ops.pwr_domain_suspend_finish()
2820.........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002821
2822This function is called by the PSCI implementation after the calling CPU is
2823powered on and released from reset in response to an asynchronous wakeup
2824event, for example a timer interrupt that was programmed by the CPU during the
2825``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
2826setup required to restore the saved state for this CPU to resume execution
2827in the normal world and also provide secure runtime firmware services.
2828
2829The ``target_state`` (first argument) has a similar meaning as described in
2830the ``pwr_domain_on_finish()`` operation. The generic code expects the platform
2831to succeed.
2832
Douglas Raillarda84996b2017-08-02 16:57:32 +01002833If the Distributor, Redistributors or ITS have been powered off as part of a
2834suspend, their context must be restored in this function in the reverse order
2835to how they were saved during suspend sequence.
2836
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002837plat_psci_ops.system_off()
2838..........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002839
2840This function is called by PSCI implementation in response to a ``SYSTEM_OFF``
2841call. It performs the platform-specific system poweroff sequence after
2842notifying the Secure Payload Dispatcher.
2843
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002844plat_psci_ops.system_reset()
2845............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002846
2847This function is called by PSCI implementation in response to a ``SYSTEM_RESET``
2848call. It performs the platform-specific system reset sequence after
2849notifying the Secure Payload Dispatcher.
2850
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002851plat_psci_ops.validate_power_state()
2852....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002853
2854This function is called by the PSCI implementation during the ``CPU_SUSPEND``
2855call to validate the ``power_state`` parameter of the PSCI API and if valid,
2856populate it in ``req_state`` (second argument) array as power domain level
2857specific local states. If the ``power_state`` is invalid, the platform must
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002858return PSCI_E_INVALID_PARAMS as error, which is propagated back to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002859normal world PSCI client.
2860
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002861plat_psci_ops.validate_ns_entrypoint()
2862......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002863
2864This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
2865``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point``
2866parameter passed by the normal world. If the ``entry_point`` is invalid,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002867the platform must return PSCI_E_INVALID_ADDRESS as error, which is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002868propagated back to the normal world PSCI client.
2869
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002870plat_psci_ops.get_sys_suspend_power_state()
2871...........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002872
2873This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
2874call to get the ``req_state`` parameter from platform which encodes the power
2875domain level specific local states to suspend to system affinity level. The
2876``req_state`` will be utilized to do the PSCI state coordination and
2877``pwr_domain_suspend()`` will be invoked with the coordinated target state to
2878enter system suspend.
2879
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002880plat_psci_ops.get_pwr_lvl_state_idx()
2881.....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002882
2883This is an optional function and, if implemented, is invoked by the PSCI
2884implementation to convert the ``local_state`` (first argument) at a specified
2885``pwr_lvl`` (second argument) to an index between 0 and
2886``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform
2887supports more than two local power states at each power domain level, that is
2888``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these
2889local power states.
2890
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002891plat_psci_ops.translate_power_state_by_mpidr()
2892..............................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002893
2894This is an optional function and, if implemented, verifies the ``power_state``
2895(second argument) parameter of the PSCI API corresponding to a target power
2896domain. The target power domain is identified by using both ``MPIDR`` (first
2897argument) and the power domain level encoded in ``power_state``. The power domain
2898level specific local states are to be extracted from ``power_state`` and be
2899populated in the ``output_state`` (third argument) array. The functionality
2900is similar to the ``validate_power_state`` function described above and is
2901envisaged to be used in case the validity of ``power_state`` depend on the
2902targeted power domain. If the ``power_state`` is invalid for the targeted power
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002903domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002904function is not implemented, then the generic implementation relies on
2905``validate_power_state`` function to translate the ``power_state``.
2906
2907This function can also be used in case the platform wants to support local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002908power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002909APIs as described in Section 5.18 of `PSCI`_.
2910
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002911plat_psci_ops.get_node_hw_state()
2912.................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002913
2914This is an optional function. If implemented this function is intended to return
2915the power state of a node (identified by the first parameter, the ``MPIDR``) in
2916the power domain topology (identified by the second parameter, ``power_level``),
2917as retrieved from a power controller or equivalent component on the platform.
2918Upon successful completion, the implementation must map and return the final
2919status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it
2920must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as
2921appropriate.
2922
2923Implementations are not expected to handle ``power_levels`` greater than
2924``PLAT_MAX_PWR_LVL``.
2925
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002926plat_psci_ops.system_reset2()
2927.............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002928
2929This is an optional function. If implemented this function is
2930called during the ``SYSTEM_RESET2`` call to perform a reset
2931based on the first parameter ``reset_type`` as specified in
2932`PSCI`_. The parameter ``cookie`` can be used to pass additional
2933reset information. If the ``reset_type`` is not supported, the
2934function must return ``PSCI_E_NOT_SUPPORTED``. For architectural
2935resets, all failures must return ``PSCI_E_INVALID_PARAMETERS``
2936and vendor reset can return other PSCI error codes as defined
2937in `PSCI`_. On success this function will not return.
2938
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002939plat_psci_ops.write_mem_protect()
2940.................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002941
2942This is an optional function. If implemented it enables or disables the
2943``MEM_PROTECT`` functionality based on the value of ``val``.
2944A non-zero value enables ``MEM_PROTECT`` and a value of zero
2945disables it. Upon encountering failures it must return a negative value
2946and on success it must return 0.
2947
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002948plat_psci_ops.read_mem_protect()
2949................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002950
2951This is an optional function. If implemented it returns the current
2952state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering
2953failures it must return a negative value and on success it must
2954return 0.
2955
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002956plat_psci_ops.mem_protect_chk()
2957...............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002958
2959This is an optional function. If implemented it checks if a memory
2960region defined by a base address ``base`` and with a size of ``length``
2961bytes is protected by ``MEM_PROTECT``. If the region is protected
2962then it must return 0, otherwise it must return a negative number.
2963
Paul Beesleyf8640672019-04-12 14:19:42 +01002964.. _porting_guide_imf_in_bl31:
2965
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002966Interrupt Management framework (in BL31)
2967----------------------------------------
2968
2969BL31 implements an Interrupt Management Framework (IMF) to manage interrupts
2970generated in either security state and targeted to EL1 or EL2 in the non-secure
2971state or EL3/S-EL1 in the secure state. The design of this framework is
Paul Beesleyf8640672019-04-12 14:19:42 +01002972described in the :ref:`Interrupt Management Framework`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002973
2974A platform should export the following APIs to support the IMF. The following
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002975text briefly describes each API and its implementation in Arm standard
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002976platforms. The API implementation depends upon the type of interrupt controller
Dan Handley610e7e12018-03-01 18:44:00 +00002977present in the platform. Arm standard platform layer supports both
2978`Arm Generic Interrupt Controller version 2.0 (GICv2)`_
2979and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the
2980FVP can be configured to use either GICv2 or GICv3 depending on the build flag
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01002981``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more
2982details).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002983
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05002984See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`.
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002985
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002986Function : plat_interrupt_type_to_line() [mandatory]
2987~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002988
2989::
2990
2991 Argument : uint32_t, uint32_t
2992 Return : uint32_t
2993
Dan Handley610e7e12018-03-01 18:44:00 +00002994The Arm processor signals an interrupt exception either through the IRQ or FIQ
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002995interrupt line. The specific line that is signaled depends on how the interrupt
2996controller (IC) reports different interrupt types from an execution context in
2997either security state. The IMF uses this API to determine which interrupt line
2998the platform IC uses to signal each type of interrupt supported by the framework
2999from a given security state. This API must be invoked at EL3.
3000
3001The first parameter will be one of the ``INTR_TYPE_*`` values (see
Paul Beesleyf8640672019-04-12 14:19:42 +01003002:ref:`Interrupt Management Framework`) indicating the target type of the
3003interrupt, the second parameter is the security state of the originating
3004execution context. The return result is the bit position in the ``SCR_EL3``
3005register of the respective interrupt trap: IRQ=1, FIQ=2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003006
Dan Handley610e7e12018-03-01 18:44:00 +00003007In the case of Arm standard platforms using GICv2, S-EL1 interrupts are
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003008configured as FIQs and Non-secure interrupts as IRQs from either security
3009state.
3010
Dan Handley610e7e12018-03-01 18:44:00 +00003011In the case of Arm standard platforms using GICv3, the interrupt line to be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003012configured depends on the security state of the execution context when the
3013interrupt is signalled and are as follows:
3014
3015- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in
3016 NS-EL0/1/2 context.
3017- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ
3018 in the NS-EL0/1/2 context.
3019- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2
3020 context.
3021
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003022Function : plat_ic_get_pending_interrupt_type() [mandatory]
3023~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003024
3025::
3026
3027 Argument : void
3028 Return : uint32_t
3029
3030This API returns the type of the highest priority pending interrupt at the
3031platform IC. The IMF uses the interrupt type to retrieve the corresponding
3032handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt
3033pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``,
3034``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3.
3035
Dan Handley610e7e12018-03-01 18:44:00 +00003036In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003037Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of
3038the pending interrupt. The type of interrupt depends upon the id value as
3039follows.
3040
3041#. id < 1022 is reported as a S-EL1 interrupt
3042#. id = 1022 is reported as a Non-secure interrupt.
3043#. id = 1023 is reported as an invalid interrupt type.
3044
Dan Handley610e7e12018-03-01 18:44:00 +00003045In the case of Arm standard platforms using GICv3, the system register
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003046``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*,
3047is read to determine the id of the pending interrupt. The type of interrupt
3048depends upon the id value as follows.
3049
3050#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt
3051#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt.
3052#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type.
3053#. All other interrupt id's are reported as EL3 interrupt.
3054
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003055Function : plat_ic_get_pending_interrupt_id() [mandatory]
3056~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003057
3058::
3059
3060 Argument : void
3061 Return : uint32_t
3062
3063This API returns the id of the highest priority pending interrupt at the
3064platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt
3065pending.
3066
Dan Handley610e7e12018-03-01 18:44:00 +00003067In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003068Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the
3069pending interrupt. The id that is returned by API depends upon the value of
3070the id read from the interrupt controller as follows.
3071
3072#. id < 1022. id is returned as is.
3073#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register*
3074 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt.
3075 This id is returned by the API.
3076#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned.
3077
Dan Handley610e7e12018-03-01 18:44:00 +00003078In the case of Arm standard platforms using GICv3, if the API is invoked from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003079EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt
3080group 0 Register*, is read to determine the id of the pending interrupt. The id
3081that is returned by API depends upon the value of the id read from the
3082interrupt controller as follows.
3083
3084#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is.
3085#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system
3086 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1
3087 Register* is read to determine the id of the group 1 interrupt. This id
3088 is returned by the API as long as it is a valid interrupt id
3089#. If the id is any of the special interrupt identifiers,
3090 ``INTR_ID_UNAVAILABLE`` is returned.
3091
3092When the API invoked from S-EL1 for GICv3 systems, the id read from system
3093register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003094Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003095``INTR_ID_UNAVAILABLE`` is returned.
3096
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003097Function : plat_ic_acknowledge_interrupt() [mandatory]
3098~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003099
3100::
3101
3102 Argument : void
3103 Return : uint32_t
3104
3105This API is used by the CPU to indicate to the platform IC that processing of
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01003106the highest pending interrupt has begun. It should return the raw, unmodified
3107value obtained from the interrupt controller when acknowledging an interrupt.
3108The actual interrupt number shall be extracted from this raw value using the API
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05003109`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003110
Dan Handley610e7e12018-03-01 18:44:00 +00003111This function in Arm standard platforms using GICv2, reads the *Interrupt
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003112Acknowledge Register* (``GICC_IAR``). This changes the state of the highest
3113priority pending interrupt from pending to active in the interrupt controller.
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01003114It returns the value read from the ``GICC_IAR``, unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003115
Dan Handley610e7e12018-03-01 18:44:00 +00003116In the case of Arm standard platforms using GICv3, if the API is invoked
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003117from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt
3118Acknowledge Register group 0*. If the API is invoked from S-EL1, the function
3119reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register
3120group 1*. The read changes the state of the highest pending interrupt from
3121pending to active in the interrupt controller. The value read is returned
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01003122unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003123
3124The TSP uses this API to start processing of the secure physical timer
3125interrupt.
3126
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003127Function : plat_ic_end_of_interrupt() [mandatory]
3128~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003129
3130::
3131
3132 Argument : uint32_t
3133 Return : void
3134
3135This API is used by the CPU to indicate to the platform IC that processing of
3136the interrupt corresponding to the id (passed as the parameter) has
3137finished. The id should be the same as the id returned by the
3138``plat_ic_acknowledge_interrupt()`` API.
3139
Dan Handley610e7e12018-03-01 18:44:00 +00003140Arm standard platforms write the id to the *End of Interrupt Register*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003141(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1``
3142system register in case of GICv3 depending on where the API is invoked from,
3143EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt
3144controller.
3145
3146The TSP uses this API to finish processing of the secure physical timer
3147interrupt.
3148
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003149Function : plat_ic_get_interrupt_type() [mandatory]
3150~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003151
3152::
3153
3154 Argument : uint32_t
3155 Return : uint32_t
3156
3157This API returns the type of the interrupt id passed as the parameter.
3158``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid
3159interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is
3160returned depending upon how the interrupt has been configured by the platform
3161IC. This API must be invoked at EL3.
3162
Dan Handley610e7e12018-03-01 18:44:00 +00003163Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003164and Non-secure interrupts as Group1 interrupts. It reads the group value
3165corresponding to the interrupt id from the relevant *Interrupt Group Register*
3166(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt.
3167
Dan Handley610e7e12018-03-01 18:44:00 +00003168In the case of Arm standard platforms using GICv3, both the *Interrupt Group
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003169Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register*
3170(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured
3171as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt.
3172
Manish Pandey3161fa52022-11-02 16:30:09 +00003173Common helper functions
3174-----------------------
Govindraj Rajab6709b02023-02-21 17:43:55 +00003175Function : elx_panic()
3176~~~~~~~~~~~~~~~~~~~~~~
Manish Pandey3161fa52022-11-02 16:30:09 +00003177
Govindraj Rajab6709b02023-02-21 17:43:55 +00003178::
3179
3180 Argument : void
3181 Return : void
3182
3183This API is called from assembly files when reporting a critical failure
3184that has occured in lower EL and is been trapped in EL3. This call
3185**must not** return.
Manish Pandey3161fa52022-11-02 16:30:09 +00003186
Govindraj Rajaa796b1b2023-01-16 17:35:07 +00003187Function : el3_panic()
3188~~~~~~~~~~~~~~~~~~~~~~
Manish Pandey3161fa52022-11-02 16:30:09 +00003189
3190::
3191
3192 Argument : void
3193 Return : void
3194
3195This API is called from assembly files when encountering a critical failure that
Govindraj Rajaa796b1b2023-01-16 17:35:07 +00003196cannot be recovered from. This function assumes that it is invoked from a C
3197runtime environment i.e. valid stack exists. This call **must not** return.
Manish Pandey3161fa52022-11-02 16:30:09 +00003198
3199Function : panic()
3200~~~~~~~~~~~~~~~~~~
3201
3202::
3203
3204 Argument : void
3205 Return : void
3206
3207This API called from C files when encountering a critical failure that cannot
3208be recovered from. This function in turn prints backtrace (if enabled) and calls
Govindraj Rajaa796b1b2023-01-16 17:35:07 +00003209el3_panic(). This call **must not** return.
Manish Pandey3161fa52022-11-02 16:30:09 +00003210
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003211Crash Reporting mechanism (in BL31)
3212-----------------------------------
3213
3214BL31 implements a crash reporting mechanism which prints the various registers
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01003215of the CPU to enable quick crash analysis and debugging. This mechanism relies
Paul Beesley1fbc97b2019-01-11 18:26:51 +00003216on the platform implementing ``plat_crash_console_init``,
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01003217``plat_crash_console_putc`` and ``plat_crash_console_flush``.
3218
3219The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample
3220implementation of all of them. Platforms may include this file to their
3221makefiles in order to benefit from them. By default, they will cause the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07003222output to be routed over the normal console infrastructure and get printed on
3223consoles configured to output in crash state. ``console_set_scope()`` can be
3224used to control whether a console is used for crash output.
Paul Beesleyba3ed402019-03-13 16:20:44 +00003225
3226.. note::
3227 Platforms are responsible for making sure that they only mark consoles for
3228 use in the crash scope that are able to support this, i.e. that are written
3229 in assembly and conform with the register clobber rules for putc()
3230 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003231
Julius Werneraae9bb12017-09-18 16:49:48 -07003232In some cases (such as debugging very early crashes that happen before the
3233normal boot console can be set up), platforms may want to control crash output
Julius Werner1338c9c2018-11-19 14:25:55 -08003234more explicitly. These platforms may instead provide custom implementations for
3235these. They are executed outside of a C environment and without a stack. Many
3236console drivers provide functions named ``console_xxx_core_init/putc/flush``
3237that are designed to be used by these functions. See Arm platforms (like juno)
3238for an example of this.
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01003239
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003240Function : plat_crash_console_init [mandatory]
3241~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003242
3243::
3244
3245 Argument : void
3246 Return : int
3247
3248This API is used by the crash reporting mechanism to initialize the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07003249console. It must only use the general purpose registers x0 through x7 to do the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003250initialization and returns 1 on success.
3251
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003252Function : plat_crash_console_putc [mandatory]
3253~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003254
3255::
3256
3257 Argument : int
3258 Return : int
3259
3260This API is used by the crash reporting mechanism to print a character on the
3261designated crash console. It must only use general purpose registers x1 and
3262x2 to do its work. The parameter and the return value are in general purpose
3263register x0.
3264
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003265Function : plat_crash_console_flush [mandatory]
3266~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003267
3268::
3269
3270 Argument : void
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05003271 Return : void
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003272
3273This API is used by the crash reporting mechanism to force write of all buffered
3274data on the designated crash console. It should only use general purpose
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05003275registers x0 through x5 to do its work.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003276
Manish Pandey9c9f38a2020-06-30 00:46:08 +01003277.. _External Abort handling and RAS Support:
3278
Jeenu Viswambharane34bf582018-10-12 08:48:36 +01003279External Abort handling and RAS Support
3280---------------------------------------
Jeenu Viswambharanbf235bc2018-07-12 10:00:01 +01003281
3282Function : plat_ea_handler
3283~~~~~~~~~~~~~~~~~~~~~~~~~~
3284
3285::
3286
3287 Argument : int
3288 Argument : uint64_t
3289 Argument : void *
3290 Argument : void *
3291 Argument : uint64_t
3292 Return : void
3293
Manish Pandeyf90a73c2023-10-10 15:42:19 +01003294This function is invoked by the runtime exception handling framework for the
3295platform to handle an External Abort received at EL3. The intention of the
3296function is to attempt to resolve the cause of External Abort and return;
3297if that's not possible then an orderly shutdown of the system is initiated.
Jeenu Viswambharanbf235bc2018-07-12 10:00:01 +01003298
3299The first parameter (``int ea_reason``) indicates the reason for External Abort.
3300Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``.
3301
3302The second parameter (``uint64_t syndrome``) is the respective syndrome
3303presented to EL3 after having received the External Abort. Depending on the
3304nature of the abort (as can be inferred from the ``ea_reason`` parameter), this
3305can be the content of either ``ESR_EL3`` or ``DISR_EL1``.
3306
3307The third parameter (``void *cookie``) is unused for now. The fourth parameter
3308(``void *handle``) is a pointer to the preempted context. The fifth parameter
3309(``uint64_t flags``) indicates the preempted security state. These parameters
3310are received from the top-level exception handler.
3311
Manish Pandeyf90a73c2023-10-10 15:42:19 +01003312This function must be implemented if a platform expects Firmware First handling
3313of External Aborts.
Jeenu Viswambharanbf235bc2018-07-12 10:00:01 +01003314
3315Function : plat_handle_uncontainable_ea
3316~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3317
3318::
3319
3320 Argument : int
3321 Argument : uint64_t
3322 Return : void
3323
3324This function is invoked by the RAS framework when an External Abort of
3325Uncontainable type is received at EL3. Due to the critical nature of
3326Uncontainable errors, the intention of this function is to initiate orderly
3327shutdown of the system, and is not expected to return.
3328
3329This function must be implemented in assembly.
3330
3331The first and second parameters are the same as that of ``plat_ea_handler``.
3332
3333The default implementation of this function calls
3334``report_unhandled_exception``.
3335
3336Function : plat_handle_double_fault
3337~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3338
3339::
3340
3341 Argument : int
3342 Argument : uint64_t
3343 Return : void
3344
3345This function is invoked by the RAS framework when another External Abort is
3346received at EL3 while one is already being handled. I.e., a call to
3347``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of
3348this function is to initiate orderly shutdown of the system, and is not expected
3349recover or return.
3350
3351This function must be implemented in assembly.
3352
3353The first and second parameters are the same as that of ``plat_ea_handler``.
3354
3355The default implementation of this function calls
3356``report_unhandled_exception``.
3357
3358Function : plat_handle_el3_ea
3359~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3360
3361::
3362
3363 Return : void
3364
3365This function is invoked when an External Abort is received while executing in
3366EL3. Due to its critical nature, the intention of this function is to initiate
3367orderly shutdown of the system, and is not expected recover or return.
3368
3369This function must be implemented in assembly.
3370
3371The default implementation of this function calls
3372``report_unhandled_exception``.
3373
Andre Przywarabdc76f12022-11-21 17:07:25 +00003374Function : plat_handle_rng_trap
3375~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3376
3377::
3378
3379 Argument : uint64_t
3380 Argument : cpu_context_t *
3381 Return : int
3382
3383This function is invoked by BL31's exception handler when there is a synchronous
3384system register trap caused by access to the RNDR or RNDRRS registers. It allows
3385platforms implementing ``FEAT_RNG_TRAP`` and enabling ``ENABLE_FEAT_RNG_TRAP`` to
3386emulate those system registers by returing back some entropy to the lower EL.
3387
3388The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3
3389syndrome register, which encodes the instruction that was trapped. The interesting
3390information in there is the target register (``get_sysreg_iss_rt()``).
3391
3392The second parameter (``cpu_context_t *ctx``) represents the CPU state in the
3393lower exception level, at the time when the execution of the ``mrs`` instruction
3394was trapped. Its content can be changed, to put the entropy into the target
3395register.
3396
3397The return value indicates how to proceed:
3398
3399- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic.
3400- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return
3401 to the same instruction, so its execution will be repeated.
3402- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return
3403 to the next instruction.
3404
3405This function needs to be implemented by a platform if it enables FEAT_RNG_TRAP.
3406
Varun Wadekar0a46eb12023-04-13 21:06:18 +01003407Function : plat_handle_impdef_trap
3408~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3409
3410::
3411
3412 Argument : uint64_t
3413 Argument : cpu_context_t *
3414 Return : int
3415
3416This function is invoked by BL31's exception handler when there is a synchronous
3417system register trap caused by access to the implementation defined registers.
3418It allows platforms enabling ``IMPDEF_SYSREG_TRAP`` to emulate those system
3419registers choosing to program bits of their choice.
3420
3421The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3
3422syndrome register, which encodes the instruction that was trapped.
3423
3424The second parameter (``cpu_context_t *ctx``) represents the CPU state in the
3425lower exception level, at the time when the execution of the ``mrs`` instruction
3426was trapped.
3427
3428The return value indicates how to proceed:
3429
3430- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic.
3431- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return
3432 to the same instruction, so its execution will be repeated.
3433- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return
3434 to the next instruction.
3435
3436This function needs to be implemented by a platform if it enables
3437IMPDEF_SYSREG_TRAP.
3438
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003439Build flags
3440-----------
3441
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003442There are some build flags which can be defined by the platform to control
3443inclusion or exclusion of certain BL stages from the FIP image. These flags
3444need to be defined in the platform makefile which will get included by the
3445build system.
3446
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003447- **NEED_BL33**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003448 By default, this flag is defined ``yes`` by the build system and ``BL33``
3449 build option should be supplied as a build option. The platform has the
3450 option of excluding the BL33 image in the ``fip`` image by defining this flag
3451 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE``
3452 are used, this flag will be set to ``no`` automatically.
3453
Govindraj Raja0386e312023-08-17 10:41:48 -05003454- **ARM_ARCH_MAJOR and ARM_ARCH_MINOR**
3455 By default, ARM_ARCH_MAJOR.ARM_ARCH_MINOR is set to 8.0 in ``defaults.mk``,
3456 if the platform makefile/build defines or uses the correct ARM_ARCH_MAJOR and
3457 ARM_ARCH_MINOR then mandatory Architectural features available for that Arch
3458 version will be enabled by default and any optional Arch feature supported by
3459 the Architecture and available in TF-A can be enabled from platform specific
3460 makefile. Look up to ``arch_features.mk`` for details pertaining to mandatory
3461 and optional Arch specific features.
3462
Paul Beesley07f0a312019-05-16 13:33:18 +01003463Platform include paths
3464----------------------
3465
3466Platforms are allowed to add more include paths to be passed to the compiler.
3467The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in
3468particular for the file ``platform_def.h``.
3469
3470Example:
3471
3472.. code:: c
3473
3474 PLAT_INCLUDES += -Iinclude/plat/myplat/include
3475
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003476C Library
3477---------
3478
3479To avoid subtle toolchain behavioral dependencies, the header files provided
3480by the compiler are not used. The software is built with the ``-nostdinc`` flag
3481to ensure no headers are included from the toolchain inadvertently. Instead the
Dan Handley610e7e12018-03-01 18:44:00 +00003482required headers are included in the TF-A source tree. The library only
3483contains those C library definitions required by the local implementation. If
3484more functionality is required, the needed library functions will need to be
3485added to the local implementation.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003486
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003487Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have
Paul Beesleyf2ec7142019-10-04 16:17:46 +00003488been written specifically for TF-A. Some implementation files have been obtained
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003489from `FreeBSD`_, others have been written specifically for TF-A as well. The
3490files can be found in ``include/lib/libc`` and ``lib/libc``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003491
Sandrine Bailleux6f0ecd72019-02-08 14:46:42 +01003492SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources
3493can be obtained from http://github.com/freebsd/freebsd.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003494
3495Storage abstraction layer
3496-------------------------
3497
Louis Mayencourtb5469002019-07-15 13:56:03 +01003498In order to improve platform independence and portability a storage abstraction
3499layer is used to load data from non-volatile platform storage. Currently
3500storage access is only required by BL1 and BL2 phases and performed inside the
3501``load_image()`` function in ``bl_common.c``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003502
Sandrine Bailleuxf17ddaa2023-02-08 14:07:29 +01003503.. uml:: resources/diagrams/plantuml/io_framework_usage_overview.puml
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003504
Dan Handley610e7e12018-03-01 18:44:00 +00003505It is mandatory to implement at least one storage driver. For the Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003506development platforms the Firmware Image Package (FIP) driver is provided as
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01003507the default means to load data from storage (see :ref:`firmware_design_fip`).
3508The storage layer is described in the header file
3509``include/drivers/io/io_storage.h``. The implementation of the common library is
3510in ``drivers/io/io_storage.c`` and the driver files are located in
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003511``drivers/io/``.
3512
Sandrine Bailleuxf17ddaa2023-02-08 14:07:29 +01003513.. uml:: resources/diagrams/plantuml/io_arm_class_diagram.puml
Louis Mayencourtb5469002019-07-15 13:56:03 +01003514
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003515Each IO driver must provide ``io_dev_*`` structures, as described in
3516``drivers/io/io_driver.h``. These are returned via a mandatory registration
3517function that is called on platform initialization. The semi-hosting driver
3518implementation in ``io_semihosting.c`` can be used as an example.
3519
Louis Mayencourtb5469002019-07-15 13:56:03 +01003520Each platform should register devices and their drivers via the storage
3521abstraction layer. These drivers then need to be initialized by bootloader
3522phases as required in their respective ``blx_platform_setup()`` functions.
3523
Sandrine Bailleuxf17ddaa2023-02-08 14:07:29 +01003524.. uml:: resources/diagrams/plantuml/io_dev_registration.puml
Louis Mayencourtb5469002019-07-15 13:56:03 +01003525
3526The storage abstraction layer provides mechanisms (``io_dev_init()``) to
3527initialize storage devices before IO operations are called.
3528
Sandrine Bailleuxf17ddaa2023-02-08 14:07:29 +01003529.. uml:: resources/diagrams/plantuml/io_dev_init_and_check.puml
Louis Mayencourtb5469002019-07-15 13:56:03 +01003530
3531The basic operations supported by the layer
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003532include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``.
3533Drivers do not have to implement all operations, but each platform must
3534provide at least one driver for a device capable of supporting generic
3535operations such as loading a bootloader image.
3536
3537The current implementation only allows for known images to be loaded by the
3538firmware. These images are specified by using their identifiers, as defined in
Antonio Nino Diaz645feb42019-02-13 14:07:38 +00003539``include/plat/common/common_def.h`` (or a separate header file included from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003540there). The platform layer (``plat_get_image_source()``) then returns a reference
3541to a device and a driver-specific ``spec`` which will be understood by the driver
3542to allow access to the image data.
3543
3544The layer is designed in such a way that is it possible to chain drivers with
3545other drivers. For example, file-system drivers may be implemented on top of
3546physical block devices, both represented by IO devices with corresponding
3547drivers. In such a case, the file-system "binding" with the block device may
3548be deferred until the file-system device is initialised.
3549
3550The abstraction currently depends on structures being statically allocated
3551by the drivers and callers, as the system does not yet provide a means of
3552dynamically allocating memory. This may also have the affect of limiting the
3553amount of open resources per driver.
3554
Manish V Badarkhe93a61be2023-06-15 10:34:05 +01003555Measured Boot Platform Interface
3556--------------------------------
3557
3558Enabling the MEASURED_BOOT flag adds extra platform requirements. Please refer
3559to :ref:`Measured Boot Design` for more details.
3560
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003561--------------
3562
Chris Kay33bfc5e2023-02-14 11:30:04 +00003563*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003564
Manish V Badarkhe9d24e9b2023-06-15 09:14:33 +01003565.. _PSCI: https://developer.arm.com/documentation/den0022/latest/
Dan Handley610e7e12018-03-01 18:44:00 +00003566.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003567.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html
Paul Beesley2437ddc2019-02-08 16:43:05 +00003568.. _FreeBSD: https://www.freebsd.org
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003569.. _SCC: http://www.simple-cc.org/
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +01003570.. _DRTM: https://developer.arm.com/documentation/den0113/a