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Paul Beesleyfc9ee362019-03-07 15:47:15 +00001Porting Guide
2=============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Douglas Raillardd7c21b72017-06-28 15:23:03 +01004Introduction
5------------
6
Dan Handley610e7e12018-03-01 18:44:00 +00007Porting Trusted Firmware-A (TF-A) to a new platform involves making some
Douglas Raillardd7c21b72017-06-28 15:23:03 +01008mandatory and optional modifications for both the cold and warm boot paths.
9Modifications consist of:
10
11- Implementing a platform-specific function or variable,
12- Setting up the execution context in a certain way, or
13- Defining certain constants (for example #defines).
14
15The platform-specific functions and variables are declared in
Paul Beesleyf8640672019-04-12 14:19:42 +010016``include/plat/common/platform.h``. The firmware provides a default
17implementation of variables and functions to fulfill the optional requirements.
18These implementations are all weakly defined; they are provided to ease the
19porting effort. Each platform port can override them with its own implementation
20if the default implementation is inadequate.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
Douglas Raillardd7c21b72017-06-28 15:23:03 +010022Some modifications are common to all Boot Loader (BL) stages. Section 2
23discusses these in detail. The subsequent sections discuss the remaining
24modifications for each BL stage in detail.
25
Paul Beesleyf8640672019-04-12 14:19:42 +010026Please refer to the :ref:`Platform Compatibility Policy` for the policy
27regarding compatibility and deprecation of these porting interfaces.
Soby Mathew02bdbb92018-09-26 11:17:23 +010028
Antonio Nino Diaz645feb42019-02-13 14:07:38 +000029Only Arm development platforms (such as FVP and Juno) may use the
30functions/definitions in ``include/plat/arm/common/`` and the corresponding
31source files in ``plat/arm/common/``. This is done so that there are no
32dependencies between platforms maintained by different people/companies. If you
33want to use any of the functionality present in ``plat/arm`` files, please
34create a pull request that moves the code to ``plat/common`` so that it can be
35discussed.
36
Douglas Raillardd7c21b72017-06-28 15:23:03 +010037Common modifications
38--------------------
39
40This section covers the modifications that should be made by the platform for
41each BL stage to correctly port the firmware stack. They are categorized as
42either mandatory or optional.
43
44Common mandatory modifications
45------------------------------
46
47A platform port must enable the Memory Management Unit (MMU) as well as the
48instruction and data caches for each BL stage. Setting up the translation
49tables is the responsibility of the platform port because memory maps differ
50across platforms. A memory translation library (see ``lib/xlat_tables/``) is
Sandrine Bailleux1861b7a2017-07-20 16:11:01 +010051provided to help in this setup.
52
53Note that although this library supports non-identity mappings, this is intended
54only for re-mapping peripheral physical addresses and allows platforms with high
55I/O addresses to reduce their virtual address space. All other addresses
56corresponding to code and data must currently use an identity mapping.
57
Dan Handley610e7e12018-03-01 18:44:00 +000058Also, the only translation granule size supported in TF-A is 4KB, as various
59parts of the code assume that is the case. It is not possible to switch to
6016 KB or 64 KB granule sizes at the moment.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010061
Dan Handley610e7e12018-03-01 18:44:00 +000062In Arm standard platforms, each BL stage configures the MMU in the
Douglas Raillardd7c21b72017-06-28 15:23:03 +010063platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses
64an identity mapping for all addresses.
65
66If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a
67block of identity mapped secure memory with Device-nGnRE attributes aligned to
68page boundary (4K) for each BL stage. All sections which allocate coherent
69memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a
70section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its
71possible for the firmware to place variables in it using the following C code
72directive:
73
74::
75
76 __section("bakery_lock")
77
78Or alternatively the following assembler code directive:
79
80::
81
82 .section bakery_lock
83
84The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are
85used to allocate any data structures that are accessed both when a CPU is
86executing with its MMU and caches enabled, and when it's running with its MMU
87and caches disabled. Examples are given below.
88
89The following variables, functions and constants must be defined by the platform
90for the firmware to work correctly.
91
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +010092File : platform_def.h [mandatory]
93~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +010094
95Each platform must ensure that a header file of this name is in the system
Antonio Nino Diaz50a4d1a2019-02-01 12:22:22 +000096include path with the following constants defined. This will require updating
97the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010098
Paul Beesleyf8640672019-04-12 14:19:42 +010099Platform ports may optionally use the file ``include/plat/common/common_def.h``,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100100which provides typical values for some of the constants below. These values are
101likely to be suitable for all platform ports.
102
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100103- **#define : PLATFORM_LINKER_FORMAT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100104
105 Defines the linker format used by the platform, for example
106 ``elf64-littleaarch64``.
107
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100108- **#define : PLATFORM_LINKER_ARCH**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100109
110 Defines the processor architecture for the linker by the platform, for
111 example ``aarch64``.
112
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100113- **#define : PLATFORM_STACK_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100114
115 Defines the normal stack memory available to each CPU. This constant is used
Paul Beesleyf8640672019-04-12 14:19:42 +0100116 by ``plat/common/aarch64/platform_mp_stack.S`` and
117 ``plat/common/aarch64/platform_up_stack.S``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100118
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100119- **define : CACHE_WRITEBACK_GRANULE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100120
121 Defines the size in bits of the largest cache line across all the cache
122 levels in the platform.
123
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100124- **#define : FIRMWARE_WELCOME_STR**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100125
126 Defines the character string printed by BL1 upon entry into the ``bl1_main()``
127 function.
128
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100129- **#define : PLATFORM_CORE_COUNT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100130
131 Defines the total number of CPUs implemented by the platform across all
132 clusters in the system.
133
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100134- **#define : PLAT_NUM_PWR_DOMAINS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100135
136 Defines the total number of nodes in the power domain topology
137 tree at all the power domain levels used by the platform.
138 This macro is used by the PSCI implementation to allocate
139 data structures to represent power domain topology.
140
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100141- **#define : PLAT_MAX_PWR_LVL**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100142
143 Defines the maximum power domain level that the power management operations
144 should apply to. More often, but not always, the power domain level
145 corresponds to affinity level. This macro allows the PSCI implementation
146 to know the highest power domain level that it should consider for power
147 management operations in the system that the platform implements. For
148 example, the Base AEM FVP implements two clusters with a configurable
149 number of CPUs and it reports the maximum power domain level as 1.
150
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100151- **#define : PLAT_MAX_OFF_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100152
153 Defines the local power state corresponding to the deepest power down
154 possible at every power domain level in the platform. The local power
155 states for each level may be sparsely allocated between 0 and this value
156 with 0 being reserved for the RUN state. The PSCI implementation uses this
157 value to initialize the local power states of the power domain nodes and
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100158 to specify the requested power state for a PSCI_CPU_OFF call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100159
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100160- **#define : PLAT_MAX_RET_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100161
162 Defines the local power state corresponding to the deepest retention state
163 possible at every power domain level in the platform. This macro should be
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100164 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100165 PSCI implementation to distinguish between retention and power down local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100166 power states within PSCI_CPU_SUSPEND call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100167
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100168- **#define : PLAT_MAX_PWR_LVL_STATES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100169
170 Defines the maximum number of local power states per power domain level
171 that the platform supports. The default value of this macro is 2 since
172 most platforms just support a maximum of two local power states at each
173 power domain level (power-down and retention). If the platform needs to
174 account for more local power states, then it must redefine this macro.
175
176 Currently, this macro is used by the Generic PSCI implementation to size
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100177 the array used for PSCI_STAT_COUNT/RESIDENCY accounting.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100178
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100179- **#define : BL1_RO_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100180
181 Defines the base address in secure ROM where BL1 originally lives. Must be
182 aligned on a page-size boundary.
183
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100184- **#define : BL1_RO_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100185
186 Defines the maximum address in secure ROM that BL1's actual content (i.e.
187 excluding any data section allocated at runtime) can occupy.
188
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100189- **#define : BL1_RW_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100190
191 Defines the base address in secure RAM where BL1's read-write data will live
192 at runtime. Must be aligned on a page-size boundary.
193
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100194- **#define : BL1_RW_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100195
196 Defines the maximum address in secure RAM that BL1's read-write data can
197 occupy at runtime.
198
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100199- **#define : BL2_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100200
201 Defines the base address in secure RAM where BL1 loads the BL2 binary image.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000202 Must be aligned on a page-size boundary. This constant is not applicable
203 when BL2_IN_XIP_MEM is set to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100204
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100205- **#define : BL2_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100206
207 Defines the maximum address in secure RAM that the BL2 image can occupy.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000208 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'.
209
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100210- **#define : BL2_RO_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000211
212 Defines the base address in secure XIP memory where BL2 RO section originally
213 lives. Must be aligned on a page-size boundary. This constant is only needed
214 when BL2_IN_XIP_MEM is set to '1'.
215
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100216- **#define : BL2_RO_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000217
218 Defines the maximum address in secure XIP memory that BL2's actual content
219 (i.e. excluding any data section allocated at runtime) can occupy. This
220 constant is only needed when BL2_IN_XIP_MEM is set to '1'.
221
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100222- **#define : BL2_RW_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000223
224 Defines the base address in secure RAM where BL2's read-write data will live
225 at runtime. Must be aligned on a page-size boundary. This constant is only
226 needed when BL2_IN_XIP_MEM is set to '1'.
227
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100228- **#define : BL2_RW_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000229
230 Defines the maximum address in secure RAM that BL2's read-write data can
231 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set
232 to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100233
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100234- **#define : BL31_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100235
236 Defines the base address in secure RAM where BL2 loads the BL31 binary
237 image. Must be aligned on a page-size boundary.
238
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100239- **#define : BL31_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100240
241 Defines the maximum address in secure RAM that the BL31 image can occupy.
242
243For every image, the platform must define individual identifiers that will be
244used by BL1 or BL2 to load the corresponding image into memory from non-volatile
245storage. For the sake of performance, integer numbers will be used as
246identifiers. The platform will use those identifiers to return the relevant
247information about the image to be loaded (file handler, load address,
248authentication information, etc.). The following image identifiers are
249mandatory:
250
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100251- **#define : BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100252
253 BL2 image identifier, used by BL1 to load BL2.
254
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100255- **#define : BL31_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100256
257 BL31 image identifier, used by BL2 to load BL31.
258
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100259- **#define : BL33_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100260
261 BL33 image identifier, used by BL2 to load BL33.
262
263If Trusted Board Boot is enabled, the following certificate identifiers must
264also be defined:
265
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100266- **#define : TRUSTED_BOOT_FW_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100267
268 BL2 content certificate identifier, used by BL1 to load the BL2 content
269 certificate.
270
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100271- **#define : TRUSTED_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100272
273 Trusted key certificate identifier, used by BL2 to load the trusted key
274 certificate.
275
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100276- **#define : SOC_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100277
278 BL31 key certificate identifier, used by BL2 to load the BL31 key
279 certificate.
280
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100281- **#define : SOC_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100282
283 BL31 content certificate identifier, used by BL2 to load the BL31 content
284 certificate.
285
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100286- **#define : NON_TRUSTED_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100287
288 BL33 key certificate identifier, used by BL2 to load the BL33 key
289 certificate.
290
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100291- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100292
293 BL33 content certificate identifier, used by BL2 to load the BL33 content
294 certificate.
295
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100296- **#define : FWU_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100297
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100298 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100299 FWU content certificate.
300
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100301- **#define : PLAT_CRYPTOCELL_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100302
Dan Handley610e7e12018-03-01 18:44:00 +0000303 This defines the base address of Arm® TrustZone® CryptoCell and must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100304 defined if CryptoCell crypto driver is used for Trusted Board Boot. For
Dan Handley610e7e12018-03-01 18:44:00 +0000305 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100306 set.
307
308If the AP Firmware Updater Configuration image, BL2U is used, the following
309must also be defined:
310
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100311- **#define : BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100312
313 Defines the base address in secure memory where BL1 copies the BL2U binary
314 image. Must be aligned on a page-size boundary.
315
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100316- **#define : BL2U_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100317
318 Defines the maximum address in secure memory that the BL2U image can occupy.
319
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100320- **#define : BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100321
322 BL2U image identifier, used by BL1 to fetch an image descriptor
323 corresponding to BL2U.
324
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100325If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100326must also be defined:
327
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100328- **#define : SCP_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100329
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100330 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor
331 corresponding to SCP_BL2U.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000332
333 .. note::
334 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100335
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100336If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100337also be defined:
338
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100339- **#define : NS_BL1U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100340
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100341 Defines the base address in non-secure ROM where NS_BL1U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100342 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000343
344 .. note::
345 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100346
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100347- **#define : NS_BL1U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100348
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100349 NS_BL1U image identifier, used by BL1 to fetch an image descriptor
350 corresponding to NS_BL1U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100351
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100352If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100353be defined:
354
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100355- **#define : NS_BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100356
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100357 Defines the base address in non-secure memory where NS_BL2U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100358 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000359
360 .. note::
361 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100362
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100363- **#define : NS_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100364
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100365 NS_BL2U image identifier, used by BL1 to fetch an image descriptor
366 corresponding to NS_BL2U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100367
368For the the Firmware update capability of TRUSTED BOARD BOOT, the following
369macros may also be defined:
370
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100371- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100372
373 Total number of images that can be loaded simultaneously. If the platform
374 doesn't specify any value, it defaults to 10.
375
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100376If a SCP_BL2 image is supported by the platform, the following constants must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100377also be defined:
378
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100379- **#define : SCP_BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100380
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100381 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000382 from platform storage before being transferred to the SCP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100383
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100384- **#define : SCP_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100385
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100386 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100387 certificate (mandatory when Trusted Board Boot is enabled).
388
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100389- **#define : SCP_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100390
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100391 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100392 content certificate (mandatory when Trusted Board Boot is enabled).
393
394If a BL32 image is supported by the platform, the following constants must
395also be defined:
396
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100397- **#define : BL32_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100398
399 BL32 image identifier, used by BL2 to load BL32.
400
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100401- **#define : TRUSTED_OS_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100402
403 BL32 key certificate identifier, used by BL2 to load the BL32 key
404 certificate (mandatory when Trusted Board Boot is enabled).
405
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100406- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100407
408 BL32 content certificate identifier, used by BL2 to load the BL32 content
409 certificate (mandatory when Trusted Board Boot is enabled).
410
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100411- **#define : BL32_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100412
413 Defines the base address in secure memory where BL2 loads the BL32 binary
414 image. Must be aligned on a page-size boundary.
415
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100416- **#define : BL32_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100417
418 Defines the maximum address that the BL32 image can occupy.
419
420If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the
421platform, the following constants must also be defined:
422
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100423- **#define : TSP_SEC_MEM_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100424
425 Defines the base address of the secure memory used by the TSP image on the
426 platform. This must be at the same address or below ``BL32_BASE``.
427
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100428- **#define : TSP_SEC_MEM_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100429
430 Defines the size of the secure memory used by the BL32 image on the
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000431 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully
432 accommodate the memory required by the BL32 image, defined by ``BL32_BASE``
433 and ``BL32_LIMIT``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100434
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100435- **#define : TSP_IRQ_SEC_PHY_TIMER**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100436
437 Defines the ID of the secure physical generic timer interrupt used by the
438 TSP's interrupt handling code.
439
440If the platform port uses the translation table library code, the following
441constants must also be defined:
442
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100443- **#define : PLAT_XLAT_TABLES_DYNAMIC**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100444
445 Optional flag that can be set per-image to enable the dynamic allocation of
446 regions even when the MMU is enabled. If not defined, only static
447 functionality will be available, if defined and set to 1 it will also
448 include the dynamic functionality.
449
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100450- **#define : MAX_XLAT_TABLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100451
452 Defines the maximum number of translation tables that are allocated by the
453 translation table library code. To minimize the amount of runtime memory
454 used, choose the smallest value needed to map the required virtual addresses
455 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL
456 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions
457 as well.
458
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100459- **#define : MAX_MMAP_REGIONS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100460
461 Defines the maximum number of regions that are allocated by the translation
462 table library code. A region consists of physical base address, virtual base
463 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
464 defined in the ``mmap_region_t`` structure. The platform defines the regions
465 that should be mapped. Then, the translation table library will create the
466 corresponding tables and descriptors at runtime. To minimize the amount of
467 runtime memory used, choose the smallest value needed to register the
468 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is
469 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate
470 the dynamic regions as well.
471
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100472- **#define : PLAT_VIRT_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100473
474 Defines the total size of the virtual address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000475 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100476
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100477- **#define : PLAT_PHY_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100478
479 Defines the total size of the physical address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000480 for a 32 bit physical address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100481
482If the platform port uses the IO storage framework, the following constants
483must also be defined:
484
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100485- **#define : MAX_IO_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100486
487 Defines the maximum number of registered IO devices. Attempting to register
488 more devices than this value using ``io_register_device()`` will fail with
489 -ENOMEM.
490
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100491- **#define : MAX_IO_HANDLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100492
493 Defines the maximum number of open IO handles. Attempting to open more IO
494 entities than this value using ``io_open()`` will fail with -ENOMEM.
495
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100496- **#define : MAX_IO_BLOCK_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100497
498 Defines the maximum number of registered IO block devices. Attempting to
499 register more devices this value using ``io_dev_open()`` will fail
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100500 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100501 With this macro, multiple block devices could be supported at the same
502 time.
503
504If the platform needs to allocate data within the per-cpu data framework in
505BL31, it should define the following macro. Currently this is only required if
506the platform decides not to use the coherent memory section by undefining the
507``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
508required memory within the the per-cpu data to minimize wastage.
509
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100510- **#define : PLAT_PCPU_DATA_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100511
512 Defines the memory (in bytes) to be reserved within the per-cpu data
513 structure for use by the platform layer.
514
515The following constants are optional. They should be defined when the platform
Dan Handley610e7e12018-03-01 18:44:00 +0000516memory layout implies some image overlaying like in Arm standard platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100517
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100518- **#define : BL31_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100519
520 Defines the maximum address in secure RAM that the BL31's progbits sections
521 can occupy.
522
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100523- **#define : TSP_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100524
525 Defines the maximum address that the TSP's progbits sections can occupy.
526
527If the platform port uses the PL061 GPIO driver, the following constant may
528optionally be defined:
529
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100530- **PLAT_PL061_MAX_GPIOS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100531 Maximum number of GPIOs required by the platform. This allows control how
532 much memory is allocated for PL061 GPIO controllers. The default value is
533
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100534 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100535
536If the platform port uses the partition driver, the following constant may
537optionally be defined:
538
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100539- **PLAT_PARTITION_MAX_ENTRIES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100540 Maximum number of partition entries required by the platform. This allows
541 control how much memory is allocated for partition entries. The default
542 value is 128.
Paul Beesleyf8640672019-04-12 14:19:42 +0100543 For example, define the build flag in ``platform.mk``:
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100544 PLAT_PARTITION_MAX_ENTRIES := 12
545 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100546
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800547- **PLAT_PARTITION_BLOCK_SIZE**
548 The size of partition block. It could be either 512 bytes or 4096 bytes.
549 The default value is 512.
Paul Beesleyf2ec7142019-10-04 16:17:46 +0000550 For example, define the build flag in ``platform.mk``:
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800551 PLAT_PARTITION_BLOCK_SIZE := 4096
552 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE))
553
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100554The following constant is optional. It should be defined to override the default
555behaviour of the ``assert()`` function (for example, to save memory).
556
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100557- **PLAT_LOG_LEVEL_ASSERT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100558 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``,
559 ``assert()`` prints the name of the file, the line number and the asserted
560 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file
561 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it
562 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't
563 defined, it defaults to ``LOG_LEVEL``.
564
Dimitris Papastamos60346db2017-12-13 10:54:37 +0000565If the platform port uses the Activity Monitor Unit, the following constants
566may be defined:
567
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100568- **PLAT_AMU_GROUP1_COUNTERS_MASK**
Dimitris Papastamos60346db2017-12-13 10:54:37 +0000569 This mask reflects the set of group counters that should be enabled. The
570 maximum number of group 1 counters supported by AMUv1 is 16 so the mask
571 can be at most 0xffff. If the platform does not define this mask, no group 1
572 counters are enabled. If the platform defines this mask, the following
573 constant needs to also be defined.
574
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100575- **PLAT_AMU_GROUP1_NR_COUNTERS**
Dimitris Papastamos60346db2017-12-13 10:54:37 +0000576 This value is used to allocate an array to save and restore the counters
577 specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend.
578 This value should be equal to the highest bit position set in the
579 mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16.
580
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100581File : plat_macros.S [mandatory]
582~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100583
584Each platform must ensure a file of this name is in the system include path with
Dan Handley610e7e12018-03-01 18:44:00 +0000585the following macro defined. In the Arm development platforms, this file is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100586found in ``plat/arm/board/<plat_name>/include/plat_macros.S``.
587
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100588- **Macro : plat_crash_print_regs**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100589
590 This macro allows the crash reporting routine to print relevant platform
591 registers in case of an unhandled exception in BL31. This aids in debugging
592 and this macro can be defined to be empty in case register reporting is not
593 desired.
594
595 For instance, GIC or interconnect registers may be helpful for
596 troubleshooting.
597
598Handling Reset
599--------------
600
601BL1 by default implements the reset vector where execution starts from a cold
602or warm boot. BL31 can be optionally set as a reset vector using the
603``RESET_TO_BL31`` make variable.
604
605For each CPU, the reset vector code is responsible for the following tasks:
606
607#. Distinguishing between a cold boot and a warm boot.
608
609#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
610 the CPU is placed in a platform-specific state until the primary CPU
611 performs the necessary steps to remove it from this state.
612
613#. In the case of a warm boot, ensuring that the CPU jumps to a platform-
614 specific address in the BL31 image in the same processor mode as it was
615 when released from reset.
616
617The following functions need to be implemented by the platform port to enable
618reset vector code to perform the above tasks.
619
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100620Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0]
621~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100622
623::
624
625 Argument : void
626 Return : uintptr_t
627
628This function is called with the MMU and caches disabled
629(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for
630distinguishing between a warm and cold reset for the current CPU using
631platform-specific means. If it's a warm reset, then it returns the warm
632reset entrypoint point provided to ``plat_setup_psci_ops()`` during
633BL31 initialization. If it's a cold reset then this function must return zero.
634
635This function does not follow the Procedure Call Standard used by the
Dan Handley610e7e12018-03-01 18:44:00 +0000636Application Binary Interface for the Arm 64-bit architecture. The caller should
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100637not assume that callee saved registers are preserved across a call to this
638function.
639
640This function fulfills requirement 1 and 3 listed above.
641
642Note that for platforms that support programming the reset address, it is
643expected that a CPU will start executing code directly at the right address,
644both on a cold and warm reset. In this case, there is no need to identify the
645type of reset nor to query the warm reset entrypoint. Therefore, implementing
646this function is not required on such platforms.
647
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100648Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
649~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100650
651::
652
653 Argument : void
654
655This function is called with the MMU and data caches disabled. It is responsible
656for placing the executing secondary CPU in a platform-specific state until the
657primary CPU performs the necessary actions to bring it out of that state and
658allow entry into the OS. This function must not return.
659
Dan Handley610e7e12018-03-01 18:44:00 +0000660In the Arm FVP port, when using the normal boot flow, each secondary CPU powers
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100661itself off. The primary CPU is responsible for powering up the secondary CPUs
662when normal world software requires them. When booting an EL3 payload instead,
663they stay powered on and are put in a holding pen until their mailbox gets
664populated.
665
666This function fulfills requirement 2 above.
667
668Note that for platforms that can't release secondary CPUs out of reset, only the
669primary CPU will execute the cold boot code. Therefore, implementing this
670function is not required on such platforms.
671
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100672Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
673~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100674
675::
676
677 Argument : void
678 Return : unsigned int
679
680This function identifies whether the current CPU is the primary CPU or a
681secondary CPU. A return value of zero indicates that the CPU is not the
682primary CPU, while a non-zero return value indicates that the CPU is the
683primary CPU.
684
685Note that for platforms that can't release secondary CPUs out of reset, only the
686primary CPU will execute the cold boot code. Therefore, there is no need to
687distinguish between primary and secondary CPUs and implementing this function is
688not required.
689
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100690Function : platform_mem_init() [mandatory]
691~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100692
693::
694
695 Argument : void
696 Return : void
697
698This function is called before any access to data is made by the firmware, in
699order to carry out any essential memory initialization.
700
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100701Function: plat_get_rotpk_info()
702~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100703
704::
705
706 Argument : void *, void **, unsigned int *, unsigned int *
707 Return : int
708
709This function is mandatory when Trusted Board Boot is enabled. It returns a
710pointer to the ROTPK stored in the platform (or a hash of it) and its length.
711The ROTPK must be encoded in DER format according to the following ASN.1
712structure:
713
714::
715
716 AlgorithmIdentifier ::= SEQUENCE {
717 algorithm OBJECT IDENTIFIER,
718 parameters ANY DEFINED BY algorithm OPTIONAL
719 }
720
721 SubjectPublicKeyInfo ::= SEQUENCE {
722 algorithm AlgorithmIdentifier,
723 subjectPublicKey BIT STRING
724 }
725
726In case the function returns a hash of the key:
727
728::
729
730 DigestInfo ::= SEQUENCE {
731 digestAlgorithm AlgorithmIdentifier,
732 digest OCTET STRING
733 }
734
735The function returns 0 on success. Any other value is treated as error by the
736Trusted Board Boot. The function also reports extra information related
737to the ROTPK in the flags parameter:
738
739::
740
741 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a
742 hash.
743 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK
744 verification while the platform ROTPK is not deployed.
745 When this flag is set, the function does not need to
746 return a platform ROTPK, and the authentication
747 framework uses the ROTPK in the certificate without
748 verifying it against the platform value. This flag
749 must not be used in a deployed production environment.
750
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100751Function: plat_get_nv_ctr()
752~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100753
754::
755
756 Argument : void *, unsigned int *
757 Return : int
758
759This function is mandatory when Trusted Board Boot is enabled. It returns the
760non-volatile counter value stored in the platform in the second argument. The
761cookie in the first argument may be used to select the counter in case the
762platform provides more than one (for example, on platforms that use the default
763TBBR CoT, the cookie will correspond to the OID values defined in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100764TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100765
766The function returns 0 on success. Any other value means the counter value could
767not be retrieved from the platform.
768
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100769Function: plat_set_nv_ctr()
770~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100771
772::
773
774 Argument : void *, unsigned int
775 Return : int
776
777This function is mandatory when Trusted Board Boot is enabled. It sets a new
778counter value in the platform. The cookie in the first argument may be used to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100779select the counter (as explained in plat_get_nv_ctr()). The second argument is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100780the updated counter value to be written to the NV counter.
781
782The function returns 0 on success. Any other value means the counter value could
783not be updated.
784
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100785Function: plat_set_nv_ctr2()
786~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100787
788::
789
790 Argument : void *, const auth_img_desc_t *, unsigned int
791 Return : int
792
793This function is optional when Trusted Board Boot is enabled. If this
794interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The
795first argument passed is a cookie and is typically used to
796differentiate between a Non Trusted NV Counter and a Trusted NV
797Counter. The second argument is a pointer to an authentication image
798descriptor and may be used to decide if the counter is allowed to be
799updated or not. The third argument is the updated counter value to
800be written to the NV counter.
801
802The function returns 0 on success. Any other value means the counter value
803either could not be updated or the authentication image descriptor indicates
804that it is not allowed to be updated.
805
806Common mandatory function modifications
807---------------------------------------
808
809The following functions are mandatory functions which need to be implemented
810by the platform port.
811
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100812Function : plat_my_core_pos()
813~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100814
815::
816
817 Argument : void
818 Return : unsigned int
819
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000820This function returns the index of the calling CPU which is used as a
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100821CPU-specific linear index into blocks of memory (for example while allocating
822per-CPU stacks). This function will be invoked very early in the
823initialization sequence which mandates that this function should be
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000824implemented in assembly and should not rely on the availability of a C
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100825runtime environment. This function can clobber x0 - x8 and must preserve
826x9 - x29.
827
828This function plays a crucial role in the power domain topology framework in
Paul Beesleyf8640672019-04-12 14:19:42 +0100829PSCI and details of this can be found in
830:ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100831
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100832Function : plat_core_pos_by_mpidr()
833~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100834
835::
836
837 Argument : u_register_t
838 Return : int
839
840This function validates the ``MPIDR`` of a CPU and converts it to an index,
841which can be used as a CPU-specific linear index into blocks of memory. In
842case the ``MPIDR`` is invalid, this function returns -1. This function will only
843be invoked by BL31 after the power domain topology is initialized and can
Dan Handley610e7e12018-03-01 18:44:00 +0000844utilize the C runtime environment. For further details about how TF-A
845represents the power domain topology and how this relates to the linear CPU
Paul Beesleyf8640672019-04-12 14:19:42 +0100846index, please refer :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100847
Ambroise Vincentd207f562019-04-10 12:50:27 +0100848Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1]
849~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
850
851::
852
853 Arguments : void **heap_addr, size_t *heap_size
854 Return : int
855
856This function is invoked during Mbed TLS library initialisation to get a heap,
857by means of a starting address and a size. This heap will then be used
858internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS
859must be able to provide a heap to it.
860
861A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in
862which a heap is statically reserved during compile time inside every image
863(i.e. every BL stage) that utilises Mbed TLS. In this default implementation,
864the function simply returns the address and size of this "pre-allocated" heap.
865For a platform to use this default implementation, only a call to the helper
866from inside plat_get_mbedtls_heap() body is enough and nothing else is needed.
867
868However, by writting their own implementation, platforms have the potential to
869optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is
870shared between BL1 and BL2 stages and, thus, the necessary space is not reserved
871twice.
872
873On success the function should return 0 and a negative error code otherwise.
874
Sumit Gargc0c369c2019-11-15 18:47:53 +0530875Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1]
876~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
877
878::
879
880 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key,
881 size_t *key_len, unsigned int *flags, const uint8_t *img_id,
882 size_t img_id_len
883 Return : int
884
885This function provides a symmetric key (either SSK or BSSK depending on
886fw_enc_status) which is invoked during runtime decryption of encrypted
887firmware images. `plat/common/plat_bl_common.c` provides a dummy weak
888implementation for testing purposes which must be overridden by the platform
889trying to implement a real world firmware encryption use-case.
890
891It also allows the platform to pass symmetric key identifier rather than
892actual symmetric key which is useful in cases where the crypto backend provides
893secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER``
894flag must be set in ``flags``.
895
896In addition to above a platform may also choose to provide an image specific
897symmetric key/identifier using img_id.
898
899On success the function should return 0 and a negative error code otherwise.
900
901Note that this API depends on ``DECRYPTION_SUPPORT`` build flag which is
902marked as experimental.
903
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100904Common optional modifications
905-----------------------------
906
907The following are helper functions implemented by the firmware that perform
908common platform-specific tasks. A platform may choose to override these
909definitions.
910
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100911Function : plat_set_my_stack()
912~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100913
914::
915
916 Argument : void
917 Return : void
918
919This function sets the current stack pointer to the normal memory stack that
920has been allocated for the current CPU. For BL images that only require a
921stack for the primary CPU, the UP version of the function is used. The size
922of the stack allocated to each CPU is specified by the platform defined
923constant ``PLATFORM_STACK_SIZE``.
924
925Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +0100926provided in ``plat/common/aarch64/platform_up_stack.S`` and
927``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100928
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100929Function : plat_get_my_stack()
930~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100931
932::
933
934 Argument : void
935 Return : uintptr_t
936
937This function returns the base address of the normal memory stack that
938has been allocated for the current CPU. For BL images that only require a
939stack for the primary CPU, the UP version of the function is used. The size
940of the stack allocated to each CPU is specified by the platform defined
941constant ``PLATFORM_STACK_SIZE``.
942
943Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +0100944provided in ``plat/common/aarch64/platform_up_stack.S`` and
945``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100946
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100947Function : plat_report_exception()
948~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100949
950::
951
952 Argument : unsigned int
953 Return : void
954
955A platform may need to report various information about its status when an
956exception is taken, for example the current exception level, the CPU security
957state (secure/non-secure), the exception type, and so on. This function is
958called in the following circumstances:
959
960- In BL1, whenever an exception is taken.
961- In BL2, whenever an exception is taken.
962
963The default implementation doesn't do anything, to avoid making assumptions
964about the way the platform displays its status information.
965
966For AArch64, this function receives the exception type as its argument.
967Possible values for exceptions types are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +0100968``include/common/bl_common.h`` header file. Note that these constants are not
Dan Handley610e7e12018-03-01 18:44:00 +0000969related to any architectural exception code; they are just a TF-A convention.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100970
971For AArch32, this function receives the exception mode as its argument.
972Possible values for exception modes are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +0100973``include/lib/aarch32/arch.h`` header file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100974
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100975Function : plat_reset_handler()
976~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100977
978::
979
980 Argument : void
981 Return : void
982
983A platform may need to do additional initialization after reset. This function
Paul Beesleyf2ec7142019-10-04 16:17:46 +0000984allows the platform to do the platform specific initializations. Platform
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000985specific errata workarounds could also be implemented here. The API should
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100986preserve the values of callee saved registers x19 to x29.
987
988The default implementation doesn't do anything. If a platform needs to override
Paul Beesleyf8640672019-04-12 14:19:42 +0100989the default implementation, refer to the :ref:`Firmware Design` for general
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100990guidelines.
991
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100992Function : plat_disable_acp()
993~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100994
995::
996
997 Argument : void
998 Return : void
999
John Tsichritzis6dda9762018-07-23 09:18:04 +01001000This API allows a platform to disable the Accelerator Coherency Port (if
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001001present) during a cluster power down sequence. The default weak implementation
John Tsichritzis6dda9762018-07-23 09:18:04 +01001002doesn't do anything. Since this API is called during the power down sequence,
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001003it has restrictions for stack usage and it can use the registers x0 - x17 as
1004scratch registers. It should preserve the value in x18 register as it is used
1005by the caller to store the return address.
1006
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001007Function : plat_error_handler()
1008~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001009
1010::
1011
1012 Argument : int
1013 Return : void
1014
1015This API is called when the generic code encounters an error situation from
1016which it cannot continue. It allows the platform to perform error reporting or
1017recovery actions (for example, reset the system). This function must not return.
1018
1019The parameter indicates the type of error using standard codes from ``errno.h``.
1020Possible errors reported by the generic code are:
1021
1022- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted
1023 Board Boot is enabled)
1024- ``-ENOENT``: the requested image or certificate could not be found or an IO
1025 error was detected
Dan Handley610e7e12018-03-01 18:44:00 +00001026- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this
1027 error is usually an indication of an incorrect array size
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001028
1029The default implementation simply spins.
1030
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001031Function : plat_panic_handler()
1032~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001033
1034::
1035
1036 Argument : void
1037 Return : void
1038
1039This API is called when the generic code encounters an unexpected error
1040situation from which it cannot recover. This function must not return,
1041and must be implemented in assembly because it may be called before the C
1042environment is initialized.
1043
Paul Beesleyba3ed402019-03-13 16:20:44 +00001044.. note::
1045 The address from where it was called is stored in x30 (Link Register).
1046 The default implementation simply spins.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001047
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001048Function : plat_get_bl_image_load_info()
1049~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001050
1051::
1052
1053 Argument : void
1054 Return : bl_load_info_t *
1055
1056This function returns pointer to the list of images that the platform has
Soby Mathew97b1bff2018-09-27 16:46:41 +01001057populated to load. This function is invoked in BL2 to load the
1058BL3xx images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001059
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001060Function : plat_get_next_bl_params()
1061~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001062
1063::
1064
1065 Argument : void
1066 Return : bl_params_t *
1067
1068This function returns a pointer to the shared memory that the platform has
Dan Handley610e7e12018-03-01 18:44:00 +00001069kept aside to pass TF-A related information that next BL image needs. This
Soby Mathew97b1bff2018-09-27 16:46:41 +01001070function is invoked in BL2 to pass this information to the next BL
1071image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001072
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001073Function : plat_get_stack_protector_canary()
1074~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001075
1076::
1077
1078 Argument : void
1079 Return : u_register_t
1080
1081This function returns a random value that is used to initialize the canary used
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001082when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001083value will weaken the protection as the attacker could easily write the right
1084value as part of the attack most of the time. Therefore, it should return a
1085true random number.
1086
Paul Beesleyba3ed402019-03-13 16:20:44 +00001087.. warning::
1088 For the protection to be effective, the global data need to be placed at
1089 a lower address than the stack bases. Failure to do so would allow an
1090 attacker to overwrite the canary as part of the stack buffer overflow attack.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001091
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001092Function : plat_flush_next_bl_params()
1093~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001094
1095::
1096
1097 Argument : void
1098 Return : void
1099
1100This function flushes to main memory all the image params that are passed to
Soby Mathew97b1bff2018-09-27 16:46:41 +01001101next image. This function is invoked in BL2 to flush this information
1102to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001103
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001104Function : plat_log_get_prefix()
1105~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewaaf15f52017-09-04 11:49:29 +01001106
1107::
1108
1109 Argument : unsigned int
1110 Return : const char *
1111
1112This function defines the prefix string corresponding to the `log_level` to be
Dan Handley610e7e12018-03-01 18:44:00 +00001113prepended to all the log output from TF-A. The `log_level` (argument) will
1114correspond to one of the standard log levels defined in debug.h. The platform
1115can override the common implementation to define a different prefix string for
John Tsichritzis30f89642018-06-07 16:31:34 +01001116the log output. The implementation should be robust to future changes that
Dan Handley610e7e12018-03-01 18:44:00 +00001117increase the number of log levels.
Soby Mathewaaf15f52017-09-04 11:49:29 +01001118
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001119Function : plat_get_soc_version()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001120~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001121
1122::
1123
1124 Argument : void
1125 Return : int32_t
1126
1127This function returns soc version which mainly consist of below fields
1128
1129::
1130
1131 soc_version[30:24] = JEP-106 continuation code for the SiP
1132 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001133 soc_version[15:0] = Implementation defined SoC ID
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001134
1135Function : plat_get_soc_revision()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001136~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001137
1138::
1139
1140 Argument : void
1141 Return : int32_t
1142
1143This function returns soc revision in below format
1144
1145::
1146
1147 soc_revision[0:30] = SOC revision of specific SOC
1148
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001149Function : plat_is_smccc_feature_available()
1150~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1151
1152::
1153
1154 Argument : u_register_t
1155 Return : int32_t
1156
1157This function returns SMC_ARCH_CALL_SUCCESS if the platform supports
1158the SMCCC function specified in the argument; otherwise returns
1159SMC_ARCH_CALL_NOT_SUPPORTED.
1160
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001161Modifications specific to a Boot Loader stage
1162---------------------------------------------
1163
1164Boot Loader Stage 1 (BL1)
1165-------------------------
1166
1167BL1 implements the reset vector where execution starts from after a cold or
1168warm boot. For each CPU, BL1 is responsible for the following tasks:
1169
1170#. Handling the reset as described in section 2.2
1171
1172#. In the case of a cold boot and the CPU being the primary CPU, ensuring that
1173 only this CPU executes the remaining BL1 code, including loading and passing
1174 control to the BL2 stage.
1175
1176#. Identifying and starting the Firmware Update process (if required).
1177
1178#. Loading the BL2 image from non-volatile storage into secure memory at the
1179 address specified by the platform defined constant ``BL2_BASE``.
1180
1181#. Populating a ``meminfo`` structure with the following information in memory,
1182 accessible by BL2 immediately upon entry.
1183
1184 ::
1185
1186 meminfo.total_base = Base address of secure RAM visible to BL2
1187 meminfo.total_size = Size of secure RAM visible to BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001188
Soby Mathew97b1bff2018-09-27 16:46:41 +01001189 By default, BL1 places this ``meminfo`` structure at the end of secure
1190 memory visible to BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001191
Soby Mathewb1bf0442018-02-16 14:52:52 +00001192 It is possible for the platform to decide where it wants to place the
1193 ``meminfo`` structure for BL2 or restrict the amount of memory visible to
1194 BL2 by overriding the weak default implementation of
1195 ``bl1_plat_handle_post_image_load`` API.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001196
1197The following functions need to be implemented by the platform port to enable
1198BL1 to perform the above tasks.
1199
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001200Function : bl1_early_platform_setup() [mandatory]
1201~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001202
1203::
1204
1205 Argument : void
1206 Return : void
1207
1208This function executes with the MMU and data caches disabled. It is only called
1209by the primary CPU.
1210
Dan Handley610e7e12018-03-01 18:44:00 +00001211On Arm standard platforms, this function:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001212
1213- Enables a secure instance of SP805 to act as the Trusted Watchdog.
1214
1215- Initializes a UART (PL011 console), which enables access to the ``printf``
1216 family of functions in BL1.
1217
1218- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to
1219 the CCI slave interface corresponding to the cluster that includes the
1220 primary CPU.
1221
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001222Function : bl1_plat_arch_setup() [mandatory]
1223~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001224
1225::
1226
1227 Argument : void
1228 Return : void
1229
1230This function performs any platform-specific and architectural setup that the
1231platform requires. Platform-specific setup might include configuration of
1232memory controllers and the interconnect.
1233
Dan Handley610e7e12018-03-01 18:44:00 +00001234In Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001235
1236This function helps fulfill requirement 2 above.
1237
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001238Function : bl1_platform_setup() [mandatory]
1239~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001240
1241::
1242
1243 Argument : void
1244 Return : void
1245
1246This function executes with the MMU and data caches enabled. It is responsible
1247for performing any remaining platform-specific setup that can occur after the
1248MMU and data cache have been enabled.
1249
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001250if support for multiple boot sources is required, it initializes the boot
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001251sequence used by plat_try_next_boot_source().
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001252
Dan Handley610e7e12018-03-01 18:44:00 +00001253In Arm standard platforms, this function initializes the storage abstraction
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001254layer used to load the next bootloader image.
1255
1256This function helps fulfill requirement 4 above.
1257
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001258Function : bl1_plat_sec_mem_layout() [mandatory]
1259~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001260
1261::
1262
1263 Argument : void
1264 Return : meminfo *
1265
1266This function should only be called on the cold boot path. It executes with the
1267MMU and data caches enabled. The pointer returned by this function must point to
1268a ``meminfo`` structure containing the extents and availability of secure RAM for
1269the BL1 stage.
1270
1271::
1272
1273 meminfo.total_base = Base address of secure RAM visible to BL1
1274 meminfo.total_size = Size of secure RAM visible to BL1
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001275
1276This information is used by BL1 to load the BL2 image in secure RAM. BL1 also
1277populates a similar structure to tell BL2 the extents of memory available for
1278its own use.
1279
1280This function helps fulfill requirements 4 and 5 above.
1281
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001282Function : bl1_plat_prepare_exit() [optional]
1283~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001284
1285::
1286
1287 Argument : entry_point_info_t *
1288 Return : void
1289
1290This function is called prior to exiting BL1 in response to the
1291``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform
1292platform specific clean up or bookkeeping operations before transferring
1293control to the next image. It receives the address of the ``entry_point_info_t``
1294structure passed from BL2. This function runs with MMU disabled.
1295
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001296Function : bl1_plat_set_ep_info() [optional]
1297~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001298
1299::
1300
1301 Argument : unsigned int image_id, entry_point_info_t *ep_info
1302 Return : void
1303
1304This function allows platforms to override ``ep_info`` for the given ``image_id``.
1305
1306The default implementation just returns.
1307
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001308Function : bl1_plat_get_next_image_id() [optional]
1309~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001310
1311::
1312
1313 Argument : void
1314 Return : unsigned int
1315
1316This and the following function must be overridden to enable the FWU feature.
1317
1318BL1 calls this function after platform setup to identify the next image to be
1319loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds
1320with the normal boot sequence, which loads and executes BL2. If the platform
1321returns a different image id, BL1 assumes that Firmware Update is required.
1322
Dan Handley610e7e12018-03-01 18:44:00 +00001323The default implementation always returns ``BL2_IMAGE_ID``. The Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001324platforms override this function to detect if firmware update is required, and
1325if so, return the first image in the firmware update process.
1326
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001327Function : bl1_plat_get_image_desc() [optional]
1328~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001329
1330::
1331
1332 Argument : unsigned int image_id
1333 Return : image_desc_t *
1334
1335BL1 calls this function to get the image descriptor information ``image_desc_t``
1336for the provided ``image_id`` from the platform.
1337
Dan Handley610e7e12018-03-01 18:44:00 +00001338The default implementation always returns a common BL2 image descriptor. Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001339standard platforms return an image descriptor corresponding to BL2 or one of
1340the firmware update images defined in the Trusted Board Boot Requirements
1341specification.
1342
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001343Function : bl1_plat_handle_pre_image_load() [optional]
1344~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001345
1346::
1347
Soby Mathew2f38ce32018-02-08 17:45:12 +00001348 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001349 Return : int
1350
1351This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001352corresponding to ``image_id``. This function is invoked in BL1, both in cold
1353boot and FWU code path, before loading the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001354
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001355Function : bl1_plat_handle_post_image_load() [optional]
1356~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001357
1358::
1359
Soby Mathew2f38ce32018-02-08 17:45:12 +00001360 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001361 Return : int
1362
1363This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001364corresponding to ``image_id``. This function is invoked in BL1, both in cold
1365boot and FWU code path, after loading and authenticating the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001366
Soby Mathewb1bf0442018-02-16 14:52:52 +00001367The default weak implementation of this function calculates the amount of
1368Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t``
1369structure at the beginning of this free memory and populates it. The address
1370of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint
1371information to BL2.
1372
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001373Function : bl1_plat_fwu_done() [optional]
1374~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001375
1376::
1377
1378 Argument : unsigned int image_id, uintptr_t image_src,
1379 unsigned int image_size
1380 Return : void
1381
1382BL1 calls this function when the FWU process is complete. It must not return.
1383The platform may override this function to take platform specific action, for
1384example to initiate the normal boot flow.
1385
1386The default implementation spins forever.
1387
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001388Function : bl1_plat_mem_check() [mandatory]
1389~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001390
1391::
1392
1393 Argument : uintptr_t mem_base, unsigned int mem_size,
1394 unsigned int flags
1395 Return : int
1396
1397BL1 calls this function while handling FWU related SMCs, more specifically when
1398copying or authenticating an image. Its responsibility is to ensure that the
1399region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and
1400that this memory corresponds to either a secure or non-secure memory region as
1401indicated by the security state of the ``flags`` argument.
1402
1403This function can safely assume that the value resulting from the addition of
1404``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not
1405overflow.
1406
1407This function must return 0 on success, a non-null error code otherwise.
1408
1409The default implementation of this function asserts therefore platforms must
1410override it when using the FWU feature.
1411
1412Boot Loader Stage 2 (BL2)
1413-------------------------
1414
1415The BL2 stage is executed only by the primary CPU, which is determined in BL1
1416using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at
Soby Mathew97b1bff2018-09-27 16:46:41 +01001417``BL2_BASE``. BL2 executes in Secure EL1 and and invokes
1418``plat_get_bl_image_load_info()`` to retrieve the list of images to load from
1419non-volatile storage to secure/non-secure RAM. After all the images are loaded
1420then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable
1421images to be passed to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001422
1423The following functions must be implemented by the platform port to enable BL2
1424to perform the above tasks.
1425
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001426Function : bl2_early_platform_setup2() [mandatory]
1427~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001428
1429::
1430
Soby Mathew97b1bff2018-09-27 16:46:41 +01001431 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001432 Return : void
1433
1434This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001435by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments
1436are platform specific.
1437
1438On Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001439
Manish V Badarkhe81414512020-06-24 15:58:38 +01001440 arg0 - Points to load address of FW_CONFIG
Soby Mathew97b1bff2018-09-27 16:46:41 +01001441
1442 arg1 - ``meminfo`` structure populated by BL1. The platform copies
1443 the contents of ``meminfo`` as it may be subsequently overwritten by BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001444
Dan Handley610e7e12018-03-01 18:44:00 +00001445On Arm standard platforms, this function also:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001446
1447- Initializes a UART (PL011 console), which enables access to the ``printf``
1448 family of functions in BL2.
1449
1450- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001451 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1452 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001453
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001454Function : bl2_plat_arch_setup() [mandatory]
1455~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001456
1457::
1458
1459 Argument : void
1460 Return : void
1461
1462This function executes with the MMU and data caches disabled. It is only called
1463by the primary CPU.
1464
1465The purpose of this function is to perform any architectural initialization
1466that varies across platforms.
1467
Dan Handley610e7e12018-03-01 18:44:00 +00001468On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001469
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001470Function : bl2_platform_setup() [mandatory]
1471~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001472
1473::
1474
1475 Argument : void
1476 Return : void
1477
1478This function may execute with the MMU and data caches enabled if the platform
1479port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only
1480called by the primary CPU.
1481
1482The purpose of this function is to perform any platform initialization
1483specific to BL2.
1484
Dan Handley610e7e12018-03-01 18:44:00 +00001485In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001486configuration of the TrustZone controller to allow non-secure masters access
1487to most of DRAM. Part of DRAM is reserved for secure world use.
1488
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001489Function : bl2_plat_handle_pre_image_load() [optional]
1490~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001491
1492::
1493
1494 Argument : unsigned int
1495 Return : int
1496
1497This function can be used by the platforms to update/use image information
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001498for given ``image_id``. This function is currently invoked in BL2 before
Soby Mathew97b1bff2018-09-27 16:46:41 +01001499loading each image.
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001500
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001501Function : bl2_plat_handle_post_image_load() [optional]
1502~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001503
1504::
1505
1506 Argument : unsigned int
1507 Return : int
1508
1509This function can be used by the platforms to update/use image information
1510for given ``image_id``. This function is currently invoked in BL2 after
Soby Mathew97b1bff2018-09-27 16:46:41 +01001511loading each image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001512
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001513Function : bl2_plat_preload_setup [optional]
1514~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001515
1516::
John Tsichritzisee10e792018-06-06 09:38:10 +01001517
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001518 Argument : void
1519 Return : void
1520
1521This optional function performs any BL2 platform initialization
1522required before image loading, that is not done later in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001523bl2_platform_setup(). Specifically, if support for multiple
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001524boot sources is required, it initializes the boot sequence used by
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001525plat_try_next_boot_source().
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001526
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001527Function : plat_try_next_boot_source() [optional]
1528~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001529
1530::
John Tsichritzisee10e792018-06-06 09:38:10 +01001531
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001532 Argument : void
1533 Return : int
1534
1535This optional function passes to the next boot source in the redundancy
1536sequence.
1537
1538This function moves the current boot redundancy source to the next
1539element in the boot sequence. If there are no more boot sources then it
1540must return 0, otherwise it must return 1. The default implementation
1541of this always returns 0.
1542
Roberto Vargasb1584272017-11-20 13:36:10 +00001543Boot Loader Stage 2 (BL2) at EL3
1544--------------------------------
1545
Dan Handley610e7e12018-03-01 18:44:00 +00001546When the platform has a non-TF-A Boot ROM it is desirable to jump
1547directly to BL2 instead of TF-A BL1. In this case BL2 is expected to
Paul Beesleyf8640672019-04-12 14:19:42 +01001548execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design`
1549document for more information.
Roberto Vargasb1584272017-11-20 13:36:10 +00001550
1551All mandatory functions of BL2 must be implemented, except the functions
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001552bl2_early_platform_setup and bl2_el3_plat_arch_setup, because
1553their work is done now by bl2_el3_early_platform_setup and
1554bl2_el3_plat_arch_setup. These functions should generally implement
1555the bl1_plat_xxx() and bl2_plat_xxx() functionality combined.
Roberto Vargasb1584272017-11-20 13:36:10 +00001556
1557
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001558Function : bl2_el3_early_platform_setup() [mandatory]
1559~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001560
1561::
John Tsichritzisee10e792018-06-06 09:38:10 +01001562
Roberto Vargasb1584272017-11-20 13:36:10 +00001563 Argument : u_register_t, u_register_t, u_register_t, u_register_t
1564 Return : void
1565
1566This function executes with the MMU and data caches disabled. It is only called
1567by the primary CPU. This function receives four parameters which can be used
1568by the platform to pass any needed information from the Boot ROM to BL2.
1569
Dan Handley610e7e12018-03-01 18:44:00 +00001570On Arm standard platforms, this function does the following:
Roberto Vargasb1584272017-11-20 13:36:10 +00001571
1572- Initializes a UART (PL011 console), which enables access to the ``printf``
1573 family of functions in BL2.
1574
1575- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001576 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1577 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Roberto Vargasb1584272017-11-20 13:36:10 +00001578
1579- Initializes the private variables that define the memory layout used.
1580
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001581Function : bl2_el3_plat_arch_setup() [mandatory]
1582~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001583
1584::
John Tsichritzisee10e792018-06-06 09:38:10 +01001585
Roberto Vargasb1584272017-11-20 13:36:10 +00001586 Argument : void
1587 Return : void
1588
1589This function executes with the MMU and data caches disabled. It is only called
1590by the primary CPU.
1591
1592The purpose of this function is to perform any architectural initialization
1593that varies across platforms.
1594
Dan Handley610e7e12018-03-01 18:44:00 +00001595On Arm standard platforms, this function enables the MMU.
Roberto Vargasb1584272017-11-20 13:36:10 +00001596
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001597Function : bl2_el3_plat_prepare_exit() [optional]
1598~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001599
1600::
John Tsichritzisee10e792018-06-06 09:38:10 +01001601
Roberto Vargasb1584272017-11-20 13:36:10 +00001602 Argument : void
1603 Return : void
1604
1605This function is called prior to exiting BL2 and run the next image.
1606It should be used to perform platform specific clean up or bookkeeping
1607operations before transferring control to the next image. This function
1608runs with MMU disabled.
1609
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001610FWU Boot Loader Stage 2 (BL2U)
1611------------------------------
1612
1613The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU
1614process and is executed only by the primary CPU. BL1 passes control to BL2U at
1615``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for:
1616
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001617#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure
1618 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1.
1619 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U
1620 should be copied from. Subsequent handling of the SCP_BL2U image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001621 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function.
1622 If ``SCP_BL2U_BASE`` is not defined then this step is not performed.
1623
1624#. Any platform specific setup required to perform the FWU process. For
Dan Handley610e7e12018-03-01 18:44:00 +00001625 example, Arm standard platforms initialize the TZC controller so that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001626 normal world can access DDR memory.
1627
1628The following functions must be implemented by the platform port to enable
1629BL2U to perform the tasks mentioned above.
1630
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001631Function : bl2u_early_platform_setup() [mandatory]
1632~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001633
1634::
1635
1636 Argument : meminfo *mem_info, void *plat_info
1637 Return : void
1638
1639This function executes with the MMU and data caches disabled. It is only
1640called by the primary CPU. The arguments to this function is the address
1641of the ``meminfo`` structure and platform specific info provided by BL1.
1642
1643The platform may copy the contents of the ``mem_info`` and ``plat_info`` into
1644private storage as the original memory may be subsequently overwritten by BL2U.
1645
Dan Handley610e7e12018-03-01 18:44:00 +00001646On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001647to extract SCP_BL2U image information, which is then copied into a private
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001648variable.
1649
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001650Function : bl2u_plat_arch_setup() [mandatory]
1651~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001652
1653::
1654
1655 Argument : void
1656 Return : void
1657
1658This function executes with the MMU and data caches disabled. It is only
1659called by the primary CPU.
1660
1661The purpose of this function is to perform any architectural initialization
1662that varies across platforms, for example enabling the MMU (since the memory
1663map differs across platforms).
1664
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001665Function : bl2u_platform_setup() [mandatory]
1666~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001667
1668::
1669
1670 Argument : void
1671 Return : void
1672
1673This function may execute with the MMU and data caches enabled if the platform
1674port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only
1675called by the primary CPU.
1676
1677The purpose of this function is to perform any platform initialization
1678specific to BL2U.
1679
Dan Handley610e7e12018-03-01 18:44:00 +00001680In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001681configuration of the TrustZone controller to allow non-secure masters access
1682to most of DRAM. Part of DRAM is reserved for secure world use.
1683
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001684Function : bl2u_plat_handle_scp_bl2u() [optional]
1685~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001686
1687::
1688
1689 Argument : void
1690 Return : int
1691
1692This function is used to perform any platform-specific actions required to
1693handle the SCP firmware. Typically it transfers the image into SCP memory using
1694a platform-specific protocol and waits until SCP executes it and signals to the
1695Application Processor (AP) for BL2U execution to continue.
1696
1697This function returns 0 on success, a negative error code otherwise.
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001698This function is included if SCP_BL2U_BASE is defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001699
1700Boot Loader Stage 3-1 (BL31)
1701----------------------------
1702
1703During cold boot, the BL31 stage is executed only by the primary CPU. This is
1704determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes
1705control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all
1706CPUs. BL31 executes at EL3 and is responsible for:
1707
1708#. Re-initializing all architectural and platform state. Although BL1 performs
1709 some of this initialization, BL31 remains resident in EL3 and must ensure
1710 that EL3 architectural and platform state is completely initialized. It
1711 should make no assumptions about the system state when it receives control.
1712
1713#. Passing control to a normal world BL image, pre-loaded at a platform-
Soby Mathew97b1bff2018-09-27 16:46:41 +01001714 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list
1715 populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001716
1717#. Providing runtime firmware services. Currently, BL31 only implements a
1718 subset of the Power State Coordination Interface (PSCI) API as a runtime
1719 service. See Section 3.3 below for details of porting the PSCI
1720 implementation.
1721
1722#. Optionally passing control to the BL32 image, pre-loaded at a platform-
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001723 specific address by BL2. BL31 exports a set of APIs that allow runtime
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001724 services to specify the security state in which the next image should be
Soby Mathew97b1bff2018-09-27 16:46:41 +01001725 executed and run the corresponding image. On ARM platforms, BL31 uses the
1726 ``bl_params`` list populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001727
1728If BL31 is a reset vector, It also needs to handle the reset as specified in
1729section 2.2 before the tasks described above.
1730
1731The following functions must be implemented by the platform port to enable BL31
1732to perform the above tasks.
1733
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001734Function : bl31_early_platform_setup2() [mandatory]
1735~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001736
1737::
1738
Soby Mathew97b1bff2018-09-27 16:46:41 +01001739 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001740 Return : void
1741
1742This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001743by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are
1744platform specific.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001745
Soby Mathew97b1bff2018-09-27 16:46:41 +01001746In Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001747
Soby Mathew97b1bff2018-09-27 16:46:41 +01001748 arg0 - The pointer to the head of `bl_params_t` list
1749 which is list of executable images following BL31,
1750
1751 arg1 - Points to load address of SOC_FW_CONFIG if present
Manish V Badarkhe81414512020-06-24 15:58:38 +01001752 except in case of Arm FVP platform.
1753
1754 In case of Arm FVP platform, Points to load address
1755 of FW_CONFIG.
Soby Mathew97b1bff2018-09-27 16:46:41 +01001756
1757 arg2 - Points to load address of HW_CONFIG if present
1758
1759 arg3 - A special value to verify platform parameters from BL2 to BL31. Not
1760 used in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001761
Soby Mathew97b1bff2018-09-27 16:46:41 +01001762The function runs through the `bl_param_t` list and extracts the entry point
1763information for BL32 and BL33. It also performs the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001764
1765- Initialize a UART (PL011 console), which enables access to the ``printf``
1766 family of functions in BL31.
1767
1768- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the
1769 CCI slave interface corresponding to the cluster that includes the primary
1770 CPU.
1771
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001772Function : bl31_plat_arch_setup() [mandatory]
1773~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001774
1775::
1776
1777 Argument : void
1778 Return : void
1779
1780This function executes with the MMU and data caches disabled. It is only called
1781by the primary CPU.
1782
1783The purpose of this function is to perform any architectural initialization
1784that varies across platforms.
1785
Dan Handley610e7e12018-03-01 18:44:00 +00001786On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001787
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001788Function : bl31_platform_setup() [mandatory]
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001789~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1790
1791::
1792
1793 Argument : void
1794 Return : void
1795
1796This function may execute with the MMU and data caches enabled if the platform
1797port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only
1798called by the primary CPU.
1799
1800The purpose of this function is to complete platform initialization so that both
1801BL31 runtime services and normal world software can function correctly.
1802
Dan Handley610e7e12018-03-01 18:44:00 +00001803On Arm standard platforms, this function does the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001804
1805- Initialize the generic interrupt controller.
1806
1807 Depending on the GIC driver selected by the platform, the appropriate GICv2
1808 or GICv3 initialization will be done, which mainly consists of:
1809
1810 - Enable secure interrupts in the GIC CPU interface.
1811 - Disable the legacy interrupt bypass mechanism.
1812 - Configure the priority mask register to allow interrupts of all priorities
1813 to be signaled to the CPU interface.
1814 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure.
1815 - Target all secure SPIs to CPU0.
1816 - Enable these secure interrupts in the GIC distributor.
1817 - Configure all other interrupts as non-secure.
1818 - Enable signaling of secure interrupts in the GIC distributor.
1819
1820- Enable system-level implementation of the generic timer counter through the
1821 memory mapped interface.
1822
1823- Grant access to the system counter timer module
1824
1825- Initialize the power controller device.
1826
1827 In particular, initialise the locks that prevent concurrent accesses to the
1828 power controller device.
1829
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001830Function : bl31_plat_runtime_setup() [optional]
1831~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001832
1833::
1834
1835 Argument : void
1836 Return : void
1837
1838The purpose of this function is allow the platform to perform any BL31 runtime
1839setup just prior to BL31 exit during cold boot. The default weak
Julius Werneraae9bb12017-09-18 16:49:48 -07001840implementation of this function will invoke ``console_switch_state()`` to switch
1841console output to consoles marked for use in the ``runtime`` state.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001842
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001843Function : bl31_plat_get_next_image_ep_info() [mandatory]
1844~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001845
1846::
1847
Sandrine Bailleux842117d2018-05-14 14:25:47 +02001848 Argument : uint32_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001849 Return : entry_point_info *
1850
1851This function may execute with the MMU and data caches enabled if the platform
1852port does the necessary initializations in ``bl31_plat_arch_setup()``.
1853
1854This function is called by ``bl31_main()`` to retrieve information provided by
1855BL2 for the next image in the security state specified by the argument. BL31
1856uses this information to pass control to that image in the specified security
1857state. This function must return a pointer to the ``entry_point_info`` structure
1858(that was copied during ``bl31_early_platform_setup()``) if the image exists. It
1859should return NULL otherwise.
1860
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01001861Function : bl31_plat_enable_mmu [optional]
1862~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1863
1864::
1865
1866 Argument : uint32_t
1867 Return : void
1868
1869This function enables the MMU. The boot code calls this function with MMU and
1870caches disabled. This function should program necessary registers to enable
1871translation, and upon return, the MMU on the calling PE must be enabled.
1872
1873The function must honor flags passed in the first argument. These flags are
1874defined by the translation library, and can be found in the file
1875``include/lib/xlat_tables/xlat_mmu_helpers.h``.
1876
1877On DynamIQ systems, this function must not use stack while enabling MMU, which
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001878is how the function in xlat table library version 2 is implemented.
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01001879
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001880Function : plat_init_apkey [optional]
1881~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00001882
1883::
1884
1885 Argument : void
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001886 Return : uint128_t
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00001887
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001888This function returns the 128-bit value which can be used to program ARMv8.3
1889pointer authentication keys.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00001890
1891The value should be obtained from a reliable source of randomness.
1892
1893This function is only needed if ARMv8.3 pointer authentication is used in the
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001894Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00001895
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001896Function : plat_get_syscnt_freq2() [mandatory]
1897~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001898
1899::
1900
1901 Argument : void
1902 Return : unsigned int
1903
1904This function is used by the architecture setup code to retrieve the counter
1905frequency for the CPU's generic timer. This value will be programmed into the
Dan Handley610e7e12018-03-01 18:44:00 +00001906``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001907of the system counter, which is retrieved from the first entry in the frequency
1908modes table.
1909
johpow013e24c162020-04-22 14:05:13 -05001910Function : plat_arm_set_twedel_scr_el3() [optional]
1911~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1912
1913::
1914
1915 Argument : void
1916 Return : uint32_t
1917
1918This function is used in v8.6+ systems to set the WFE trap delay value in
1919SCR_EL3. If this function returns TWED_DISABLED or is left unimplemented, this
1920feature is not enabled. The only hook provided is to set the TWED fields in
1921SCR_EL3, there are similar fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to adjust
1922the WFE trap delays in lower ELs and these fields should be set by the
1923appropriate EL2 or EL1 code depending on the platform configuration.
1924
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001925#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]
1926~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001927
1928When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in
1929bytes) aligned to the cache line boundary that should be allocated per-cpu to
1930accommodate all the bakery locks.
1931
1932If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker
1933calculates the size of the ``bakery_lock`` input section, aligns it to the
1934nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT``
1935and stores the result in a linker symbol. This constant prevents a platform
1936from relying on the linker and provide a more efficient mechanism for
1937accessing per-cpu bakery lock information.
1938
1939If this constant is defined and its value is not equal to the value
1940calculated by the linker then a link time assertion is raised. A compile time
1941assertion is raised if the value of the constant is not aligned to the cache
1942line boundary.
1943
Paul Beesleyf8640672019-04-12 14:19:42 +01001944.. _porting_guide_sdei_requirements:
1945
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001946SDEI porting requirements
1947~~~~~~~~~~~~~~~~~~~~~~~~~
1948
Paul Beesley606d8072019-03-13 13:58:02 +00001949The |SDEI| dispatcher requires the platform to provide the following macros
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001950and functions, of which some are optional, and some others mandatory.
1951
1952Macros
1953......
1954
1955Macro: PLAT_SDEI_NORMAL_PRI [mandatory]
1956^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1957
1958This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00001959Normal |SDEI| events on the platform. This must have a higher value
1960(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001961
1962Macro: PLAT_SDEI_CRITICAL_PRI [mandatory]
1963^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1964
1965This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00001966Critical |SDEI| events on the platform. This must have a lower value
1967(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001968
Paul Beesley606d8072019-03-13 13:58:02 +00001969**Note**: |SDEI| exception priorities must be the lowest among Secure
1970priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must
1971be higher than Normal |SDEI| priority.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001972
1973Functions
1974.........
1975
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02001976Function: int plat_sdei_validate_entry_point() [optional]
1977^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001978
1979::
1980
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02001981 Argument: uintptr_t ep, unsigned int client_mode
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001982 Return: int
1983
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02001984This function validates the entry point address of the event handler provided by
1985the client for both event registration and *Complete and Resume* |SDEI| calls.
1986The function ensures that the address is valid in the client translation regime.
1987
1988The second argument is the exception level that the client is executing in. It
1989can be Non-Secure EL1 or Non-Secure EL2.
1990
1991The function must return ``0`` for successful validation, or ``-1`` upon failure.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001992
Dan Handley610e7e12018-03-01 18:44:00 +00001993The default implementation always returns ``0``. On Arm platforms, this function
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02001994translates the entry point address within the client translation regime and
1995further ensures that the resulting physical address is located in Non-secure
1996DRAM.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001997
1998Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional]
1999^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2000
2001::
2002
2003 Argument: uint64_t
2004 Argument: unsigned int
2005 Return: void
2006
Paul Beesley606d8072019-03-13 13:58:02 +00002007|SDEI| specification requires that a PE comes out of reset with the events
2008masked. The client therefore is expected to call ``PE_UNMASK`` to unmask
2009|SDEI| events on the PE. No |SDEI| events can be dispatched until such
2010time.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002011
Paul Beesley606d8072019-03-13 13:58:02 +00002012Should a PE receive an interrupt that was bound to an |SDEI| event while the
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002013events are masked on the PE, the dispatcher implementation invokes the function
2014``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the
2015interrupt and the interrupt ID are passed as parameters.
2016
2017The default implementation only prints out a warning message.
2018
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002019Power State Coordination Interface (in BL31)
2020--------------------------------------------
2021
Dan Handley610e7e12018-03-01 18:44:00 +00002022The TF-A implementation of the PSCI API is based around the concept of a
2023*power domain*. A *power domain* is a CPU or a logical group of CPUs which
2024share some state on which power management operations can be performed as
2025specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is
2026a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The
2027*power domains* are arranged in a hierarchical tree structure and each
2028*power domain* can be identified in a system by the cpu index of any CPU that
2029is part of that domain and a *power domain level*. A processing element (for
2030example, a CPU) is at level 0. If the *power domain* node above a CPU is a
2031logical grouping of CPUs that share some state, then level 1 is that group of
2032CPUs (for example, a cluster), and level 2 is a group of clusters (for
2033example, the system). More details on the power domain topology and its
Paul Beesleyf8640672019-04-12 14:19:42 +01002034organization can be found in :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002035
2036BL31's platform initialization code exports a pointer to the platform-specific
2037power management operations required for the PSCI implementation to function
2038correctly. This information is populated in the ``plat_psci_ops`` structure. The
2039PSCI implementation calls members of the ``plat_psci_ops`` structure for performing
2040power management operations on the power domains. For example, the target
2041CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()``
2042handler (if present) is called for the CPU power domain.
2043
2044The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to
2045describe composite power states specific to a platform. The PSCI implementation
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00002046defines a generic representation of the power-state parameter, which is an
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002047array of local power states where each index corresponds to a power domain
2048level. Each entry contains the local power state the power domain at that power
2049level could enter. It depends on the ``validate_power_state()`` handler to
2050convert the power-state parameter (possibly encoding a composite power state)
2051passed in a PSCI ``CPU_SUSPEND`` call to this representation.
2052
2053The following functions form part of platform port of PSCI functionality.
2054
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002055Function : plat_psci_stat_accounting_start() [optional]
2056~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002057
2058::
2059
2060 Argument : const psci_power_state_t *
2061 Return : void
2062
2063This is an optional hook that platforms can implement for residency statistics
2064accounting before entering a low power state. The ``pwr_domain_state`` field of
2065``state_info`` (first argument) can be inspected if stat accounting is done
2066differently at CPU level versus higher levels. As an example, if the element at
2067index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2068state, special hardware logic may be programmed in order to keep track of the
2069residency statistics. For higher levels (array indices > 0), the residency
2070statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2071default implementation will use PMF to capture timestamps.
2072
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002073Function : plat_psci_stat_accounting_stop() [optional]
2074~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002075
2076::
2077
2078 Argument : const psci_power_state_t *
2079 Return : void
2080
2081This is an optional hook that platforms can implement for residency statistics
2082accounting after exiting from a low power state. The ``pwr_domain_state`` field
2083of ``state_info`` (first argument) can be inspected if stat accounting is done
2084differently at CPU level versus higher levels. As an example, if the element at
2085index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2086state, special hardware logic may be programmed in order to keep track of the
2087residency statistics. For higher levels (array indices > 0), the residency
2088statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2089default implementation will use PMF to capture timestamps.
2090
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002091Function : plat_psci_stat_get_residency() [optional]
2092~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002093
2094::
2095
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -06002096 Argument : unsigned int, const psci_power_state_t *, unsigned int
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002097 Return : u_register_t
2098
2099This is an optional interface that is is invoked after resuming from a low power
2100state and provides the time spent resident in that low power state by the power
2101domain at a particular power domain level. When a CPU wakes up from suspend,
2102all its parent power domain levels are also woken up. The generic PSCI code
2103invokes this function for each parent power domain that is resumed and it
2104identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second
2105argument) describes the low power state that the power domain has resumed from.
2106The current CPU is the first CPU in the power domain to resume from the low
2107power state and the ``last_cpu_idx`` (third parameter) is the index of the last
2108CPU in the power domain to suspend and may be needed to calculate the residency
2109for that power domain.
2110
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002111Function : plat_get_target_pwr_state() [optional]
2112~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002113
2114::
2115
2116 Argument : unsigned int, const plat_local_state_t *, unsigned int
2117 Return : plat_local_state_t
2118
2119The PSCI generic code uses this function to let the platform participate in
2120state coordination during a power management operation. The function is passed
2121a pointer to an array of platform specific local power state ``states`` (second
2122argument) which contains the requested power state for each CPU at a particular
2123power domain level ``lvl`` (first argument) within the power domain. The function
2124is expected to traverse this array of upto ``ncpus`` (third argument) and return
2125a coordinated target power state by the comparing all the requested power
2126states. The target power state should not be deeper than any of the requested
2127power states.
2128
2129A weak definition of this API is provided by default wherein it assumes
2130that the platform assigns a local state value in order of increasing depth
2131of the power state i.e. for two power states X & Y, if X < Y
2132then X represents a shallower power state than Y. As a result, the
2133coordinated target local power state for a power domain will be the minimum
2134of the requested local power state values.
2135
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002136Function : plat_get_power_domain_tree_desc() [mandatory]
2137~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002138
2139::
2140
2141 Argument : void
2142 Return : const unsigned char *
2143
2144This function returns a pointer to the byte array containing the power domain
2145topology tree description. The format and method to construct this array are
Paul Beesleyf8640672019-04-12 14:19:42 +01002146described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI
2147initialization code requires this array to be described by the platform, either
2148statically or dynamically, to initialize the power domain topology tree. In case
2149the array is populated dynamically, then plat_core_pos_by_mpidr() and
2150plat_my_core_pos() should also be implemented suitably so that the topology tree
2151description matches the CPU indices returned by these APIs. These APIs together
2152form the platform interface for the PSCI topology framework.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002153
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002154Function : plat_setup_psci_ops() [mandatory]
2155~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002156
2157::
2158
2159 Argument : uintptr_t, const plat_psci_ops **
2160 Return : int
2161
2162This function may execute with the MMU and data caches enabled if the platform
2163port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
2164called by the primary CPU.
2165
2166This function is called by PSCI initialization code. Its purpose is to let
2167the platform layer know about the warm boot entrypoint through the
2168``sec_entrypoint`` (first argument) and to export handler routines for
2169platform-specific psci power management actions by populating the passed
2170pointer with a pointer to BL31's private ``plat_psci_ops`` structure.
2171
2172A description of each member of this structure is given below. Please refer to
Dan Handley610e7e12018-03-01 18:44:00 +00002173the Arm FVP specific implementation of these handlers in
Paul Beesleyf8640672019-04-12 14:19:42 +01002174``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002175platform wants to support, the associated operation or operations in this
2176structure must be provided and implemented (Refer section 4 of
Paul Beesleyf8640672019-04-12 14:19:42 +01002177:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI
Dan Handley610e7e12018-03-01 18:44:00 +00002178function in a platform port, the operation should be removed from this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002179structure instead of providing an empty implementation.
2180
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002181plat_psci_ops.cpu_standby()
2182...........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002183
2184Perform the platform-specific actions to enter the standby state for a cpu
2185indicated by the passed argument. This provides a fast path for CPU standby
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002186wherein overheads of PSCI state management and lock acquisition is avoided.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002187For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation,
2188the suspend state type specified in the ``power-state`` parameter should be
2189STANDBY and the target power domain level specified should be the CPU. The
2190handler should put the CPU into a low power retention state (usually by
2191issuing a wfi instruction) and ensure that it can be woken up from that
2192state by a normal interrupt. The generic code expects the handler to succeed.
2193
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002194plat_psci_ops.pwr_domain_on()
2195.............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002196
2197Perform the platform specific actions to power on a CPU, specified
2198by the ``MPIDR`` (first argument). The generic code expects the platform to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002199return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002200
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002201plat_psci_ops.pwr_domain_off()
2202..............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002203
2204Perform the platform specific actions to prepare to power off the calling CPU
2205and its higher parent power domain levels as indicated by the ``target_state``
2206(first argument). It is called by the PSCI ``CPU_OFF`` API implementation.
2207
2208The ``target_state`` encodes the platform coordinated target local power states
2209for the CPU power domain and its parent power domain levels. The handler
2210needs to perform power management operation corresponding to the local state
2211at each power level.
2212
2213For this handler, the local power state for the CPU power domain will be a
2214power down state where as it could be either power down, retention or run state
2215for the higher power domain levels depending on the result of state
2216coordination. The generic code expects the handler to succeed.
2217
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002218plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]
2219...........................................................
Varun Wadekarae87f4b2017-07-10 16:02:05 -07002220
2221This optional function may be used as a performance optimization to replace
2222or complement pwr_domain_suspend() on some platforms. Its calling semantics
2223are identical to pwr_domain_suspend(), except the PSCI implementation only
2224calls this function when suspending to a power down state, and it guarantees
2225that data caches are enabled.
2226
2227When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches
2228before calling pwr_domain_suspend(). If the target_state corresponds to a
2229power down state and it is safe to perform some or all of the platform
2230specific actions in that function with data caches enabled, it may be more
2231efficient to move those actions to this function. When HW_ASSISTED_COHERENCY
2232= 1, data caches remain enabled throughout, and so there is no advantage to
2233moving platform specific actions to this function.
2234
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002235plat_psci_ops.pwr_domain_suspend()
2236..................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002237
2238Perform the platform specific actions to prepare to suspend the calling
2239CPU and its higher parent power domain levels as indicated by the
2240``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND``
2241API implementation.
2242
2243The ``target_state`` has a similar meaning as described in
2244the ``pwr_domain_off()`` operation. It encodes the platform coordinated
2245target local power states for the CPU power domain and its parent
2246power domain levels. The handler needs to perform power management operation
2247corresponding to the local state at each power level. The generic code
2248expects the handler to succeed.
2249
Douglas Raillarda84996b2017-08-02 16:57:32 +01002250The difference between turning a power domain off versus suspending it is that
2251in the former case, the power domain is expected to re-initialize its state
2252when it is next powered on (see ``pwr_domain_on_finish()``). In the latter
2253case, the power domain is expected to save enough state so that it can resume
2254execution by restoring this state when its powered on (see
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002255``pwr_domain_suspend_finish()``).
2256
Douglas Raillarda84996b2017-08-02 16:57:32 +01002257When suspending a core, the platform can also choose to power off the GICv3
2258Redistributor and ITS through an implementation-defined sequence. To achieve
2259this safely, the ITS context must be saved first. The architectural part is
2260implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed
2261sequence is implementation defined and it is therefore the responsibility of
2262the platform code to implement the necessary sequence. Then the GIC
2263Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper.
2264Powering off the Redistributor requires the implementation to support it and it
2265is the responsibility of the platform code to execute the right implementation
2266defined sequence.
2267
2268When a system suspend is requested, the platform can also make use of the
2269``gicv3_distif_save()`` helper to save the context of the GIC Distributor after
2270it has saved the context of the Redistributors and ITS of all the cores in the
2271system. The context of the Distributor can be large and may require it to be
2272allocated in a special area if it cannot fit in the platform's global static
2273data, for example in DRAM. The Distributor can then be powered down using an
2274implementation-defined sequence.
2275
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002276plat_psci_ops.pwr_domain_pwr_down_wfi()
2277.......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002278
2279This is an optional function and, if implemented, is expected to perform
2280platform specific actions including the ``wfi`` invocation which allows the
2281CPU to powerdown. Since this function is invoked outside the PSCI locks,
2282the actions performed in this hook must be local to the CPU or the platform
2283must ensure that races between multiple CPUs cannot occur.
2284
2285The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()``
2286operation and it encodes the platform coordinated target local power states for
2287the CPU power domain and its parent power domain levels. This function must
2288not return back to the caller.
2289
2290If this function is not implemented by the platform, PSCI generic
2291implementation invokes ``psci_power_down_wfi()`` for power down.
2292
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002293plat_psci_ops.pwr_domain_on_finish()
2294....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002295
2296This function is called by the PSCI implementation after the calling CPU is
2297powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
2298It performs the platform-specific setup required to initialize enough state for
2299this CPU to enter the normal world and also provide secure runtime firmware
2300services.
2301
2302The ``target_state`` (first argument) is the prior state of the power domains
2303immediately before the CPU was turned on. It indicates which power domains
2304above the CPU might require initialization due to having previously been in
2305low power states. The generic code expects the handler to succeed.
2306
Madhukar Pappireddy33bd5142019-08-12 18:31:33 -05002307plat_psci_ops.pwr_domain_on_finish_late() [optional]
2308...........................................................
2309
2310This optional function is called by the PSCI implementation after the calling
2311CPU is fully powered on with respective data caches enabled. The calling CPU and
2312the associated cluster are guaranteed to be participating in coherency. This
2313function gives the flexibility to perform any platform-specific actions safely,
2314such as initialization or modification of shared data structures, without the
2315overhead of explicit cache maintainace operations.
2316
2317The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()``
2318operation. The generic code expects the handler to succeed.
2319
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002320plat_psci_ops.pwr_domain_suspend_finish()
2321.........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002322
2323This function is called by the PSCI implementation after the calling CPU is
2324powered on and released from reset in response to an asynchronous wakeup
2325event, for example a timer interrupt that was programmed by the CPU during the
2326``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
2327setup required to restore the saved state for this CPU to resume execution
2328in the normal world and also provide secure runtime firmware services.
2329
2330The ``target_state`` (first argument) has a similar meaning as described in
2331the ``pwr_domain_on_finish()`` operation. The generic code expects the platform
2332to succeed.
2333
Douglas Raillarda84996b2017-08-02 16:57:32 +01002334If the Distributor, Redistributors or ITS have been powered off as part of a
2335suspend, their context must be restored in this function in the reverse order
2336to how they were saved during suspend sequence.
2337
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002338plat_psci_ops.system_off()
2339..........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002340
2341This function is called by PSCI implementation in response to a ``SYSTEM_OFF``
2342call. It performs the platform-specific system poweroff sequence after
2343notifying the Secure Payload Dispatcher.
2344
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002345plat_psci_ops.system_reset()
2346............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002347
2348This function is called by PSCI implementation in response to a ``SYSTEM_RESET``
2349call. It performs the platform-specific system reset sequence after
2350notifying the Secure Payload Dispatcher.
2351
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002352plat_psci_ops.validate_power_state()
2353....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002354
2355This function is called by the PSCI implementation during the ``CPU_SUSPEND``
2356call to validate the ``power_state`` parameter of the PSCI API and if valid,
2357populate it in ``req_state`` (second argument) array as power domain level
2358specific local states. If the ``power_state`` is invalid, the platform must
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002359return PSCI_E_INVALID_PARAMS as error, which is propagated back to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002360normal world PSCI client.
2361
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002362plat_psci_ops.validate_ns_entrypoint()
2363......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002364
2365This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
2366``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point``
2367parameter passed by the normal world. If the ``entry_point`` is invalid,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002368the platform must return PSCI_E_INVALID_ADDRESS as error, which is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002369propagated back to the normal world PSCI client.
2370
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002371plat_psci_ops.get_sys_suspend_power_state()
2372...........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002373
2374This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
2375call to get the ``req_state`` parameter from platform which encodes the power
2376domain level specific local states to suspend to system affinity level. The
2377``req_state`` will be utilized to do the PSCI state coordination and
2378``pwr_domain_suspend()`` will be invoked with the coordinated target state to
2379enter system suspend.
2380
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002381plat_psci_ops.get_pwr_lvl_state_idx()
2382.....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002383
2384This is an optional function and, if implemented, is invoked by the PSCI
2385implementation to convert the ``local_state`` (first argument) at a specified
2386``pwr_lvl`` (second argument) to an index between 0 and
2387``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform
2388supports more than two local power states at each power domain level, that is
2389``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these
2390local power states.
2391
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002392plat_psci_ops.translate_power_state_by_mpidr()
2393..............................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002394
2395This is an optional function and, if implemented, verifies the ``power_state``
2396(second argument) parameter of the PSCI API corresponding to a target power
2397domain. The target power domain is identified by using both ``MPIDR`` (first
2398argument) and the power domain level encoded in ``power_state``. The power domain
2399level specific local states are to be extracted from ``power_state`` and be
2400populated in the ``output_state`` (third argument) array. The functionality
2401is similar to the ``validate_power_state`` function described above and is
2402envisaged to be used in case the validity of ``power_state`` depend on the
2403targeted power domain. If the ``power_state`` is invalid for the targeted power
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002404domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002405function is not implemented, then the generic implementation relies on
2406``validate_power_state`` function to translate the ``power_state``.
2407
2408This function can also be used in case the platform wants to support local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002409power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002410APIs as described in Section 5.18 of `PSCI`_.
2411
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002412plat_psci_ops.get_node_hw_state()
2413.................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002414
2415This is an optional function. If implemented this function is intended to return
2416the power state of a node (identified by the first parameter, the ``MPIDR``) in
2417the power domain topology (identified by the second parameter, ``power_level``),
2418as retrieved from a power controller or equivalent component on the platform.
2419Upon successful completion, the implementation must map and return the final
2420status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it
2421must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as
2422appropriate.
2423
2424Implementations are not expected to handle ``power_levels`` greater than
2425``PLAT_MAX_PWR_LVL``.
2426
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002427plat_psci_ops.system_reset2()
2428.............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002429
2430This is an optional function. If implemented this function is
2431called during the ``SYSTEM_RESET2`` call to perform a reset
2432based on the first parameter ``reset_type`` as specified in
2433`PSCI`_. The parameter ``cookie`` can be used to pass additional
2434reset information. If the ``reset_type`` is not supported, the
2435function must return ``PSCI_E_NOT_SUPPORTED``. For architectural
2436resets, all failures must return ``PSCI_E_INVALID_PARAMETERS``
2437and vendor reset can return other PSCI error codes as defined
2438in `PSCI`_. On success this function will not return.
2439
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002440plat_psci_ops.write_mem_protect()
2441.................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002442
2443This is an optional function. If implemented it enables or disables the
2444``MEM_PROTECT`` functionality based on the value of ``val``.
2445A non-zero value enables ``MEM_PROTECT`` and a value of zero
2446disables it. Upon encountering failures it must return a negative value
2447and on success it must return 0.
2448
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002449plat_psci_ops.read_mem_protect()
2450................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002451
2452This is an optional function. If implemented it returns the current
2453state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering
2454failures it must return a negative value and on success it must
2455return 0.
2456
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002457plat_psci_ops.mem_protect_chk()
2458...............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002459
2460This is an optional function. If implemented it checks if a memory
2461region defined by a base address ``base`` and with a size of ``length``
2462bytes is protected by ``MEM_PROTECT``. If the region is protected
2463then it must return 0, otherwise it must return a negative number.
2464
Paul Beesleyf8640672019-04-12 14:19:42 +01002465.. _porting_guide_imf_in_bl31:
2466
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002467Interrupt Management framework (in BL31)
2468----------------------------------------
2469
2470BL31 implements an Interrupt Management Framework (IMF) to manage interrupts
2471generated in either security state and targeted to EL1 or EL2 in the non-secure
2472state or EL3/S-EL1 in the secure state. The design of this framework is
Paul Beesleyf8640672019-04-12 14:19:42 +01002473described in the :ref:`Interrupt Management Framework`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002474
2475A platform should export the following APIs to support the IMF. The following
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002476text briefly describes each API and its implementation in Arm standard
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002477platforms. The API implementation depends upon the type of interrupt controller
Dan Handley610e7e12018-03-01 18:44:00 +00002478present in the platform. Arm standard platform layer supports both
2479`Arm Generic Interrupt Controller version 2.0 (GICv2)`_
2480and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the
2481FVP can be configured to use either GICv2 or GICv3 depending on the build flag
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01002482``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more
2483details).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002484
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002485See also: `Interrupt Controller Abstraction APIs`__.
2486
Paul Beesleyea225122019-02-11 17:54:45 +00002487.. __: ../design/platform-interrupt-controller-API.rst
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002488
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002489Function : plat_interrupt_type_to_line() [mandatory]
2490~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002491
2492::
2493
2494 Argument : uint32_t, uint32_t
2495 Return : uint32_t
2496
Dan Handley610e7e12018-03-01 18:44:00 +00002497The Arm processor signals an interrupt exception either through the IRQ or FIQ
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002498interrupt line. The specific line that is signaled depends on how the interrupt
2499controller (IC) reports different interrupt types from an execution context in
2500either security state. The IMF uses this API to determine which interrupt line
2501the platform IC uses to signal each type of interrupt supported by the framework
2502from a given security state. This API must be invoked at EL3.
2503
2504The first parameter will be one of the ``INTR_TYPE_*`` values (see
Paul Beesleyf8640672019-04-12 14:19:42 +01002505:ref:`Interrupt Management Framework`) indicating the target type of the
2506interrupt, the second parameter is the security state of the originating
2507execution context. The return result is the bit position in the ``SCR_EL3``
2508register of the respective interrupt trap: IRQ=1, FIQ=2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002509
Dan Handley610e7e12018-03-01 18:44:00 +00002510In the case of Arm standard platforms using GICv2, S-EL1 interrupts are
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002511configured as FIQs and Non-secure interrupts as IRQs from either security
2512state.
2513
Dan Handley610e7e12018-03-01 18:44:00 +00002514In the case of Arm standard platforms using GICv3, the interrupt line to be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002515configured depends on the security state of the execution context when the
2516interrupt is signalled and are as follows:
2517
2518- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in
2519 NS-EL0/1/2 context.
2520- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ
2521 in the NS-EL0/1/2 context.
2522- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2
2523 context.
2524
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002525Function : plat_ic_get_pending_interrupt_type() [mandatory]
2526~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002527
2528::
2529
2530 Argument : void
2531 Return : uint32_t
2532
2533This API returns the type of the highest priority pending interrupt at the
2534platform IC. The IMF uses the interrupt type to retrieve the corresponding
2535handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt
2536pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``,
2537``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3.
2538
Dan Handley610e7e12018-03-01 18:44:00 +00002539In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002540Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of
2541the pending interrupt. The type of interrupt depends upon the id value as
2542follows.
2543
2544#. id < 1022 is reported as a S-EL1 interrupt
2545#. id = 1022 is reported as a Non-secure interrupt.
2546#. id = 1023 is reported as an invalid interrupt type.
2547
Dan Handley610e7e12018-03-01 18:44:00 +00002548In the case of Arm standard platforms using GICv3, the system register
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002549``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*,
2550is read to determine the id of the pending interrupt. The type of interrupt
2551depends upon the id value as follows.
2552
2553#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt
2554#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt.
2555#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type.
2556#. All other interrupt id's are reported as EL3 interrupt.
2557
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002558Function : plat_ic_get_pending_interrupt_id() [mandatory]
2559~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002560
2561::
2562
2563 Argument : void
2564 Return : uint32_t
2565
2566This API returns the id of the highest priority pending interrupt at the
2567platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt
2568pending.
2569
Dan Handley610e7e12018-03-01 18:44:00 +00002570In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002571Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the
2572pending interrupt. The id that is returned by API depends upon the value of
2573the id read from the interrupt controller as follows.
2574
2575#. id < 1022. id is returned as is.
2576#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register*
2577 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt.
2578 This id is returned by the API.
2579#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned.
2580
Dan Handley610e7e12018-03-01 18:44:00 +00002581In the case of Arm standard platforms using GICv3, if the API is invoked from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002582EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt
2583group 0 Register*, is read to determine the id of the pending interrupt. The id
2584that is returned by API depends upon the value of the id read from the
2585interrupt controller as follows.
2586
2587#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is.
2588#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system
2589 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1
2590 Register* is read to determine the id of the group 1 interrupt. This id
2591 is returned by the API as long as it is a valid interrupt id
2592#. If the id is any of the special interrupt identifiers,
2593 ``INTR_ID_UNAVAILABLE`` is returned.
2594
2595When the API invoked from S-EL1 for GICv3 systems, the id read from system
2596register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002597Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002598``INTR_ID_UNAVAILABLE`` is returned.
2599
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002600Function : plat_ic_acknowledge_interrupt() [mandatory]
2601~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002602
2603::
2604
2605 Argument : void
2606 Return : uint32_t
2607
2608This API is used by the CPU to indicate to the platform IC that processing of
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002609the highest pending interrupt has begun. It should return the raw, unmodified
2610value obtained from the interrupt controller when acknowledging an interrupt.
2611The actual interrupt number shall be extracted from this raw value using the API
2612`plat_ic_get_interrupt_id()`__.
2613
Paul Beesleyea225122019-02-11 17:54:45 +00002614.. __: ../design/platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002615
Dan Handley610e7e12018-03-01 18:44:00 +00002616This function in Arm standard platforms using GICv2, reads the *Interrupt
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002617Acknowledge Register* (``GICC_IAR``). This changes the state of the highest
2618priority pending interrupt from pending to active in the interrupt controller.
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002619It returns the value read from the ``GICC_IAR``, unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002620
Dan Handley610e7e12018-03-01 18:44:00 +00002621In the case of Arm standard platforms using GICv3, if the API is invoked
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002622from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt
2623Acknowledge Register group 0*. If the API is invoked from S-EL1, the function
2624reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register
2625group 1*. The read changes the state of the highest pending interrupt from
2626pending to active in the interrupt controller. The value read is returned
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002627unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002628
2629The TSP uses this API to start processing of the secure physical timer
2630interrupt.
2631
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002632Function : plat_ic_end_of_interrupt() [mandatory]
2633~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002634
2635::
2636
2637 Argument : uint32_t
2638 Return : void
2639
2640This API is used by the CPU to indicate to the platform IC that processing of
2641the interrupt corresponding to the id (passed as the parameter) has
2642finished. The id should be the same as the id returned by the
2643``plat_ic_acknowledge_interrupt()`` API.
2644
Dan Handley610e7e12018-03-01 18:44:00 +00002645Arm standard platforms write the id to the *End of Interrupt Register*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002646(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1``
2647system register in case of GICv3 depending on where the API is invoked from,
2648EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt
2649controller.
2650
2651The TSP uses this API to finish processing of the secure physical timer
2652interrupt.
2653
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002654Function : plat_ic_get_interrupt_type() [mandatory]
2655~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002656
2657::
2658
2659 Argument : uint32_t
2660 Return : uint32_t
2661
2662This API returns the type of the interrupt id passed as the parameter.
2663``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid
2664interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is
2665returned depending upon how the interrupt has been configured by the platform
2666IC. This API must be invoked at EL3.
2667
Dan Handley610e7e12018-03-01 18:44:00 +00002668Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002669and Non-secure interrupts as Group1 interrupts. It reads the group value
2670corresponding to the interrupt id from the relevant *Interrupt Group Register*
2671(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt.
2672
Dan Handley610e7e12018-03-01 18:44:00 +00002673In the case of Arm standard platforms using GICv3, both the *Interrupt Group
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002674Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register*
2675(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured
2676as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt.
2677
2678Crash Reporting mechanism (in BL31)
2679-----------------------------------
2680
2681BL31 implements a crash reporting mechanism which prints the various registers
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002682of the CPU to enable quick crash analysis and debugging. This mechanism relies
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002683on the platform implementing ``plat_crash_console_init``,
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002684``plat_crash_console_putc`` and ``plat_crash_console_flush``.
2685
2686The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample
2687implementation of all of them. Platforms may include this file to their
2688makefiles in order to benefit from them. By default, they will cause the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07002689output to be routed over the normal console infrastructure and get printed on
2690consoles configured to output in crash state. ``console_set_scope()`` can be
2691used to control whether a console is used for crash output.
Paul Beesleyba3ed402019-03-13 16:20:44 +00002692
2693.. note::
2694 Platforms are responsible for making sure that they only mark consoles for
2695 use in the crash scope that are able to support this, i.e. that are written
2696 in assembly and conform with the register clobber rules for putc()
2697 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002698
Julius Werneraae9bb12017-09-18 16:49:48 -07002699In some cases (such as debugging very early crashes that happen before the
2700normal boot console can be set up), platforms may want to control crash output
Julius Werner1338c9c2018-11-19 14:25:55 -08002701more explicitly. These platforms may instead provide custom implementations for
2702these. They are executed outside of a C environment and without a stack. Many
2703console drivers provide functions named ``console_xxx_core_init/putc/flush``
2704that are designed to be used by these functions. See Arm platforms (like juno)
2705for an example of this.
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002706
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002707Function : plat_crash_console_init [mandatory]
2708~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002709
2710::
2711
2712 Argument : void
2713 Return : int
2714
2715This API is used by the crash reporting mechanism to initialize the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07002716console. It must only use the general purpose registers x0 through x7 to do the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002717initialization and returns 1 on success.
2718
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002719Function : plat_crash_console_putc [mandatory]
2720~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002721
2722::
2723
2724 Argument : int
2725 Return : int
2726
2727This API is used by the crash reporting mechanism to print a character on the
2728designated crash console. It must only use general purpose registers x1 and
2729x2 to do its work. The parameter and the return value are in general purpose
2730register x0.
2731
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002732Function : plat_crash_console_flush [mandatory]
2733~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002734
2735::
2736
2737 Argument : void
2738 Return : int
2739
2740This API is used by the crash reporting mechanism to force write of all buffered
2741data on the designated crash console. It should only use general purpose
Julius Werneraae9bb12017-09-18 16:49:48 -07002742registers x0 through x5 to do its work. The return value is 0 on successful
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002743completion; otherwise the return value is -1.
2744
Manish Pandey9c9f38a2020-06-30 00:46:08 +01002745.. _External Abort handling and RAS Support:
2746
Jeenu Viswambharane34bf582018-10-12 08:48:36 +01002747External Abort handling and RAS Support
2748---------------------------------------
Jeenu Viswambharanbf235bc2018-07-12 10:00:01 +01002749
2750Function : plat_ea_handler
2751~~~~~~~~~~~~~~~~~~~~~~~~~~
2752
2753::
2754
2755 Argument : int
2756 Argument : uint64_t
2757 Argument : void *
2758 Argument : void *
2759 Argument : uint64_t
2760 Return : void
2761
2762This function is invoked by the RAS framework for the platform to handle an
2763External Abort received at EL3. The intention of the function is to attempt to
2764resolve the cause of External Abort and return; if that's not possible, to
2765initiate orderly shutdown of the system.
2766
2767The first parameter (``int ea_reason``) indicates the reason for External Abort.
2768Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``.
2769
2770The second parameter (``uint64_t syndrome``) is the respective syndrome
2771presented to EL3 after having received the External Abort. Depending on the
2772nature of the abort (as can be inferred from the ``ea_reason`` parameter), this
2773can be the content of either ``ESR_EL3`` or ``DISR_EL1``.
2774
2775The third parameter (``void *cookie``) is unused for now. The fourth parameter
2776(``void *handle``) is a pointer to the preempted context. The fifth parameter
2777(``uint64_t flags``) indicates the preempted security state. These parameters
2778are received from the top-level exception handler.
2779
2780If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this
2781function iterates through RAS handlers registered by the platform. If any of the
2782RAS handlers resolve the External Abort, no further action is taken.
2783
2784If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers
2785could resolve the External Abort, the default implementation prints an error
2786message, and panics.
2787
2788Function : plat_handle_uncontainable_ea
2789~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2790
2791::
2792
2793 Argument : int
2794 Argument : uint64_t
2795 Return : void
2796
2797This function is invoked by the RAS framework when an External Abort of
2798Uncontainable type is received at EL3. Due to the critical nature of
2799Uncontainable errors, the intention of this function is to initiate orderly
2800shutdown of the system, and is not expected to return.
2801
2802This function must be implemented in assembly.
2803
2804The first and second parameters are the same as that of ``plat_ea_handler``.
2805
2806The default implementation of this function calls
2807``report_unhandled_exception``.
2808
2809Function : plat_handle_double_fault
2810~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2811
2812::
2813
2814 Argument : int
2815 Argument : uint64_t
2816 Return : void
2817
2818This function is invoked by the RAS framework when another External Abort is
2819received at EL3 while one is already being handled. I.e., a call to
2820``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of
2821this function is to initiate orderly shutdown of the system, and is not expected
2822recover or return.
2823
2824This function must be implemented in assembly.
2825
2826The first and second parameters are the same as that of ``plat_ea_handler``.
2827
2828The default implementation of this function calls
2829``report_unhandled_exception``.
2830
2831Function : plat_handle_el3_ea
2832~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2833
2834::
2835
2836 Return : void
2837
2838This function is invoked when an External Abort is received while executing in
2839EL3. Due to its critical nature, the intention of this function is to initiate
2840orderly shutdown of the system, and is not expected recover or return.
2841
2842This function must be implemented in assembly.
2843
2844The default implementation of this function calls
2845``report_unhandled_exception``.
2846
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002847Build flags
2848-----------
2849
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002850There are some build flags which can be defined by the platform to control
2851inclusion or exclusion of certain BL stages from the FIP image. These flags
2852need to be defined in the platform makefile which will get included by the
2853build system.
2854
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002855- **NEED_BL33**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002856 By default, this flag is defined ``yes`` by the build system and ``BL33``
2857 build option should be supplied as a build option. The platform has the
2858 option of excluding the BL33 image in the ``fip`` image by defining this flag
2859 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE``
2860 are used, this flag will be set to ``no`` automatically.
2861
Paul Beesley07f0a312019-05-16 13:33:18 +01002862Platform include paths
2863----------------------
2864
2865Platforms are allowed to add more include paths to be passed to the compiler.
2866The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in
2867particular for the file ``platform_def.h``.
2868
2869Example:
2870
2871.. code:: c
2872
2873 PLAT_INCLUDES += -Iinclude/plat/myplat/include
2874
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002875C Library
2876---------
2877
2878To avoid subtle toolchain behavioral dependencies, the header files provided
2879by the compiler are not used. The software is built with the ``-nostdinc`` flag
2880to ensure no headers are included from the toolchain inadvertently. Instead the
Dan Handley610e7e12018-03-01 18:44:00 +00002881required headers are included in the TF-A source tree. The library only
2882contains those C library definitions required by the local implementation. If
2883more functionality is required, the needed library functions will need to be
2884added to the local implementation.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002885
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01002886Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have
Paul Beesleyf2ec7142019-10-04 16:17:46 +00002887been written specifically for TF-A. Some implementation files have been obtained
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01002888from `FreeBSD`_, others have been written specifically for TF-A as well. The
2889files can be found in ``include/lib/libc`` and ``lib/libc``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002890
Sandrine Bailleux6f0ecd72019-02-08 14:46:42 +01002891SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources
2892can be obtained from http://github.com/freebsd/freebsd.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002893
2894Storage abstraction layer
2895-------------------------
2896
Louis Mayencourtb5469002019-07-15 13:56:03 +01002897In order to improve platform independence and portability a storage abstraction
2898layer is used to load data from non-volatile platform storage. Currently
2899storage access is only required by BL1 and BL2 phases and performed inside the
2900``load_image()`` function in ``bl_common.c``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002901
Louis Mayencourtb5469002019-07-15 13:56:03 +01002902.. uml:: ../resources/diagrams/plantuml/io_framework_usage_overview.puml
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002903
Dan Handley610e7e12018-03-01 18:44:00 +00002904It is mandatory to implement at least one storage driver. For the Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002905development platforms the Firmware Image Package (FIP) driver is provided as
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01002906the default means to load data from storage (see :ref:`firmware_design_fip`).
2907The storage layer is described in the header file
2908``include/drivers/io/io_storage.h``. The implementation of the common library is
2909in ``drivers/io/io_storage.c`` and the driver files are located in
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002910``drivers/io/``.
2911
Louis Mayencourtb5469002019-07-15 13:56:03 +01002912.. uml:: ../resources/diagrams/plantuml/io_arm_class_diagram.puml
2913
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002914Each IO driver must provide ``io_dev_*`` structures, as described in
2915``drivers/io/io_driver.h``. These are returned via a mandatory registration
2916function that is called on platform initialization. The semi-hosting driver
2917implementation in ``io_semihosting.c`` can be used as an example.
2918
Louis Mayencourtb5469002019-07-15 13:56:03 +01002919Each platform should register devices and their drivers via the storage
2920abstraction layer. These drivers then need to be initialized by bootloader
2921phases as required in their respective ``blx_platform_setup()`` functions.
2922
2923.. uml:: ../resources/diagrams/plantuml/io_dev_registration.puml
2924
2925The storage abstraction layer provides mechanisms (``io_dev_init()``) to
2926initialize storage devices before IO operations are called.
2927
2928.. uml:: ../resources/diagrams/plantuml/io_dev_init_and_check.puml
2929
2930The basic operations supported by the layer
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002931include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``.
2932Drivers do not have to implement all operations, but each platform must
2933provide at least one driver for a device capable of supporting generic
2934operations such as loading a bootloader image.
2935
2936The current implementation only allows for known images to be loaded by the
2937firmware. These images are specified by using their identifiers, as defined in
Antonio Nino Diaz645feb42019-02-13 14:07:38 +00002938``include/plat/common/common_def.h`` (or a separate header file included from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002939there). The platform layer (``plat_get_image_source()``) then returns a reference
2940to a device and a driver-specific ``spec`` which will be understood by the driver
2941to allow access to the image data.
2942
2943The layer is designed in such a way that is it possible to chain drivers with
2944other drivers. For example, file-system drivers may be implemented on top of
2945physical block devices, both represented by IO devices with corresponding
2946drivers. In such a case, the file-system "binding" with the block device may
2947be deferred until the file-system device is initialised.
2948
2949The abstraction currently depends on structures being statically allocated
2950by the drivers and callers, as the system does not yet provide a means of
2951dynamically allocating memory. This may also have the affect of limiting the
2952amount of open resources per driver.
2953
2954--------------
2955
Paul Beesley07f0a312019-05-16 13:33:18 +01002956*Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002957
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002958.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
Dan Handley610e7e12018-03-01 18:44:00 +00002959.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002960.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html
Paul Beesley2437ddc2019-02-08 16:43:05 +00002961.. _FreeBSD: https://www.freebsd.org
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01002962.. _SCC: http://www.simple-cc.org/