Porting Guide: Remove useless escape characters
Replace all occurences of escaped underscore characters by plain ones.
This makes the text version of the porting guide easier to read and
grep into.
Change-Id: I7bf3b292b686be4c6d847a467b6708ac16544c90
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index 655c720..6be1830 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -28,7 +28,7 @@
default implementation is inadequate.
Platform ports that want to be aligned with standard Arm platforms (for example
-FVP and Juno) may also use `include/plat/arm/common/plat\_arm.h`_ and the
+FVP and Juno) may also use `include/plat/arm/common/plat_arm.h`_ and the
corresponding source files in ``plat/arm/common/``. These provide standard
implementations for some of the required platform porting functions. However,
using these functions requires the platform port to implement additional
@@ -99,56 +99,56 @@
The following variables, functions and constants must be defined by the platform
for the firmware to work correctly.
-File : platform\_def.h [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+File : platform_def.h [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Each platform must ensure that a header file of this name is in the system
include path with the following constants defined. This will require updating
the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file.
-Platform ports may optionally use the file `include/plat/common/common\_def.h`_,
+Platform ports may optionally use the file `include/plat/common/common_def.h`_,
which provides typical values for some of the constants below. These values are
likely to be suitable for all platform ports.
-- **#define : PLATFORM\_LINKER\_FORMAT**
+- **#define : PLATFORM_LINKER_FORMAT**
Defines the linker format used by the platform, for example
``elf64-littleaarch64``.
-- **#define : PLATFORM\_LINKER\_ARCH**
+- **#define : PLATFORM_LINKER_ARCH**
Defines the processor architecture for the linker by the platform, for
example ``aarch64``.
-- **#define : PLATFORM\_STACK\_SIZE**
+- **#define : PLATFORM_STACK_SIZE**
Defines the normal stack memory available to each CPU. This constant is used
- by `plat/common/aarch64/platform\_mp\_stack.S`_ and
- `plat/common/aarch64/platform\_up\_stack.S`_.
+ by `plat/common/aarch64/platform_mp_stack.S`_ and
+ `plat/common/aarch64/platform_up_stack.S`_.
-- **define : CACHE\_WRITEBACK\_GRANULE**
+- **define : CACHE_WRITEBACK_GRANULE**
Defines the size in bits of the largest cache line across all the cache
levels in the platform.
-- **#define : FIRMWARE\_WELCOME\_STR**
+- **#define : FIRMWARE_WELCOME_STR**
Defines the character string printed by BL1 upon entry into the ``bl1_main()``
function.
-- **#define : PLATFORM\_CORE\_COUNT**
+- **#define : PLATFORM_CORE_COUNT**
Defines the total number of CPUs implemented by the platform across all
clusters in the system.
-- **#define : PLAT\_NUM\_PWR\_DOMAINS**
+- **#define : PLAT_NUM_PWR_DOMAINS**
Defines the total number of nodes in the power domain topology
tree at all the power domain levels used by the platform.
This macro is used by the PSCI implementation to allocate
data structures to represent power domain topology.
-- **#define : PLAT\_MAX\_PWR\_LVL**
+- **#define : PLAT_MAX_PWR_LVL**
Defines the maximum power domain level that the power management operations
should apply to. More often, but not always, the power domain level
@@ -158,24 +158,24 @@
example, the Base AEM FVP implements two clusters with a configurable
number of CPUs and it reports the maximum power domain level as 1.
-- **#define : PLAT\_MAX\_OFF\_STATE**
+- **#define : PLAT_MAX_OFF_STATE**
Defines the local power state corresponding to the deepest power down
possible at every power domain level in the platform. The local power
states for each level may be sparsely allocated between 0 and this value
with 0 being reserved for the RUN state. The PSCI implementation uses this
value to initialize the local power states of the power domain nodes and
- to specify the requested power state for a PSCI\_CPU\_OFF call.
+ to specify the requested power state for a PSCI_CPU_OFF call.
-- **#define : PLAT\_MAX\_RET\_STATE**
+- **#define : PLAT_MAX_RET_STATE**
Defines the local power state corresponding to the deepest retention state
possible at every power domain level in the platform. This macro should be
- a value less than PLAT\_MAX\_OFF\_STATE and greater than 0. It is used by the
+ a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the
PSCI implementation to distinguish between retention and power down local
- power states within PSCI\_CPU\_SUSPEND call.
+ power states within PSCI_CPU_SUSPEND call.
-- **#define : PLAT\_MAX\_PWR\_LVL\_STATES**
+- **#define : PLAT_MAX_PWR_LVL_STATES**
Defines the maximum number of local power states per power domain level
that the platform supports. The default value of this macro is 2 since
@@ -184,69 +184,69 @@
account for more local power states, then it must redefine this macro.
Currently, this macro is used by the Generic PSCI implementation to size
- the array used for PSCI\_STAT\_COUNT/RESIDENCY accounting.
+ the array used for PSCI_STAT_COUNT/RESIDENCY accounting.
-- **#define : BL1\_RO\_BASE**
+- **#define : BL1_RO_BASE**
Defines the base address in secure ROM where BL1 originally lives. Must be
aligned on a page-size boundary.
-- **#define : BL1\_RO\_LIMIT**
+- **#define : BL1_RO_LIMIT**
Defines the maximum address in secure ROM that BL1's actual content (i.e.
excluding any data section allocated at runtime) can occupy.
-- **#define : BL1\_RW\_BASE**
+- **#define : BL1_RW_BASE**
Defines the base address in secure RAM where BL1's read-write data will live
at runtime. Must be aligned on a page-size boundary.
-- **#define : BL1\_RW\_LIMIT**
+- **#define : BL1_RW_LIMIT**
Defines the maximum address in secure RAM that BL1's read-write data can
occupy at runtime.
-- **#define : BL2\_BASE**
+- **#define : BL2_BASE**
Defines the base address in secure RAM where BL1 loads the BL2 binary image.
Must be aligned on a page-size boundary. This constant is not applicable
when BL2_IN_XIP_MEM is set to '1'.
-- **#define : BL2\_LIMIT**
+- **#define : BL2_LIMIT**
Defines the maximum address in secure RAM that the BL2 image can occupy.
This constant is not applicable when BL2_IN_XIP_MEM is set to '1'.
-- **#define : BL2\_RO\_BASE**
+- **#define : BL2_RO_BASE**
Defines the base address in secure XIP memory where BL2 RO section originally
lives. Must be aligned on a page-size boundary. This constant is only needed
when BL2_IN_XIP_MEM is set to '1'.
-- **#define : BL2\_RO\_LIMIT**
+- **#define : BL2_RO_LIMIT**
Defines the maximum address in secure XIP memory that BL2's actual content
(i.e. excluding any data section allocated at runtime) can occupy. This
constant is only needed when BL2_IN_XIP_MEM is set to '1'.
-- **#define : BL2\_RW\_BASE**
+- **#define : BL2_RW_BASE**
Defines the base address in secure RAM where BL2's read-write data will live
at runtime. Must be aligned on a page-size boundary. This constant is only
needed when BL2_IN_XIP_MEM is set to '1'.
-- **#define : BL2\_RW\_LIMIT**
+- **#define : BL2_RW_LIMIT**
Defines the maximum address in secure RAM that BL2's read-write data can
occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set
to '1'.
-- **#define : BL31\_BASE**
+- **#define : BL31_BASE**
Defines the base address in secure RAM where BL2 loads the BL31 binary
image. Must be aligned on a page-size boundary.
-- **#define : BL31\_LIMIT**
+- **#define : BL31_LIMIT**
Defines the maximum address in secure RAM that the BL31 image can occupy.
@@ -258,57 +258,57 @@
authentication information, etc.). The following image identifiers are
mandatory:
-- **#define : BL2\_IMAGE\_ID**
+- **#define : BL2_IMAGE_ID**
BL2 image identifier, used by BL1 to load BL2.
-- **#define : BL31\_IMAGE\_ID**
+- **#define : BL31_IMAGE_ID**
BL31 image identifier, used by BL2 to load BL31.
-- **#define : BL33\_IMAGE\_ID**
+- **#define : BL33_IMAGE_ID**
BL33 image identifier, used by BL2 to load BL33.
If Trusted Board Boot is enabled, the following certificate identifiers must
also be defined:
-- **#define : TRUSTED\_BOOT\_FW\_CERT\_ID**
+- **#define : TRUSTED_BOOT_FW_CERT_ID**
BL2 content certificate identifier, used by BL1 to load the BL2 content
certificate.
-- **#define : TRUSTED\_KEY\_CERT\_ID**
+- **#define : TRUSTED_KEY_CERT_ID**
Trusted key certificate identifier, used by BL2 to load the trusted key
certificate.
-- **#define : SOC\_FW\_KEY\_CERT\_ID**
+- **#define : SOC_FW_KEY_CERT_ID**
BL31 key certificate identifier, used by BL2 to load the BL31 key
certificate.
-- **#define : SOC\_FW\_CONTENT\_CERT\_ID**
+- **#define : SOC_FW_CONTENT_CERT_ID**
BL31 content certificate identifier, used by BL2 to load the BL31 content
certificate.
-- **#define : NON\_TRUSTED\_FW\_KEY\_CERT\_ID**
+- **#define : NON_TRUSTED_FW_KEY_CERT_ID**
BL33 key certificate identifier, used by BL2 to load the BL33 key
certificate.
-- **#define : NON\_TRUSTED\_FW\_CONTENT\_CERT\_ID**
+- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID**
BL33 content certificate identifier, used by BL2 to load the BL33 content
certificate.
-- **#define : FWU\_CERT\_ID**
+- **#define : FWU_CERT_ID**
- Firmware Update (FWU) certificate identifier, used by NS\_BL1U to load the
+ Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
FWU content certificate.
-- **#define : PLAT\_CRYPTOCELL\_BASE**
+- **#define : PLAT_CRYPTOCELL_BASE**
This defines the base address of Arm® TrustZone® CryptoCell and must be
defined if CryptoCell crypto driver is used for Trusted Board Boot. For
@@ -318,125 +318,125 @@
If the AP Firmware Updater Configuration image, BL2U is used, the following
must also be defined:
-- **#define : BL2U\_BASE**
+- **#define : BL2U_BASE**
Defines the base address in secure memory where BL1 copies the BL2U binary
image. Must be aligned on a page-size boundary.
-- **#define : BL2U\_LIMIT**
+- **#define : BL2U_LIMIT**
Defines the maximum address in secure memory that the BL2U image can occupy.
-- **#define : BL2U\_IMAGE\_ID**
+- **#define : BL2U_IMAGE_ID**
BL2U image identifier, used by BL1 to fetch an image descriptor
corresponding to BL2U.
-If the SCP Firmware Update Configuration Image, SCP\_BL2U is used, the following
+If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following
must also be defined:
-- **#define : SCP\_BL2U\_IMAGE\_ID**
+- **#define : SCP_BL2U_IMAGE_ID**
- SCP\_BL2U image identifier, used by BL1 to fetch an image descriptor
- corresponding to SCP\_BL2U.
+ SCP_BL2U image identifier, used by BL1 to fetch an image descriptor
+ corresponding to SCP_BL2U.
NOTE: TF-A does not provide source code for this image.
-If the Non-Secure Firmware Updater ROM, NS\_BL1U is used, the following must
+If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must
also be defined:
-- **#define : NS\_BL1U\_BASE**
+- **#define : NS_BL1U_BASE**
- Defines the base address in non-secure ROM where NS\_BL1U executes.
+ Defines the base address in non-secure ROM where NS_BL1U executes.
Must be aligned on a page-size boundary.
NOTE: TF-A does not provide source code for this image.
-- **#define : NS\_BL1U\_IMAGE\_ID**
+- **#define : NS_BL1U_IMAGE_ID**
- NS\_BL1U image identifier, used by BL1 to fetch an image descriptor
- corresponding to NS\_BL1U.
+ NS_BL1U image identifier, used by BL1 to fetch an image descriptor
+ corresponding to NS_BL1U.
-If the Non-Secure Firmware Updater, NS\_BL2U is used, the following must also
+If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also
be defined:
-- **#define : NS\_BL2U\_BASE**
+- **#define : NS_BL2U_BASE**
- Defines the base address in non-secure memory where NS\_BL2U executes.
+ Defines the base address in non-secure memory where NS_BL2U executes.
Must be aligned on a page-size boundary.
NOTE: TF-A does not provide source code for this image.
-- **#define : NS\_BL2U\_IMAGE\_ID**
+- **#define : NS_BL2U_IMAGE_ID**
- NS\_BL2U image identifier, used by BL1 to fetch an image descriptor
- corresponding to NS\_BL2U.
+ NS_BL2U image identifier, used by BL1 to fetch an image descriptor
+ corresponding to NS_BL2U.
For the the Firmware update capability of TRUSTED BOARD BOOT, the following
macros may also be defined:
-- **#define : PLAT\_FWU\_MAX\_SIMULTANEOUS\_IMAGES**
+- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES**
Total number of images that can be loaded simultaneously. If the platform
doesn't specify any value, it defaults to 10.
-If a SCP\_BL2 image is supported by the platform, the following constants must
+If a SCP_BL2 image is supported by the platform, the following constants must
also be defined:
-- **#define : SCP\_BL2\_IMAGE\_ID**
+- **#define : SCP_BL2_IMAGE_ID**
- SCP\_BL2 image identifier, used by BL2 to load SCP\_BL2 into secure memory
+ SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory
from platform storage before being transferred to the SCP.
-- **#define : SCP\_FW\_KEY\_CERT\_ID**
+- **#define : SCP_FW_KEY_CERT_ID**
- SCP\_BL2 key certificate identifier, used by BL2 to load the SCP\_BL2 key
+ SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key
certificate (mandatory when Trusted Board Boot is enabled).
-- **#define : SCP\_FW\_CONTENT\_CERT\_ID**
+- **#define : SCP_FW_CONTENT_CERT_ID**
- SCP\_BL2 content certificate identifier, used by BL2 to load the SCP\_BL2
+ SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2
content certificate (mandatory when Trusted Board Boot is enabled).
If a BL32 image is supported by the platform, the following constants must
also be defined:
-- **#define : BL32\_IMAGE\_ID**
+- **#define : BL32_IMAGE_ID**
BL32 image identifier, used by BL2 to load BL32.
-- **#define : TRUSTED\_OS\_FW\_KEY\_CERT\_ID**
+- **#define : TRUSTED_OS_FW_KEY_CERT_ID**
BL32 key certificate identifier, used by BL2 to load the BL32 key
certificate (mandatory when Trusted Board Boot is enabled).
-- **#define : TRUSTED\_OS\_FW\_CONTENT\_CERT\_ID**
+- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID**
BL32 content certificate identifier, used by BL2 to load the BL32 content
certificate (mandatory when Trusted Board Boot is enabled).
-- **#define : BL32\_BASE**
+- **#define : BL32_BASE**
Defines the base address in secure memory where BL2 loads the BL32 binary
image. Must be aligned on a page-size boundary.
-- **#define : BL32\_LIMIT**
+- **#define : BL32_LIMIT**
Defines the maximum address that the BL32 image can occupy.
If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the
platform, the following constants must also be defined:
-- **#define : TSP\_SEC\_MEM\_BASE**
+- **#define : TSP_SEC_MEM_BASE**
Defines the base address of the secure memory used by the TSP image on the
platform. This must be at the same address or below ``BL32_BASE``.
-- **#define : TSP\_SEC\_MEM\_SIZE**
+- **#define : TSP_SEC_MEM_SIZE**
Defines the size of the secure memory used by the BL32 image on the
platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully
accommodate the memory required by the BL32 image, defined by ``BL32_BASE``
and ``BL32_LIMIT``.
-- **#define : TSP\_IRQ\_SEC\_PHY\_TIMER**
+- **#define : TSP_IRQ_SEC_PHY_TIMER**
Defines the ID of the secure physical generic timer interrupt used by the
TSP's interrupt handling code.
@@ -444,14 +444,14 @@
If the platform port uses the translation table library code, the following
constants must also be defined:
-- **#define : PLAT\_XLAT\_TABLES\_DYNAMIC**
+- **#define : PLAT_XLAT_TABLES_DYNAMIC**
Optional flag that can be set per-image to enable the dynamic allocation of
regions even when the MMU is enabled. If not defined, only static
functionality will be available, if defined and set to 1 it will also
include the dynamic functionality.
-- **#define : MAX\_XLAT\_TABLES**
+- **#define : MAX_XLAT_TABLES**
Defines the maximum number of translation tables that are allocated by the
translation table library code. To minimize the amount of runtime memory
@@ -460,7 +460,7 @@
image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions
as well.
-- **#define : MAX\_MMAP\_REGIONS**
+- **#define : MAX_MMAP_REGIONS**
Defines the maximum number of regions that are allocated by the translation
table library code. A region consists of physical base address, virtual base
@@ -473,12 +473,12 @@
enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate
the dynamic regions as well.
-- **#define : PLAT\_VIRT\_ADDR\_SPACE\_SIZE**
+- **#define : PLAT_VIRT_ADDR_SPACE_SIZE**
Defines the total size of the virtual address space in bytes. For example,
for a 32 bit virtual address space, this value should be ``(1ULL << 32)``.
-- **#define : PLAT\_PHY\_ADDR\_SPACE\_SIZE**
+- **#define : PLAT_PHY_ADDR_SPACE_SIZE**
Defines the total size of the physical address space in bytes. For example,
for a 32 bit physical address space, this value should be ``(1ULL << 32)``.
@@ -486,22 +486,22 @@
If the platform port uses the IO storage framework, the following constants
must also be defined:
-- **#define : MAX\_IO\_DEVICES**
+- **#define : MAX_IO_DEVICES**
Defines the maximum number of registered IO devices. Attempting to register
more devices than this value using ``io_register_device()`` will fail with
-ENOMEM.
-- **#define : MAX\_IO\_HANDLES**
+- **#define : MAX_IO_HANDLES**
Defines the maximum number of open IO handles. Attempting to open more IO
entities than this value using ``io_open()`` will fail with -ENOMEM.
-- **#define : MAX\_IO\_BLOCK\_DEVICES**
+- **#define : MAX_IO_BLOCK_DEVICES**
Defines the maximum number of registered IO block devices. Attempting to
register more devices this value using ``io_dev_open()`` will fail
- with -ENOMEM. MAX\_IO\_BLOCK\_DEVICES should be less than MAX\_IO\_DEVICES.
+ with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES.
With this macro, multiple block devices could be supported at the same
time.
@@ -511,7 +511,7 @@
``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
required memory within the the per-cpu data to minimize wastage.
-- **#define : PLAT\_PCPU\_DATA\_SIZE**
+- **#define : PLAT_PCPU_DATA_SIZE**
Defines the memory (in bytes) to be reserved within the per-cpu data
structure for use by the platform layer.
@@ -519,39 +519,39 @@
The following constants are optional. They should be defined when the platform
memory layout implies some image overlaying like in Arm standard platforms.
-- **#define : BL31\_PROGBITS\_LIMIT**
+- **#define : BL31_PROGBITS_LIMIT**
Defines the maximum address in secure RAM that the BL31's progbits sections
can occupy.
-- **#define : TSP\_PROGBITS\_LIMIT**
+- **#define : TSP_PROGBITS_LIMIT**
Defines the maximum address that the TSP's progbits sections can occupy.
If the platform port uses the PL061 GPIO driver, the following constant may
optionally be defined:
-- **PLAT\_PL061\_MAX\_GPIOS**
+- **PLAT_PL061_MAX_GPIOS**
Maximum number of GPIOs required by the platform. This allows control how
much memory is allocated for PL061 GPIO controllers. The default value is
- #. $(eval $(call add\_define,PLAT\_PL061\_MAX\_GPIOS))
+ #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
If the platform port uses the partition driver, the following constant may
optionally be defined:
-- **PLAT\_PARTITION\_MAX\_ENTRIES**
+- **PLAT_PARTITION_MAX_ENTRIES**
Maximum number of partition entries required by the platform. This allows
control how much memory is allocated for partition entries. The default
value is 128.
`For example, define the build flag in platform.mk`_:
- PLAT\_PARTITION\_MAX\_ENTRIES := 12
- $(eval $(call add\_define,PLAT\_PARTITION\_MAX\_ENTRIES))
+ PLAT_PARTITION_MAX_ENTRIES := 12
+ $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
The following constant is optional. It should be defined to override the default
behaviour of the ``assert()`` function (for example, to save memory).
-- **PLAT\_LOG\_LEVEL\_ASSERT**
+- **PLAT_LOG_LEVEL_ASSERT**
If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``,
``assert()`` prints the name of the file, the line number and the asserted
expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file
@@ -562,27 +562,27 @@
If the platform port uses the Activity Monitor Unit, the following constants
may be defined:
-- **PLAT\_AMU\_GROUP1\_COUNTERS\_MASK**
+- **PLAT_AMU_GROUP1_COUNTERS_MASK**
This mask reflects the set of group counters that should be enabled. The
maximum number of group 1 counters supported by AMUv1 is 16 so the mask
can be at most 0xffff. If the platform does not define this mask, no group 1
counters are enabled. If the platform defines this mask, the following
constant needs to also be defined.
-- **PLAT\_AMU\_GROUP1\_NR\_COUNTERS**
+- **PLAT_AMU_GROUP1_NR_COUNTERS**
This value is used to allocate an array to save and restore the counters
specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend.
This value should be equal to the highest bit position set in the
mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16.
-File : plat\_macros.S [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+File : plat_macros.S [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Each platform must ensure a file of this name is in the system include path with
the following macro defined. In the Arm development platforms, this file is
found in ``plat/arm/board/<plat_name>/include/plat_macros.S``.
-- **Macro : plat\_crash\_print\_regs**
+- **Macro : plat_crash_print_regs**
This macro allows the crash reporting routine to print relevant platform
registers in case of an unhandled exception in BL31. This aids in debugging
@@ -614,8 +614,8 @@
The following functions need to be implemented by the platform port to enable
reset vector code to perform the above tasks.
-Function : plat\_get\_my\_entrypoint() [mandatory when PROGRAMMABLE\_RESET\_ADDRESS == 0]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -642,8 +642,8 @@
type of reset nor to query the warm reset entrypoint. Therefore, implementing
this function is not required on such platforms.
-Function : plat\_secondary\_cold\_boot\_setup() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -666,8 +666,8 @@
primary CPU will execute the cold boot code. Therefore, implementing this
function is not required on such platforms.
-Function : plat\_is\_my\_cpu\_primary() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -684,8 +684,8 @@
distinguish between primary and secondary CPUs and implementing this function is
not required.
-Function : platform\_mem\_init() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : platform_mem_init() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -695,8 +695,8 @@
This function is called before any access to data is made by the firmware, in
order to carry out any essential memory initialization.
-Function: plat\_get\_rotpk\_info()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function: plat_get_rotpk_info()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -745,8 +745,8 @@
verifying it against the platform value. This flag
must not be used in a deployed production environment.
-Function: plat\_get\_nv\_ctr()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function: plat_get_nv_ctr()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -758,13 +758,13 @@
cookie in the first argument may be used to select the counter in case the
platform provides more than one (for example, on platforms that use the default
TBBR CoT, the cookie will correspond to the OID values defined in
-TRUSTED\_FW\_NVCOUNTER\_OID or NON\_TRUSTED\_FW\_NVCOUNTER\_OID).
+TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID).
The function returns 0 on success. Any other value means the counter value could
not be retrieved from the platform.
-Function: plat\_set\_nv\_ctr()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function: plat_set_nv_ctr()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -773,14 +773,14 @@
This function is mandatory when Trusted Board Boot is enabled. It sets a new
counter value in the platform. The cookie in the first argument may be used to
-select the counter (as explained in plat\_get\_nv\_ctr()). The second argument is
+select the counter (as explained in plat_get_nv_ctr()). The second argument is
the updated counter value to be written to the NV counter.
The function returns 0 on success. Any other value means the counter value could
not be updated.
-Function: plat\_set\_nv\_ctr2()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function: plat_set_nv_ctr2()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -806,8 +806,8 @@
The following functions are mandatory functions which need to be implemented
by the platform port.
-Function : plat\_my\_core\_pos()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_my_core_pos()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -825,8 +825,8 @@
This function plays a crucial role in the power domain topology framework in
PSCI and details of this can be found in `Power Domain Topology Design`_.
-Function : plat\_core\_pos\_by\_mpidr()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_core_pos_by_mpidr()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -848,8 +848,8 @@
common platform-specific tasks. A platform may choose to override these
definitions.
-Function : plat\_set\_my\_stack()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_set_my_stack()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -863,11 +863,11 @@
constant ``PLATFORM_STACK_SIZE``.
Common implementations of this function for the UP and MP BL images are
-provided in `plat/common/aarch64/platform\_up\_stack.S`_ and
-`plat/common/aarch64/platform\_mp\_stack.S`_
+provided in `plat/common/aarch64/platform_up_stack.S`_ and
+`plat/common/aarch64/platform_mp_stack.S`_
-Function : plat\_get\_my\_stack()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_my_stack()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -881,11 +881,11 @@
constant ``PLATFORM_STACK_SIZE``.
Common implementations of this function for the UP and MP BL images are
-provided in `plat/common/aarch64/platform\_up\_stack.S`_ and
-`plat/common/aarch64/platform\_mp\_stack.S`_
+provided in `plat/common/aarch64/platform_up_stack.S`_ and
+`plat/common/aarch64/platform_mp_stack.S`_
-Function : plat\_report\_exception()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_report_exception()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -905,15 +905,15 @@
For AArch64, this function receives the exception type as its argument.
Possible values for exceptions types are listed in the
-`include/common/bl\_common.h`_ header file. Note that these constants are not
+`include/common/bl_common.h`_ header file. Note that these constants are not
related to any architectural exception code; they are just a TF-A convention.
For AArch32, this function receives the exception mode as its argument.
Possible values for exception modes are listed in the
`include/lib/aarch32/arch.h`_ header file.
-Function : plat\_reset\_handler()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_reset_handler()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -929,8 +929,8 @@
the default implementation, refer to the `Firmware Design`_ for general
guidelines.
-Function : plat\_disable\_acp()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_disable_acp()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -944,8 +944,8 @@
scratch registers. It should preserve the value in x18 register as it is used
by the caller to store the return address.
-Function : plat\_error\_handler()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_error_handler()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -968,8 +968,8 @@
The default implementation simply spins.
-Function : plat\_panic\_handler()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_panic_handler()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -984,8 +984,8 @@
Note: The address from where it was called is stored in x30 (Link Register).
The default implementation simply spins.
-Function : plat\_get\_bl\_image\_load\_info()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_bl_image_load_info()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -996,8 +996,8 @@
populated to load. This function is invoked in BL2 to load the
BL3xx images.
-Function : plat\_get\_next\_bl\_params()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_next_bl_params()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1009,8 +1009,8 @@
function is invoked in BL2 to pass this information to the next BL
image.
-Function : plat\_get\_stack\_protector\_canary()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_stack_protector_canary()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1018,7 +1018,7 @@
Return : u_register_t
This function returns a random value that is used to initialize the canary used
-when the stack protector is enabled with ENABLE\_STACK\_PROTECTOR. A predictable
+when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable
value will weaken the protection as the attacker could easily write the right
value as part of the attack most of the time. Therefore, it should return a
true random number.
@@ -1027,8 +1027,8 @@
a lower address than the stack bases. Failure to do so would allow an attacker
to overwrite the canary as part of the stack buffer overflow attack.
-Function : plat\_flush\_next\_bl\_params()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_flush_next_bl_params()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1039,8 +1039,8 @@
next image. This function is invoked in BL2 to flush this information
to the next BL image.
-Function : plat\_log\_get\_prefix()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_log_get_prefix()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1054,8 +1054,8 @@
the log output. The implementation should be robust to future changes that
increase the number of log levels.
-Function : plat\_get\_mbedtls\_heap()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_mbedtls_heap()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1116,8 +1116,8 @@
The following functions need to be implemented by the platform port to enable
BL1 to perform the above tasks.
-Function : bl1\_early\_platform\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_early_platform_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1138,8 +1138,8 @@
the CCI slave interface corresponding to the cluster that includes the
primary CPU.
-Function : bl1\_plat\_arch\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_arch_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1154,8 +1154,8 @@
This function helps fulfill requirement 2 above.
-Function : bl1\_platform\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_platform_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1167,15 +1167,15 @@
MMU and data cache have been enabled.
if support for multiple boot sources is required, it initializes the boot
-sequence used by plat\_try\_next\_boot\_source().
+sequence used by plat_try_next_boot_source().
In Arm standard platforms, this function initializes the storage abstraction
layer used to load the next bootloader image.
This function helps fulfill requirement 4 above.
-Function : bl1\_plat\_sec\_mem\_layout() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_sec_mem_layout() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1198,8 +1198,8 @@
This function helps fulfill requirements 4 and 5 above.
-Function : bl1\_plat\_prepare\_exit() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_prepare_exit() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1212,8 +1212,8 @@
control to the next image. It receives the address of the ``entry_point_info_t``
structure passed from BL2. This function runs with MMU disabled.
-Function : bl1\_plat\_set\_ep\_info() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_set_ep_info() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1224,8 +1224,8 @@
The default implementation just returns.
-Function : bl1\_plat\_get\_next\_image\_id() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_get_next_image_id() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1243,8 +1243,8 @@
platforms override this function to detect if firmware update is required, and
if so, return the first image in the firmware update process.
-Function : bl1\_plat\_get\_image\_desc() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_get_image_desc() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1259,8 +1259,8 @@
the firmware update images defined in the Trusted Board Boot Requirements
specification.
-Function : bl1\_plat\_handle\_pre\_image\_load() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_handle_pre_image_load() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1271,8 +1271,8 @@
corresponding to ``image_id``. This function is invoked in BL1, both in cold
boot and FWU code path, before loading the image.
-Function : bl1\_plat\_handle\_post\_image\_load() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_handle_post_image_load() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1289,8 +1289,8 @@
of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint
information to BL2.
-Function : bl1\_plat\_fwu\_done() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_fwu_done() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1304,8 +1304,8 @@
The default implementation spins forever.
-Function : bl1\_plat\_mem\_check() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_mem_check() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1342,8 +1342,8 @@
The following functions must be implemented by the platform port to enable BL2
to perform the above tasks.
-Function : bl2\_early\_platform\_setup2() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_early_platform_setup2() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1367,11 +1367,11 @@
family of functions in BL2.
- Initializes the storage abstraction layer used to load further bootloader
- images. It is necessary to do this early on platforms with a SCP\_BL2 image,
- since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded.
+ images. It is necessary to do this early on platforms with a SCP_BL2 image,
+ since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
-Function : bl2\_plat\_arch\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_plat_arch_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1386,8 +1386,8 @@
On Arm standard platforms, this function enables the MMU.
-Function : bl2\_platform\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_platform_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1405,8 +1405,8 @@
configuration of the TrustZone controller to allow non-secure masters access
to most of DRAM. Part of DRAM is reserved for secure world use.
-Function : bl2\_plat\_handle\_pre\_image\_load() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_plat_handle_pre_image_load() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1417,8 +1417,8 @@
for given ``image_id``. This function is currently invoked in BL2 before
loading each image.
-Function : bl2\_plat\_handle\_post\_image\_load() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_plat_handle_post_image_load() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1429,8 +1429,8 @@
for given ``image_id``. This function is currently invoked in BL2 after
loading each image.
-Function : bl2\_plat\_preload\_setup [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_plat_preload_setup [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1439,12 +1439,12 @@
This optional function performs any BL2 platform initialization
required before image loading, that is not done later in
-bl2\_platform\_setup(). Specifically, if support for multiple
+bl2_platform_setup(). Specifically, if support for multiple
boot sources is required, it initializes the boot sequence used by
-plat\_try\_next\_boot\_source().
+plat_try_next_boot_source().
-Function : plat\_try\_next\_boot\_source() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_try_next_boot_source() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1468,14 +1468,14 @@
Design`_ for more information.
All mandatory functions of BL2 must be implemented, except the functions
-bl2\_early\_platform\_setup and bl2\_el3\_plat\_arch\_setup, because
-their work is done now by bl2\_el3\_early\_platform\_setup and
-bl2\_el3\_plat\_arch\_setup. These functions should generally implement
-the bl1\_plat\_xxx() and bl2\_plat\_xxx() functionality combined.
+bl2_early_platform_setup and bl2_el3_plat_arch_setup, because
+their work is done now by bl2_el3_early_platform_setup and
+bl2_el3_plat_arch_setup. These functions should generally implement
+the bl1_plat_xxx() and bl2_plat_xxx() functionality combined.
-Function : bl2\_el3\_early\_platform\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_el3_early_platform_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1492,13 +1492,13 @@
family of functions in BL2.
- Initializes the storage abstraction layer used to load further bootloader
- images. It is necessary to do this early on platforms with a SCP\_BL2 image,
- since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded.
+ images. It is necessary to do this early on platforms with a SCP_BL2 image,
+ since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
- Initializes the private variables that define the memory layout used.
-Function : bl2\_el3\_plat\_arch\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_el3_plat_arch_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1513,8 +1513,8 @@
On Arm standard platforms, this function enables the MMU.
-Function : bl2\_el3\_plat\_prepare\_exit() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_el3_plat_prepare_exit() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1533,10 +1533,10 @@
process and is executed only by the primary CPU. BL1 passes control to BL2U at
``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for:
-#. (Optional) Transferring the optional SCP\_BL2U binary image from AP secure
- memory to SCP RAM. BL2U uses the SCP\_BL2U ``image_info`` passed by BL1.
- ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP\_BL2U
- should be copied from. Subsequent handling of the SCP\_BL2U image is
+#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure
+ memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1.
+ ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U
+ should be copied from. Subsequent handling of the SCP_BL2U image is
implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function.
If ``SCP_BL2U_BASE`` is not defined then this step is not performed.
@@ -1547,8 +1547,8 @@
The following functions must be implemented by the platform port to enable
BL2U to perform the tasks mentioned above.
-Function : bl2u\_early\_platform\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2u_early_platform_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1563,11 +1563,11 @@
private storage as the original memory may be subsequently overwritten by BL2U.
On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure,
-to extract SCP\_BL2U image information, which is then copied into a private
+to extract SCP_BL2U image information, which is then copied into a private
variable.
-Function : bl2u\_plat\_arch\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2u_plat_arch_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1581,8 +1581,8 @@
that varies across platforms, for example enabling the MMU (since the memory
map differs across platforms).
-Function : bl2u\_platform\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2u_platform_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1600,8 +1600,8 @@
configuration of the TrustZone controller to allow non-secure masters access
to most of DRAM. Part of DRAM is reserved for secure world use.
-Function : bl2u\_plat\_handle\_scp\_bl2u() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2u_plat_handle_scp_bl2u() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1614,7 +1614,7 @@
Application Processor (AP) for BL2U execution to continue.
This function returns 0 on success, a negative error code otherwise.
-This function is included if SCP\_BL2U\_BASE is defined.
+This function is included if SCP_BL2U_BASE is defined.
Boot Loader Stage 3-1 (BL31)
----------------------------
@@ -1650,8 +1650,8 @@
The following functions must be implemented by the platform port to enable BL31
to perform the above tasks.
-Function : bl31\_early\_platform\_setup2() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl31_early_platform_setup2() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1684,8 +1684,8 @@
CCI slave interface corresponding to the cluster that includes the primary
CPU.
-Function : bl31\_plat\_arch\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl31_plat_arch_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1700,7 +1700,7 @@
On Arm standard platforms, this function enables the MMU.
-Function : bl31\_platform\_setup() [mandatory]
+Function : bl31_platform_setup() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1742,8 +1742,8 @@
In particular, initialise the locks that prevent concurrent accesses to the
power controller device.
-Function : bl31\_plat\_runtime\_setup() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl31_plat_runtime_setup() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1755,8 +1755,8 @@
implementation of this function will invoke ``console_switch_state()`` to switch
console output to consoles marked for use in the ``runtime`` state.
-Function : bl31\_plat\_get\_next\_image\_ep\_info() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl31_plat_get_next_image_ep_info() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1792,8 +1792,8 @@
On DynamIQ systems, this function must not use stack while enabling MMU, which
is how the function in xlat table library version 2 is implemented.
-Function : plat\_get\_syscnt\_freq2() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_syscnt_freq2() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1806,8 +1806,8 @@
of the system counter, which is retrieved from the first entry in the frequency
modes table.
-#define : PLAT\_PERCPU\_BAKERY\_LOCK\_SIZE [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in
bytes) aligned to the cache line boundary that should be allocated per-cpu to
@@ -1929,8 +1929,8 @@
The following functions form part of platform port of PSCI functionality.
-Function : plat\_psci\_stat\_accounting\_start() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_psci_stat_accounting_start() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1947,8 +1947,8 @@
statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
default implementation will use PMF to capture timestamps.
-Function : plat\_psci\_stat\_accounting\_stop() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_psci_stat_accounting_stop() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1965,8 +1965,8 @@
statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
default implementation will use PMF to capture timestamps.
-Function : plat\_psci\_stat\_get\_residency() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_psci_stat_get_residency() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1985,8 +1985,8 @@
CPU in the power domain to suspend and may be needed to calculate the residency
for that power domain.
-Function : plat\_get\_target\_pwr\_state() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_target_pwr_state() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2010,8 +2010,8 @@
coordinated target local power state for a power domain will be the minimum
of the requested local power state values.
-Function : plat\_get\_power\_domain\_tree\_desc() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_power_domain_tree_desc() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2023,13 +2023,13 @@
described in `Power Domain Topology Design`_. The BL31 PSCI initialization code
requires this array to be described by the platform, either statically or
dynamically, to initialize the power domain topology tree. In case the array
-is populated dynamically, then plat\_core\_pos\_by\_mpidr() and
-plat\_my\_core\_pos() should also be implemented suitably so that the topology
+is populated dynamically, then plat_core_pos_by_mpidr() and
+plat_my_core_pos() should also be implemented suitably so that the topology
tree description matches the CPU indices returned by these APIs. These APIs
together form the platform interface for the PSCI topology framework.
-Function : plat\_setup\_psci\_ops() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_setup_psci_ops() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2048,15 +2048,15 @@
A description of each member of this structure is given below. Please refer to
the Arm FVP specific implementation of these handlers in
-`plat/arm/board/fvp/fvp\_pm.c`_ as an example. For each PSCI function that the
+`plat/arm/board/fvp/fvp_pm.c`_ as an example. For each PSCI function that the
platform wants to support, the associated operation or operations in this
structure must be provided and implemented (Refer section 4 of
`Firmware Design`_ for the PSCI API supported in TF-A). To disable a PSCI
function in a platform port, the operation should be removed from this
structure instead of providing an empty implementation.
-plat\_psci\_ops.cpu\_standby()
-..............................
+plat_psci_ops.cpu_standby()
+...........................
Perform the platform-specific actions to enter the standby state for a cpu
indicated by the passed argument. This provides a fast path for CPU standby
@@ -2068,15 +2068,15 @@
issuing a wfi instruction) and ensure that it can be woken up from that
state by a normal interrupt. The generic code expects the handler to succeed.
-plat\_psci\_ops.pwr\_domain\_on()
-.................................
+plat_psci_ops.pwr_domain_on()
+.............................
Perform the platform specific actions to power on a CPU, specified
by the ``MPIDR`` (first argument). The generic code expects the platform to
-return PSCI\_E\_SUCCESS on success or PSCI\_E\_INTERN\_FAIL for any failure.
+return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure.
-plat\_psci\_ops.pwr\_domain\_off()
-..................................
+plat_psci_ops.pwr_domain_off()
+..............................
Perform the platform specific actions to prepare to power off the calling CPU
and its higher parent power domain levels as indicated by the ``target_state``
@@ -2092,8 +2092,8 @@
for the higher power domain levels depending on the result of state
coordination. The generic code expects the handler to succeed.
-plat\_psci\_ops.pwr\_domain\_suspend\_pwrdown\_early() [optional]
-.................................................................
+plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]
+...........................................................
This optional function may be used as a performance optimization to replace
or complement pwr_domain_suspend() on some platforms. Its calling semantics
@@ -2109,8 +2109,8 @@
= 1, data caches remain enabled throughout, and so there is no advantage to
moving platform specific actions to this function.
-plat\_psci\_ops.pwr\_domain\_suspend()
-......................................
+plat_psci_ops.pwr_domain_suspend()
+..................................
Perform the platform specific actions to prepare to suspend the calling
CPU and its higher parent power domain levels as indicated by the
@@ -2150,8 +2150,8 @@
data, for example in DRAM. The Distributor can then be powered down using an
implementation-defined sequence.
-plat\_psci\_ops.pwr\_domain\_pwr\_down\_wfi()
-.............................................
+plat_psci_ops.pwr_domain_pwr_down_wfi()
+.......................................
This is an optional function and, if implemented, is expected to perform
platform specific actions including the ``wfi`` invocation which allows the
@@ -2167,8 +2167,8 @@
If this function is not implemented by the platform, PSCI generic
implementation invokes ``psci_power_down_wfi()`` for power down.
-plat\_psci\_ops.pwr\_domain\_on\_finish()
-.........................................
+plat_psci_ops.pwr_domain_on_finish()
+....................................
This function is called by the PSCI implementation after the calling CPU is
powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
@@ -2181,8 +2181,8 @@
above the CPU might require initialization due to having previously been in
low power states. The generic code expects the handler to succeed.
-plat\_psci\_ops.pwr\_domain\_suspend\_finish()
-..............................................
+plat_psci_ops.pwr_domain_suspend_finish()
+.........................................
This function is called by the PSCI implementation after the calling CPU is
powered on and released from reset in response to an asynchronous wakeup
@@ -2199,41 +2199,41 @@
suspend, their context must be restored in this function in the reverse order
to how they were saved during suspend sequence.
-plat\_psci\_ops.system\_off()
-.............................
+plat_psci_ops.system_off()
+..........................
This function is called by PSCI implementation in response to a ``SYSTEM_OFF``
call. It performs the platform-specific system poweroff sequence after
notifying the Secure Payload Dispatcher.
-plat\_psci\_ops.system\_reset()
-...............................
+plat_psci_ops.system_reset()
+............................
This function is called by PSCI implementation in response to a ``SYSTEM_RESET``
call. It performs the platform-specific system reset sequence after
notifying the Secure Payload Dispatcher.
-plat\_psci\_ops.validate\_power\_state()
-........................................
+plat_psci_ops.validate_power_state()
+....................................
This function is called by the PSCI implementation during the ``CPU_SUSPEND``
call to validate the ``power_state`` parameter of the PSCI API and if valid,
populate it in ``req_state`` (second argument) array as power domain level
specific local states. If the ``power_state`` is invalid, the platform must
-return PSCI\_E\_INVALID\_PARAMS as error, which is propagated back to the
+return PSCI_E_INVALID_PARAMS as error, which is propagated back to the
normal world PSCI client.
-plat\_psci\_ops.validate\_ns\_entrypoint()
-..........................................
+plat_psci_ops.validate_ns_entrypoint()
+......................................
This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point``
parameter passed by the normal world. If the ``entry_point`` is invalid,
-the platform must return PSCI\_E\_INVALID\_ADDRESS as error, which is
+the platform must return PSCI_E_INVALID_ADDRESS as error, which is
propagated back to the normal world PSCI client.
-plat\_psci\_ops.get\_sys\_suspend\_power\_state()
-.................................................
+plat_psci_ops.get_sys_suspend_power_state()
+...........................................
This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
call to get the ``req_state`` parameter from platform which encodes the power
@@ -2242,8 +2242,8 @@
``pwr_domain_suspend()`` will be invoked with the coordinated target state to
enter system suspend.
-plat\_psci\_ops.get\_pwr\_lvl\_state\_idx()
-...........................................
+plat_psci_ops.get_pwr_lvl_state_idx()
+.....................................
This is an optional function and, if implemented, is invoked by the PSCI
implementation to convert the ``local_state`` (first argument) at a specified
@@ -2253,8 +2253,8 @@
``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these
local power states.
-plat\_psci\_ops.translate\_power\_state\_by\_mpidr()
-....................................................
+plat_psci_ops.translate_power_state_by_mpidr()
+..............................................
This is an optional function and, if implemented, verifies the ``power_state``
(second argument) parameter of the PSCI API corresponding to a target power
@@ -2265,16 +2265,16 @@
is similar to the ``validate_power_state`` function described above and is
envisaged to be used in case the validity of ``power_state`` depend on the
targeted power domain. If the ``power_state`` is invalid for the targeted power
-domain, the platform must return PSCI\_E\_INVALID\_PARAMS as error. If this
+domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this
function is not implemented, then the generic implementation relies on
``validate_power_state`` function to translate the ``power_state``.
This function can also be used in case the platform wants to support local
-power state encoding for ``power_state`` parameter of PSCI\_STAT\_COUNT/RESIDENCY
+power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY
APIs as described in Section 5.18 of `PSCI`_.
-plat\_psci\_ops.get\_node\_hw\_state()
-......................................
+plat_psci_ops.get_node_hw_state()
+.................................
This is an optional function. If implemented this function is intended to return
the power state of a node (identified by the first parameter, the ``MPIDR``) in
@@ -2288,8 +2288,8 @@
Implementations are not expected to handle ``power_levels`` greater than
``PLAT_MAX_PWR_LVL``.
-plat\_psci\_ops.system\_reset2()
-................................
+plat_psci_ops.system_reset2()
+.............................
This is an optional function. If implemented this function is
called during the ``SYSTEM_RESET2`` call to perform a reset
@@ -2301,8 +2301,8 @@
and vendor reset can return other PSCI error codes as defined
in `PSCI`_. On success this function will not return.
-plat\_psci\_ops.write\_mem\_protect()
-....................................
+plat_psci_ops.write_mem_protect()
+.................................
This is an optional function. If implemented it enables or disables the
``MEM_PROTECT`` functionality based on the value of ``val``.
@@ -2310,16 +2310,16 @@
disables it. Upon encountering failures it must return a negative value
and on success it must return 0.
-plat\_psci\_ops.read\_mem\_protect()
-.....................................
+plat_psci_ops.read_mem_protect()
+................................
This is an optional function. If implemented it returns the current
state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering
failures it must return a negative value and on success it must
return 0.
-plat\_psci\_ops.mem\_protect\_chk()
-...................................
+plat_psci_ops.mem_protect_chk()
+...............................
This is an optional function. If implemented it checks if a memory
region defined by a base address ``base`` and with a size of ``length``
@@ -2348,8 +2348,8 @@
.. __: platform-interrupt-controller-API.rst
-Function : plat\_interrupt\_type\_to\_line() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_interrupt_type_to_line() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2384,8 +2384,8 @@
- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2
context.
-Function : plat\_ic\_get\_pending\_interrupt\_type() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_ic_get_pending_interrupt_type() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2417,8 +2417,8 @@
#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type.
#. All other interrupt id's are reported as EL3 interrupt.
-Function : plat\_ic\_get\_pending\_interrupt\_id() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_ic_get_pending_interrupt_id() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2456,11 +2456,11 @@
When the API invoked from S-EL1 for GICv3 systems, the id read from system
register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
-Register*, is returned if is not equal to GIC\_SPURIOUS\_INTERRUPT (1023) else
+Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else
``INTR_ID_UNAVAILABLE`` is returned.
-Function : plat\_ic\_acknowledge\_interrupt() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_ic_acknowledge_interrupt() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2491,8 +2491,8 @@
The TSP uses this API to start processing of the secure physical timer
interrupt.
-Function : plat\_ic\_end\_of\_interrupt() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_ic_end_of_interrupt() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2513,8 +2513,8 @@
The TSP uses this API to finish processing of the secure physical timer
interrupt.
-Function : plat\_ic\_get\_interrupt\_type() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_ic_get_interrupt_type() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2564,8 +2564,8 @@
that are designed to be used by these functions. See Arm platforms (like juno)
for an example of this.
-Function : plat\_crash\_console\_init [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_crash_console_init [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2576,8 +2576,8 @@
console. It must only use the general purpose registers x0 through x7 to do the
initialization and returns 1 on success.
-Function : plat\_crash\_console\_putc [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_crash_console_putc [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2589,8 +2589,8 @@
x2 to do its work. The parameter and the return value are in general purpose
register x0.
-Function : plat\_crash\_console\_flush [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_crash_console_flush [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2710,7 +2710,7 @@
need to be defined in the platform makefile which will get included by the
build system.
-- **NEED\_BL33**
+- **NEED_BL33**
By default, this flag is defined ``yes`` by the build system and ``BL33``
build option should be supplied as a build option. The platform has the
option of excluding the BL33 image in the ``fip`` image by defining this flag
@@ -2770,7 +2770,7 @@
The current implementation only allows for known images to be loaded by the
firmware. These images are specified by using their identifiers, as defined in
-[include/plat/common/platform\_def.h] (or a separate header file included from
+[include/plat/common/platform_def.h] (or a separate header file included from
there). The platform layer (``plat_get_image_source()``) then returns a reference
to a device and a driver-specific ``spec`` which will be understood by the driver
to allow access to the image data.
@@ -2791,19 +2791,19 @@
*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.*
.. _include/plat/common/platform.h: ../include/plat/common/platform.h
-.. _include/plat/arm/common/plat\_arm.h: ../include/plat/arm/common/plat_arm.h%5D
+.. _include/plat/arm/common/plat_arm.h: ../include/plat/arm/common/plat_arm.h%5D
.. _User Guide: user-guide.rst
-.. _include/plat/common/common\_def.h: ../include/plat/common/common_def.h
-.. _include/plat/arm/common/arm\_def.h: ../include/plat/arm/common/arm_def.h
-.. _plat/common/aarch64/platform\_mp\_stack.S: ../plat/common/aarch64/platform_mp_stack.S
-.. _plat/common/aarch64/platform\_up\_stack.S: ../plat/common/aarch64/platform_up_stack.S
+.. _include/plat/common/common_def.h: ../include/plat/common/common_def.h
+.. _include/plat/arm/common/arm_def.h: ../include/plat/arm/common/arm_def.h
+.. _plat/common/aarch64/platform_mp_stack.S: ../plat/common/aarch64/platform_mp_stack.S
+.. _plat/common/aarch64/platform_up_stack.S: ../plat/common/aarch64/platform_up_stack.S
.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160
.. _Power Domain Topology Design: psci-pd-tree.rst
-.. _include/common/bl\_common.h: ../include/common/bl_common.h
+.. _include/common/bl_common.h: ../include/common/bl_common.h
.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h
.. _Firmware Design: firmware-design.rst
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
-.. _plat/arm/board/fvp/fvp\_pm.c: ../plat/arm/board/fvp/fvp_pm.c
+.. _plat/arm/board/fvp/fvp_pm.c: ../plat/arm/board/fvp/fvp_pm.c
.. _Platform compatibility policy: ./platform-compatibility-policy.rst
.. _IMF Design Guide: interrupt-framework-design.rst
.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html