blob: 3d3b2e3e34bd57833feef5a7d61e905e3014ca55 [file] [log] [blame]
Paul Beesleyfc9ee362019-03-07 15:47:15 +00001Porting Guide
2=============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Douglas Raillardd7c21b72017-06-28 15:23:03 +01004Introduction
5------------
6
Dan Handley610e7e12018-03-01 18:44:00 +00007Porting Trusted Firmware-A (TF-A) to a new platform involves making some
Douglas Raillardd7c21b72017-06-28 15:23:03 +01008mandatory and optional modifications for both the cold and warm boot paths.
9Modifications consist of:
10
11- Implementing a platform-specific function or variable,
12- Setting up the execution context in a certain way, or
13- Defining certain constants (for example #defines).
14
15The platform-specific functions and variables are declared in
Paul Beesleyf8640672019-04-12 14:19:42 +010016``include/plat/common/platform.h``. The firmware provides a default
17implementation of variables and functions to fulfill the optional requirements.
18These implementations are all weakly defined; they are provided to ease the
19porting effort. Each platform port can override them with its own implementation
20if the default implementation is inadequate.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
Douglas Raillardd7c21b72017-06-28 15:23:03 +010022Some modifications are common to all Boot Loader (BL) stages. Section 2
23discusses these in detail. The subsequent sections discuss the remaining
24modifications for each BL stage in detail.
25
Paul Beesleyf8640672019-04-12 14:19:42 +010026Please refer to the :ref:`Platform Compatibility Policy` for the policy
27regarding compatibility and deprecation of these porting interfaces.
Soby Mathew02bdbb92018-09-26 11:17:23 +010028
Antonio Nino Diaz645feb42019-02-13 14:07:38 +000029Only Arm development platforms (such as FVP and Juno) may use the
30functions/definitions in ``include/plat/arm/common/`` and the corresponding
31source files in ``plat/arm/common/``. This is done so that there are no
32dependencies between platforms maintained by different people/companies. If you
33want to use any of the functionality present in ``plat/arm`` files, please
34create a pull request that moves the code to ``plat/common`` so that it can be
35discussed.
36
Douglas Raillardd7c21b72017-06-28 15:23:03 +010037Common modifications
38--------------------
39
40This section covers the modifications that should be made by the platform for
41each BL stage to correctly port the firmware stack. They are categorized as
42either mandatory or optional.
43
44Common mandatory modifications
45------------------------------
46
47A platform port must enable the Memory Management Unit (MMU) as well as the
48instruction and data caches for each BL stage. Setting up the translation
49tables is the responsibility of the platform port because memory maps differ
50across platforms. A memory translation library (see ``lib/xlat_tables/``) is
Sandrine Bailleux1861b7a2017-07-20 16:11:01 +010051provided to help in this setup.
52
53Note that although this library supports non-identity mappings, this is intended
54only for re-mapping peripheral physical addresses and allows platforms with high
55I/O addresses to reduce their virtual address space. All other addresses
56corresponding to code and data must currently use an identity mapping.
57
Dan Handley610e7e12018-03-01 18:44:00 +000058Also, the only translation granule size supported in TF-A is 4KB, as various
59parts of the code assume that is the case. It is not possible to switch to
6016 KB or 64 KB granule sizes at the moment.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010061
Dan Handley610e7e12018-03-01 18:44:00 +000062In Arm standard platforms, each BL stage configures the MMU in the
Douglas Raillardd7c21b72017-06-28 15:23:03 +010063platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses
64an identity mapping for all addresses.
65
66If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a
67block of identity mapped secure memory with Device-nGnRE attributes aligned to
68page boundary (4K) for each BL stage. All sections which allocate coherent
69memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a
70section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its
71possible for the firmware to place variables in it using the following C code
72directive:
73
74::
75
76 __section("bakery_lock")
77
78Or alternatively the following assembler code directive:
79
80::
81
82 .section bakery_lock
83
84The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are
85used to allocate any data structures that are accessed both when a CPU is
86executing with its MMU and caches enabled, and when it's running with its MMU
87and caches disabled. Examples are given below.
88
89The following variables, functions and constants must be defined by the platform
90for the firmware to work correctly.
91
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +010092File : platform_def.h [mandatory]
93~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +010094
95Each platform must ensure that a header file of this name is in the system
Antonio Nino Diaz50a4d1a2019-02-01 12:22:22 +000096include path with the following constants defined. This will require updating
97the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010098
Paul Beesleyf8640672019-04-12 14:19:42 +010099Platform ports may optionally use the file ``include/plat/common/common_def.h``,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100100which provides typical values for some of the constants below. These values are
101likely to be suitable for all platform ports.
102
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100103- **#define : PLATFORM_LINKER_FORMAT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100104
105 Defines the linker format used by the platform, for example
106 ``elf64-littleaarch64``.
107
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100108- **#define : PLATFORM_LINKER_ARCH**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100109
110 Defines the processor architecture for the linker by the platform, for
111 example ``aarch64``.
112
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100113- **#define : PLATFORM_STACK_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100114
115 Defines the normal stack memory available to each CPU. This constant is used
Paul Beesleyf8640672019-04-12 14:19:42 +0100116 by ``plat/common/aarch64/platform_mp_stack.S`` and
117 ``plat/common/aarch64/platform_up_stack.S``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100118
David Horstmann051fd6d2020-11-12 15:19:04 +0000119- **#define : CACHE_WRITEBACK_GRANULE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100120
121 Defines the size in bits of the largest cache line across all the cache
122 levels in the platform.
123
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100124- **#define : FIRMWARE_WELCOME_STR**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100125
126 Defines the character string printed by BL1 upon entry into the ``bl1_main()``
127 function.
128
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100129- **#define : PLATFORM_CORE_COUNT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100130
131 Defines the total number of CPUs implemented by the platform across all
132 clusters in the system.
133
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100134- **#define : PLAT_NUM_PWR_DOMAINS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100135
136 Defines the total number of nodes in the power domain topology
137 tree at all the power domain levels used by the platform.
138 This macro is used by the PSCI implementation to allocate
139 data structures to represent power domain topology.
140
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100141- **#define : PLAT_MAX_PWR_LVL**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100142
143 Defines the maximum power domain level that the power management operations
144 should apply to. More often, but not always, the power domain level
145 corresponds to affinity level. This macro allows the PSCI implementation
146 to know the highest power domain level that it should consider for power
147 management operations in the system that the platform implements. For
148 example, the Base AEM FVP implements two clusters with a configurable
149 number of CPUs and it reports the maximum power domain level as 1.
150
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100151- **#define : PLAT_MAX_OFF_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100152
153 Defines the local power state corresponding to the deepest power down
154 possible at every power domain level in the platform. The local power
155 states for each level may be sparsely allocated between 0 and this value
156 with 0 being reserved for the RUN state. The PSCI implementation uses this
157 value to initialize the local power states of the power domain nodes and
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100158 to specify the requested power state for a PSCI_CPU_OFF call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100159
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100160- **#define : PLAT_MAX_RET_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100161
162 Defines the local power state corresponding to the deepest retention state
163 possible at every power domain level in the platform. This macro should be
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100164 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100165 PSCI implementation to distinguish between retention and power down local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100166 power states within PSCI_CPU_SUSPEND call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100167
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100168- **#define : PLAT_MAX_PWR_LVL_STATES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100169
170 Defines the maximum number of local power states per power domain level
171 that the platform supports. The default value of this macro is 2 since
172 most platforms just support a maximum of two local power states at each
173 power domain level (power-down and retention). If the platform needs to
174 account for more local power states, then it must redefine this macro.
175
176 Currently, this macro is used by the Generic PSCI implementation to size
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100177 the array used for PSCI_STAT_COUNT/RESIDENCY accounting.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100178
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100179- **#define : BL1_RO_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100180
181 Defines the base address in secure ROM where BL1 originally lives. Must be
182 aligned on a page-size boundary.
183
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100184- **#define : BL1_RO_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100185
186 Defines the maximum address in secure ROM that BL1's actual content (i.e.
187 excluding any data section allocated at runtime) can occupy.
188
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100189- **#define : BL1_RW_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100190
191 Defines the base address in secure RAM where BL1's read-write data will live
192 at runtime. Must be aligned on a page-size boundary.
193
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100194- **#define : BL1_RW_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100195
196 Defines the maximum address in secure RAM that BL1's read-write data can
197 occupy at runtime.
198
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100199- **#define : BL2_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100200
201 Defines the base address in secure RAM where BL1 loads the BL2 binary image.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000202 Must be aligned on a page-size boundary. This constant is not applicable
203 when BL2_IN_XIP_MEM is set to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100204
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100205- **#define : BL2_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100206
207 Defines the maximum address in secure RAM that the BL2 image can occupy.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000208 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'.
209
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100210- **#define : BL2_RO_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000211
212 Defines the base address in secure XIP memory where BL2 RO section originally
213 lives. Must be aligned on a page-size boundary. This constant is only needed
214 when BL2_IN_XIP_MEM is set to '1'.
215
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100216- **#define : BL2_RO_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000217
218 Defines the maximum address in secure XIP memory that BL2's actual content
219 (i.e. excluding any data section allocated at runtime) can occupy. This
220 constant is only needed when BL2_IN_XIP_MEM is set to '1'.
221
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100222- **#define : BL2_RW_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000223
224 Defines the base address in secure RAM where BL2's read-write data will live
225 at runtime. Must be aligned on a page-size boundary. This constant is only
226 needed when BL2_IN_XIP_MEM is set to '1'.
227
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100228- **#define : BL2_RW_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000229
230 Defines the maximum address in secure RAM that BL2's read-write data can
231 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set
232 to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100233
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100234- **#define : BL31_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100235
236 Defines the base address in secure RAM where BL2 loads the BL31 binary
237 image. Must be aligned on a page-size boundary.
238
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100239- **#define : BL31_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100240
241 Defines the maximum address in secure RAM that the BL31 image can occupy.
242
243For every image, the platform must define individual identifiers that will be
244used by BL1 or BL2 to load the corresponding image into memory from non-volatile
245storage. For the sake of performance, integer numbers will be used as
246identifiers. The platform will use those identifiers to return the relevant
247information about the image to be loaded (file handler, load address,
248authentication information, etc.). The following image identifiers are
249mandatory:
250
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100251- **#define : BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100252
253 BL2 image identifier, used by BL1 to load BL2.
254
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100255- **#define : BL31_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100256
257 BL31 image identifier, used by BL2 to load BL31.
258
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100259- **#define : BL33_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100260
261 BL33 image identifier, used by BL2 to load BL33.
262
263If Trusted Board Boot is enabled, the following certificate identifiers must
264also be defined:
265
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100266- **#define : TRUSTED_BOOT_FW_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100267
268 BL2 content certificate identifier, used by BL1 to load the BL2 content
269 certificate.
270
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100271- **#define : TRUSTED_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100272
273 Trusted key certificate identifier, used by BL2 to load the trusted key
274 certificate.
275
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100276- **#define : SOC_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100277
278 BL31 key certificate identifier, used by BL2 to load the BL31 key
279 certificate.
280
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100281- **#define : SOC_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100282
283 BL31 content certificate identifier, used by BL2 to load the BL31 content
284 certificate.
285
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100286- **#define : NON_TRUSTED_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100287
288 BL33 key certificate identifier, used by BL2 to load the BL33 key
289 certificate.
290
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100291- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100292
293 BL33 content certificate identifier, used by BL2 to load the BL33 content
294 certificate.
295
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100296- **#define : FWU_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100297
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100298 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100299 FWU content certificate.
300
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100301- **#define : PLAT_CRYPTOCELL_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100302
Dan Handley610e7e12018-03-01 18:44:00 +0000303 This defines the base address of Arm® TrustZone® CryptoCell and must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100304 defined if CryptoCell crypto driver is used for Trusted Board Boot. For
Dan Handley610e7e12018-03-01 18:44:00 +0000305 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100306 set.
307
308If the AP Firmware Updater Configuration image, BL2U is used, the following
309must also be defined:
310
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100311- **#define : BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100312
313 Defines the base address in secure memory where BL1 copies the BL2U binary
314 image. Must be aligned on a page-size boundary.
315
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100316- **#define : BL2U_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100317
318 Defines the maximum address in secure memory that the BL2U image can occupy.
319
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100320- **#define : BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100321
322 BL2U image identifier, used by BL1 to fetch an image descriptor
323 corresponding to BL2U.
324
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100325If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100326must also be defined:
327
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100328- **#define : SCP_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100329
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100330 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor
331 corresponding to SCP_BL2U.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000332
333 .. note::
334 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100335
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100336If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100337also be defined:
338
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100339- **#define : NS_BL1U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100340
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100341 Defines the base address in non-secure ROM where NS_BL1U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100342 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000343
344 .. note::
345 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100346
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100347- **#define : NS_BL1U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100348
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100349 NS_BL1U image identifier, used by BL1 to fetch an image descriptor
350 corresponding to NS_BL1U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100351
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100352If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100353be defined:
354
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100355- **#define : NS_BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100356
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100357 Defines the base address in non-secure memory where NS_BL2U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100358 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000359
360 .. note::
361 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100362
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100363- **#define : NS_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100364
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100365 NS_BL2U image identifier, used by BL1 to fetch an image descriptor
366 corresponding to NS_BL2U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100367
368For the the Firmware update capability of TRUSTED BOARD BOOT, the following
369macros may also be defined:
370
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100371- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100372
373 Total number of images that can be loaded simultaneously. If the platform
374 doesn't specify any value, it defaults to 10.
375
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100376If a SCP_BL2 image is supported by the platform, the following constants must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100377also be defined:
378
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100379- **#define : SCP_BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100380
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100381 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000382 from platform storage before being transferred to the SCP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100383
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100384- **#define : SCP_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100385
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100386 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100387 certificate (mandatory when Trusted Board Boot is enabled).
388
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100389- **#define : SCP_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100390
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100391 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100392 content certificate (mandatory when Trusted Board Boot is enabled).
393
394If a BL32 image is supported by the platform, the following constants must
395also be defined:
396
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100397- **#define : BL32_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100398
399 BL32 image identifier, used by BL2 to load BL32.
400
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100401- **#define : TRUSTED_OS_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100402
403 BL32 key certificate identifier, used by BL2 to load the BL32 key
404 certificate (mandatory when Trusted Board Boot is enabled).
405
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100406- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100407
408 BL32 content certificate identifier, used by BL2 to load the BL32 content
409 certificate (mandatory when Trusted Board Boot is enabled).
410
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100411- **#define : BL32_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100412
413 Defines the base address in secure memory where BL2 loads the BL32 binary
414 image. Must be aligned on a page-size boundary.
415
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100416- **#define : BL32_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100417
418 Defines the maximum address that the BL32 image can occupy.
419
420If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the
421platform, the following constants must also be defined:
422
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100423- **#define : TSP_SEC_MEM_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100424
425 Defines the base address of the secure memory used by the TSP image on the
426 platform. This must be at the same address or below ``BL32_BASE``.
427
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100428- **#define : TSP_SEC_MEM_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100429
430 Defines the size of the secure memory used by the BL32 image on the
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000431 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully
432 accommodate the memory required by the BL32 image, defined by ``BL32_BASE``
433 and ``BL32_LIMIT``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100434
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100435- **#define : TSP_IRQ_SEC_PHY_TIMER**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100436
437 Defines the ID of the secure physical generic timer interrupt used by the
438 TSP's interrupt handling code.
439
440If the platform port uses the translation table library code, the following
441constants must also be defined:
442
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100443- **#define : PLAT_XLAT_TABLES_DYNAMIC**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100444
445 Optional flag that can be set per-image to enable the dynamic allocation of
446 regions even when the MMU is enabled. If not defined, only static
447 functionality will be available, if defined and set to 1 it will also
448 include the dynamic functionality.
449
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100450- **#define : MAX_XLAT_TABLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100451
452 Defines the maximum number of translation tables that are allocated by the
453 translation table library code. To minimize the amount of runtime memory
454 used, choose the smallest value needed to map the required virtual addresses
455 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL
456 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions
457 as well.
458
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100459- **#define : MAX_MMAP_REGIONS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100460
461 Defines the maximum number of regions that are allocated by the translation
462 table library code. A region consists of physical base address, virtual base
463 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
464 defined in the ``mmap_region_t`` structure. The platform defines the regions
465 that should be mapped. Then, the translation table library will create the
466 corresponding tables and descriptors at runtime. To minimize the amount of
467 runtime memory used, choose the smallest value needed to register the
468 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is
469 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate
470 the dynamic regions as well.
471
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100472- **#define : PLAT_VIRT_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100473
474 Defines the total size of the virtual address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000475 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100476
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100477- **#define : PLAT_PHY_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100478
479 Defines the total size of the physical address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000480 for a 32 bit physical address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100481
482If the platform port uses the IO storage framework, the following constants
483must also be defined:
484
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100485- **#define : MAX_IO_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100486
487 Defines the maximum number of registered IO devices. Attempting to register
488 more devices than this value using ``io_register_device()`` will fail with
489 -ENOMEM.
490
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100491- **#define : MAX_IO_HANDLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100492
493 Defines the maximum number of open IO handles. Attempting to open more IO
494 entities than this value using ``io_open()`` will fail with -ENOMEM.
495
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100496- **#define : MAX_IO_BLOCK_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100497
498 Defines the maximum number of registered IO block devices. Attempting to
499 register more devices this value using ``io_dev_open()`` will fail
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100500 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100501 With this macro, multiple block devices could be supported at the same
502 time.
503
504If the platform needs to allocate data within the per-cpu data framework in
505BL31, it should define the following macro. Currently this is only required if
506the platform decides not to use the coherent memory section by undefining the
507``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
508required memory within the the per-cpu data to minimize wastage.
509
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100510- **#define : PLAT_PCPU_DATA_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100511
512 Defines the memory (in bytes) to be reserved within the per-cpu data
513 structure for use by the platform layer.
514
515The following constants are optional. They should be defined when the platform
Dan Handley610e7e12018-03-01 18:44:00 +0000516memory layout implies some image overlaying like in Arm standard platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100517
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100518- **#define : BL31_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100519
520 Defines the maximum address in secure RAM that the BL31's progbits sections
521 can occupy.
522
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100523- **#define : TSP_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100524
525 Defines the maximum address that the TSP's progbits sections can occupy.
526
527If the platform port uses the PL061 GPIO driver, the following constant may
528optionally be defined:
529
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100530- **PLAT_PL061_MAX_GPIOS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100531 Maximum number of GPIOs required by the platform. This allows control how
532 much memory is allocated for PL061 GPIO controllers. The default value is
533
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100534 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100535
536If the platform port uses the partition driver, the following constant may
537optionally be defined:
538
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100539- **PLAT_PARTITION_MAX_ENTRIES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100540 Maximum number of partition entries required by the platform. This allows
541 control how much memory is allocated for partition entries. The default
542 value is 128.
Paul Beesleyf8640672019-04-12 14:19:42 +0100543 For example, define the build flag in ``platform.mk``:
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100544 PLAT_PARTITION_MAX_ENTRIES := 12
545 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100546
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800547- **PLAT_PARTITION_BLOCK_SIZE**
548 The size of partition block. It could be either 512 bytes or 4096 bytes.
549 The default value is 512.
Paul Beesleyf2ec7142019-10-04 16:17:46 +0000550 For example, define the build flag in ``platform.mk``:
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800551 PLAT_PARTITION_BLOCK_SIZE := 4096
552 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE))
553
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100554The following constant is optional. It should be defined to override the default
555behaviour of the ``assert()`` function (for example, to save memory).
556
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100557- **PLAT_LOG_LEVEL_ASSERT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100558 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``,
559 ``assert()`` prints the name of the file, the line number and the asserted
560 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file
561 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it
562 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't
563 defined, it defaults to ``LOG_LEVEL``.
564
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100565File : plat_macros.S [mandatory]
566~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100567
568Each platform must ensure a file of this name is in the system include path with
Dan Handley610e7e12018-03-01 18:44:00 +0000569the following macro defined. In the Arm development platforms, this file is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100570found in ``plat/arm/board/<plat_name>/include/plat_macros.S``.
571
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100572- **Macro : plat_crash_print_regs**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100573
574 This macro allows the crash reporting routine to print relevant platform
575 registers in case of an unhandled exception in BL31. This aids in debugging
576 and this macro can be defined to be empty in case register reporting is not
577 desired.
578
579 For instance, GIC or interconnect registers may be helpful for
580 troubleshooting.
581
582Handling Reset
583--------------
584
585BL1 by default implements the reset vector where execution starts from a cold
586or warm boot. BL31 can be optionally set as a reset vector using the
587``RESET_TO_BL31`` make variable.
588
589For each CPU, the reset vector code is responsible for the following tasks:
590
591#. Distinguishing between a cold boot and a warm boot.
592
593#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
594 the CPU is placed in a platform-specific state until the primary CPU
595 performs the necessary steps to remove it from this state.
596
597#. In the case of a warm boot, ensuring that the CPU jumps to a platform-
598 specific address in the BL31 image in the same processor mode as it was
599 when released from reset.
600
601The following functions need to be implemented by the platform port to enable
602reset vector code to perform the above tasks.
603
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100604Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0]
605~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100606
607::
608
609 Argument : void
610 Return : uintptr_t
611
612This function is called with the MMU and caches disabled
613(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for
614distinguishing between a warm and cold reset for the current CPU using
615platform-specific means. If it's a warm reset, then it returns the warm
616reset entrypoint point provided to ``plat_setup_psci_ops()`` during
617BL31 initialization. If it's a cold reset then this function must return zero.
618
619This function does not follow the Procedure Call Standard used by the
Dan Handley610e7e12018-03-01 18:44:00 +0000620Application Binary Interface for the Arm 64-bit architecture. The caller should
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100621not assume that callee saved registers are preserved across a call to this
622function.
623
624This function fulfills requirement 1 and 3 listed above.
625
626Note that for platforms that support programming the reset address, it is
627expected that a CPU will start executing code directly at the right address,
628both on a cold and warm reset. In this case, there is no need to identify the
629type of reset nor to query the warm reset entrypoint. Therefore, implementing
630this function is not required on such platforms.
631
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100632Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
633~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100634
635::
636
637 Argument : void
638
639This function is called with the MMU and data caches disabled. It is responsible
640for placing the executing secondary CPU in a platform-specific state until the
641primary CPU performs the necessary actions to bring it out of that state and
642allow entry into the OS. This function must not return.
643
Dan Handley610e7e12018-03-01 18:44:00 +0000644In the Arm FVP port, when using the normal boot flow, each secondary CPU powers
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100645itself off. The primary CPU is responsible for powering up the secondary CPUs
646when normal world software requires them. When booting an EL3 payload instead,
647they stay powered on and are put in a holding pen until their mailbox gets
648populated.
649
650This function fulfills requirement 2 above.
651
652Note that for platforms that can't release secondary CPUs out of reset, only the
653primary CPU will execute the cold boot code. Therefore, implementing this
654function is not required on such platforms.
655
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100656Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
657~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100658
659::
660
661 Argument : void
662 Return : unsigned int
663
664This function identifies whether the current CPU is the primary CPU or a
665secondary CPU. A return value of zero indicates that the CPU is not the
666primary CPU, while a non-zero return value indicates that the CPU is the
667primary CPU.
668
669Note that for platforms that can't release secondary CPUs out of reset, only the
670primary CPU will execute the cold boot code. Therefore, there is no need to
671distinguish between primary and secondary CPUs and implementing this function is
672not required.
673
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100674Function : platform_mem_init() [mandatory]
675~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100676
677::
678
679 Argument : void
680 Return : void
681
682This function is called before any access to data is made by the firmware, in
683order to carry out any essential memory initialization.
684
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100685Function: plat_get_rotpk_info()
686~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100687
688::
689
690 Argument : void *, void **, unsigned int *, unsigned int *
691 Return : int
692
693This function is mandatory when Trusted Board Boot is enabled. It returns a
694pointer to the ROTPK stored in the platform (or a hash of it) and its length.
695The ROTPK must be encoded in DER format according to the following ASN.1
696structure:
697
698::
699
700 AlgorithmIdentifier ::= SEQUENCE {
701 algorithm OBJECT IDENTIFIER,
702 parameters ANY DEFINED BY algorithm OPTIONAL
703 }
704
705 SubjectPublicKeyInfo ::= SEQUENCE {
706 algorithm AlgorithmIdentifier,
707 subjectPublicKey BIT STRING
708 }
709
710In case the function returns a hash of the key:
711
712::
713
714 DigestInfo ::= SEQUENCE {
715 digestAlgorithm AlgorithmIdentifier,
716 digest OCTET STRING
717 }
718
719The function returns 0 on success. Any other value is treated as error by the
720Trusted Board Boot. The function also reports extra information related
721to the ROTPK in the flags parameter:
722
723::
724
725 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a
726 hash.
727 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK
728 verification while the platform ROTPK is not deployed.
729 When this flag is set, the function does not need to
730 return a platform ROTPK, and the authentication
731 framework uses the ROTPK in the certificate without
732 verifying it against the platform value. This flag
733 must not be used in a deployed production environment.
734
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100735Function: plat_get_nv_ctr()
736~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100737
738::
739
740 Argument : void *, unsigned int *
741 Return : int
742
743This function is mandatory when Trusted Board Boot is enabled. It returns the
744non-volatile counter value stored in the platform in the second argument. The
745cookie in the first argument may be used to select the counter in case the
746platform provides more than one (for example, on platforms that use the default
747TBBR CoT, the cookie will correspond to the OID values defined in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100748TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100749
750The function returns 0 on success. Any other value means the counter value could
751not be retrieved from the platform.
752
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100753Function: plat_set_nv_ctr()
754~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100755
756::
757
758 Argument : void *, unsigned int
759 Return : int
760
761This function is mandatory when Trusted Board Boot is enabled. It sets a new
762counter value in the platform. The cookie in the first argument may be used to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100763select the counter (as explained in plat_get_nv_ctr()). The second argument is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100764the updated counter value to be written to the NV counter.
765
766The function returns 0 on success. Any other value means the counter value could
767not be updated.
768
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100769Function: plat_set_nv_ctr2()
770~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100771
772::
773
774 Argument : void *, const auth_img_desc_t *, unsigned int
775 Return : int
776
777This function is optional when Trusted Board Boot is enabled. If this
778interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The
779first argument passed is a cookie and is typically used to
780differentiate between a Non Trusted NV Counter and a Trusted NV
781Counter. The second argument is a pointer to an authentication image
782descriptor and may be used to decide if the counter is allowed to be
783updated or not. The third argument is the updated counter value to
784be written to the NV counter.
785
786The function returns 0 on success. Any other value means the counter value
787either could not be updated or the authentication image descriptor indicates
788that it is not allowed to be updated.
789
790Common mandatory function modifications
791---------------------------------------
792
793The following functions are mandatory functions which need to be implemented
794by the platform port.
795
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100796Function : plat_my_core_pos()
797~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100798
799::
800
801 Argument : void
802 Return : unsigned int
803
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000804This function returns the index of the calling CPU which is used as a
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100805CPU-specific linear index into blocks of memory (for example while allocating
806per-CPU stacks). This function will be invoked very early in the
807initialization sequence which mandates that this function should be
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000808implemented in assembly and should not rely on the availability of a C
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100809runtime environment. This function can clobber x0 - x8 and must preserve
810x9 - x29.
811
812This function plays a crucial role in the power domain topology framework in
Paul Beesleyf8640672019-04-12 14:19:42 +0100813PSCI and details of this can be found in
814:ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100815
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100816Function : plat_core_pos_by_mpidr()
817~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100818
819::
820
821 Argument : u_register_t
822 Return : int
823
824This function validates the ``MPIDR`` of a CPU and converts it to an index,
825which can be used as a CPU-specific linear index into blocks of memory. In
826case the ``MPIDR`` is invalid, this function returns -1. This function will only
827be invoked by BL31 after the power domain topology is initialized and can
Dan Handley610e7e12018-03-01 18:44:00 +0000828utilize the C runtime environment. For further details about how TF-A
829represents the power domain topology and how this relates to the linear CPU
Paul Beesleyf8640672019-04-12 14:19:42 +0100830index, please refer :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100831
Ambroise Vincentd207f562019-04-10 12:50:27 +0100832Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1]
833~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
834
835::
836
837 Arguments : void **heap_addr, size_t *heap_size
838 Return : int
839
840This function is invoked during Mbed TLS library initialisation to get a heap,
841by means of a starting address and a size. This heap will then be used
842internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS
843must be able to provide a heap to it.
844
845A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in
846which a heap is statically reserved during compile time inside every image
847(i.e. every BL stage) that utilises Mbed TLS. In this default implementation,
848the function simply returns the address and size of this "pre-allocated" heap.
849For a platform to use this default implementation, only a call to the helper
850from inside plat_get_mbedtls_heap() body is enough and nothing else is needed.
851
852However, by writting their own implementation, platforms have the potential to
853optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is
854shared between BL1 and BL2 stages and, thus, the necessary space is not reserved
855twice.
856
857On success the function should return 0 and a negative error code otherwise.
858
Sumit Gargc0c369c2019-11-15 18:47:53 +0530859Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1]
860~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
861
862::
863
864 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key,
865 size_t *key_len, unsigned int *flags, const uint8_t *img_id,
866 size_t img_id_len
867 Return : int
868
869This function provides a symmetric key (either SSK or BSSK depending on
870fw_enc_status) which is invoked during runtime decryption of encrypted
871firmware images. `plat/common/plat_bl_common.c` provides a dummy weak
872implementation for testing purposes which must be overridden by the platform
873trying to implement a real world firmware encryption use-case.
874
875It also allows the platform to pass symmetric key identifier rather than
876actual symmetric key which is useful in cases where the crypto backend provides
877secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER``
878flag must be set in ``flags``.
879
880In addition to above a platform may also choose to provide an image specific
881symmetric key/identifier using img_id.
882
883On success the function should return 0 and a negative error code otherwise.
884
Manish Pandey34a305e2021-10-21 21:53:49 +0100885Note that this API depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530886
Manish V Badarkheda87af12021-06-20 21:14:46 +0100887Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1]
888~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
889
890::
891
Sughosh Ganuf40154f2021-11-17 17:08:10 +0530892 Argument : const struct fwu_metadata *metadata
Manish V Badarkheda87af12021-06-20 21:14:46 +0100893 Return : void
894
895This function is mandatory when PSA_FWU_SUPPORT is enabled.
896It provides a means to retrieve image specification (offset in
897non-volatile storage and length) of active/updated images using the passed
898FWU metadata, and update I/O policies of active/updated images using retrieved
899image specification information.
900Further I/O layer operations such as I/O open, I/O read, etc. on these
901images rely on this function call.
902
903In Arm platforms, this function is used to set an I/O policy of the FIP image,
904container of all active/updated secure and non-secure images.
905
906Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1]
907~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
908
909::
910
911 Argument : unsigned int image_id, uintptr_t *dev_handle,
912 uintptr_t *image_spec
913 Return : int
914
915This function is mandatory when PSA_FWU_SUPPORT is enabled. It is
916responsible for setting up the platform I/O policy of the requested metadata
917image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will
918be used to load this image from the platform's non-volatile storage.
919
920FWU metadata can not be always stored as a raw image in non-volatile storage
921to define its image specification (offset in non-volatile storage and length)
922statically in I/O policy.
923For example, the FWU metadata image is stored as a partition inside the GUID
924partition table image. Its specification is defined in the partition table
925that needs to be parsed dynamically.
926This function provides a means to retrieve such dynamic information to set
927the I/O policy of the FWU metadata image.
928Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata
929image relies on this function call.
930
931It returns '0' on success, otherwise a negative error value on error.
932Alongside, returns device handle and image specification from the I/O policy
933of the requested FWU metadata image.
934
Sughosh Ganu4e336a62021-12-01 15:53:32 +0530935Function : plat_fwu_get_boot_idx() [when PSA_FWU_SUPPORT == 1]
936~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
937
938::
939
940 Argument : void
941 Return : uint32_t
942
943This function is mandatory when PSA_FWU_SUPPORT is enabled. It provides the
944means to retrieve the boot index value from the platform. The boot index is the
945bank from which the platform has booted the firmware images.
946
947By default, the platform will read the metadata structure and try to boot from
948the active bank. If the platform fails to boot from the active bank due to
949reasons like an Authentication failure, or on crossing a set number of watchdog
950resets while booting from the active bank, the platform can then switch to boot
951from a different bank. This function then returns the bank that the platform
952should boot its images from.
953
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100954Common optional modifications
955-----------------------------
956
957The following are helper functions implemented by the firmware that perform
958common platform-specific tasks. A platform may choose to override these
959definitions.
960
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100961Function : plat_set_my_stack()
962~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100963
964::
965
966 Argument : void
967 Return : void
968
969This function sets the current stack pointer to the normal memory stack that
970has been allocated for the current CPU. For BL images that only require a
971stack for the primary CPU, the UP version of the function is used. The size
972of the stack allocated to each CPU is specified by the platform defined
973constant ``PLATFORM_STACK_SIZE``.
974
975Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +0100976provided in ``plat/common/aarch64/platform_up_stack.S`` and
977``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100978
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100979Function : plat_get_my_stack()
980~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100981
982::
983
984 Argument : void
985 Return : uintptr_t
986
987This function returns the base address of the normal memory stack that
988has been allocated for the current CPU. For BL images that only require a
989stack for the primary CPU, the UP version of the function is used. The size
990of the stack allocated to each CPU is specified by the platform defined
991constant ``PLATFORM_STACK_SIZE``.
992
993Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +0100994provided in ``plat/common/aarch64/platform_up_stack.S`` and
995``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100996
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100997Function : plat_report_exception()
998~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100999
1000::
1001
1002 Argument : unsigned int
1003 Return : void
1004
1005A platform may need to report various information about its status when an
1006exception is taken, for example the current exception level, the CPU security
1007state (secure/non-secure), the exception type, and so on. This function is
1008called in the following circumstances:
1009
1010- In BL1, whenever an exception is taken.
1011- In BL2, whenever an exception is taken.
1012
1013The default implementation doesn't do anything, to avoid making assumptions
1014about the way the platform displays its status information.
1015
1016For AArch64, this function receives the exception type as its argument.
1017Possible values for exceptions types are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +01001018``include/common/bl_common.h`` header file. Note that these constants are not
Dan Handley610e7e12018-03-01 18:44:00 +00001019related to any architectural exception code; they are just a TF-A convention.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001020
1021For AArch32, this function receives the exception mode as its argument.
1022Possible values for exception modes are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +01001023``include/lib/aarch32/arch.h`` header file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001024
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001025Function : plat_reset_handler()
1026~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001027
1028::
1029
1030 Argument : void
1031 Return : void
1032
1033A platform may need to do additional initialization after reset. This function
Paul Beesleyf2ec7142019-10-04 16:17:46 +00001034allows the platform to do the platform specific initializations. Platform
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001035specific errata workarounds could also be implemented here. The API should
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001036preserve the values of callee saved registers x19 to x29.
1037
1038The default implementation doesn't do anything. If a platform needs to override
Paul Beesleyf8640672019-04-12 14:19:42 +01001039the default implementation, refer to the :ref:`Firmware Design` for general
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001040guidelines.
1041
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001042Function : plat_disable_acp()
1043~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001044
1045::
1046
1047 Argument : void
1048 Return : void
1049
John Tsichritzis6dda9762018-07-23 09:18:04 +01001050This API allows a platform to disable the Accelerator Coherency Port (if
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001051present) during a cluster power down sequence. The default weak implementation
John Tsichritzis6dda9762018-07-23 09:18:04 +01001052doesn't do anything. Since this API is called during the power down sequence,
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001053it has restrictions for stack usage and it can use the registers x0 - x17 as
1054scratch registers. It should preserve the value in x18 register as it is used
1055by the caller to store the return address.
1056
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001057Function : plat_error_handler()
1058~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001059
1060::
1061
1062 Argument : int
1063 Return : void
1064
1065This API is called when the generic code encounters an error situation from
1066which it cannot continue. It allows the platform to perform error reporting or
1067recovery actions (for example, reset the system). This function must not return.
1068
1069The parameter indicates the type of error using standard codes from ``errno.h``.
1070Possible errors reported by the generic code are:
1071
1072- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted
1073 Board Boot is enabled)
1074- ``-ENOENT``: the requested image or certificate could not be found or an IO
1075 error was detected
Dan Handley610e7e12018-03-01 18:44:00 +00001076- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this
1077 error is usually an indication of an incorrect array size
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001078
1079The default implementation simply spins.
1080
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001081Function : plat_panic_handler()
1082~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001083
1084::
1085
1086 Argument : void
1087 Return : void
1088
1089This API is called when the generic code encounters an unexpected error
1090situation from which it cannot recover. This function must not return,
1091and must be implemented in assembly because it may be called before the C
1092environment is initialized.
1093
Paul Beesleyba3ed402019-03-13 16:20:44 +00001094.. note::
1095 The address from where it was called is stored in x30 (Link Register).
1096 The default implementation simply spins.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001097
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001098Function : plat_get_bl_image_load_info()
1099~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001100
1101::
1102
1103 Argument : void
1104 Return : bl_load_info_t *
1105
1106This function returns pointer to the list of images that the platform has
Soby Mathew97b1bff2018-09-27 16:46:41 +01001107populated to load. This function is invoked in BL2 to load the
1108BL3xx images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001109
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001110Function : plat_get_next_bl_params()
1111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001112
1113::
1114
1115 Argument : void
1116 Return : bl_params_t *
1117
1118This function returns a pointer to the shared memory that the platform has
Dan Handley610e7e12018-03-01 18:44:00 +00001119kept aside to pass TF-A related information that next BL image needs. This
Soby Mathew97b1bff2018-09-27 16:46:41 +01001120function is invoked in BL2 to pass this information to the next BL
1121image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001122
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001123Function : plat_get_stack_protector_canary()
1124~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001125
1126::
1127
1128 Argument : void
1129 Return : u_register_t
1130
1131This function returns a random value that is used to initialize the canary used
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001132when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001133value will weaken the protection as the attacker could easily write the right
1134value as part of the attack most of the time. Therefore, it should return a
1135true random number.
1136
Paul Beesleyba3ed402019-03-13 16:20:44 +00001137.. warning::
1138 For the protection to be effective, the global data need to be placed at
1139 a lower address than the stack bases. Failure to do so would allow an
1140 attacker to overwrite the canary as part of the stack buffer overflow attack.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001141
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001142Function : plat_flush_next_bl_params()
1143~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001144
1145::
1146
1147 Argument : void
1148 Return : void
1149
1150This function flushes to main memory all the image params that are passed to
Soby Mathew97b1bff2018-09-27 16:46:41 +01001151next image. This function is invoked in BL2 to flush this information
1152to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001153
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001154Function : plat_log_get_prefix()
1155~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewaaf15f52017-09-04 11:49:29 +01001156
1157::
1158
1159 Argument : unsigned int
1160 Return : const char *
1161
1162This function defines the prefix string corresponding to the `log_level` to be
Dan Handley610e7e12018-03-01 18:44:00 +00001163prepended to all the log output from TF-A. The `log_level` (argument) will
1164correspond to one of the standard log levels defined in debug.h. The platform
1165can override the common implementation to define a different prefix string for
John Tsichritzis30f89642018-06-07 16:31:34 +01001166the log output. The implementation should be robust to future changes that
Dan Handley610e7e12018-03-01 18:44:00 +00001167increase the number of log levels.
Soby Mathewaaf15f52017-09-04 11:49:29 +01001168
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001169Function : plat_get_soc_version()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001170~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001171
1172::
1173
1174 Argument : void
1175 Return : int32_t
1176
1177This function returns soc version which mainly consist of below fields
1178
1179::
1180
1181 soc_version[30:24] = JEP-106 continuation code for the SiP
1182 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001183 soc_version[15:0] = Implementation defined SoC ID
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001184
1185Function : plat_get_soc_revision()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001186~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001187
1188::
1189
1190 Argument : void
1191 Return : int32_t
1192
1193This function returns soc revision in below format
1194
1195::
1196
1197 soc_revision[0:30] = SOC revision of specific SOC
1198
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001199Function : plat_is_smccc_feature_available()
1200~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1201
1202::
1203
1204 Argument : u_register_t
1205 Return : int32_t
1206
1207This function returns SMC_ARCH_CALL_SUCCESS if the platform supports
1208the SMCCC function specified in the argument; otherwise returns
1209SMC_ARCH_CALL_NOT_SUPPORTED.
1210
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001211Function : plat_mboot_measure_image()
1212~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1213
1214::
1215
1216 Argument : unsigned int, image_info_t *
Manish V Badarkhe931c6ef2021-10-21 09:06:18 +01001217 Return : int
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001218
1219When the MEASURED_BOOT flag is enabled:
1220
1221- This function measures the given image and records its measurement using
1222 the measured boot backend driver.
1223- On the Arm FVP port, this function measures the given image using its
1224 passed id and information and then records that measurement in the
1225 Event Log buffer.
Manish V Badarkhe931c6ef2021-10-21 09:06:18 +01001226- This function must return 0 on success, a signed integer error code
1227 otherwise.
1228
1229When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1230
1231Function : plat_mboot_measure_critical_data()
1232~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1233
1234::
1235
1236 Argument : unsigned int, const void *, size_t
1237 Return : int
1238
1239When the MEASURED_BOOT flag is enabled:
1240
1241- This function measures the given critical data structure and records its
1242 measurement using the measured boot backend driver.
1243- This function must return 0 on success, a signed integer error code
1244 otherwise.
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001245
1246When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1247
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001248Modifications specific to a Boot Loader stage
1249---------------------------------------------
1250
1251Boot Loader Stage 1 (BL1)
1252-------------------------
1253
1254BL1 implements the reset vector where execution starts from after a cold or
1255warm boot. For each CPU, BL1 is responsible for the following tasks:
1256
1257#. Handling the reset as described in section 2.2
1258
1259#. In the case of a cold boot and the CPU being the primary CPU, ensuring that
1260 only this CPU executes the remaining BL1 code, including loading and passing
1261 control to the BL2 stage.
1262
1263#. Identifying and starting the Firmware Update process (if required).
1264
1265#. Loading the BL2 image from non-volatile storage into secure memory at the
1266 address specified by the platform defined constant ``BL2_BASE``.
1267
1268#. Populating a ``meminfo`` structure with the following information in memory,
1269 accessible by BL2 immediately upon entry.
1270
1271 ::
1272
1273 meminfo.total_base = Base address of secure RAM visible to BL2
1274 meminfo.total_size = Size of secure RAM visible to BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001275
Soby Mathew97b1bff2018-09-27 16:46:41 +01001276 By default, BL1 places this ``meminfo`` structure at the end of secure
1277 memory visible to BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001278
Soby Mathewb1bf0442018-02-16 14:52:52 +00001279 It is possible for the platform to decide where it wants to place the
1280 ``meminfo`` structure for BL2 or restrict the amount of memory visible to
1281 BL2 by overriding the weak default implementation of
1282 ``bl1_plat_handle_post_image_load`` API.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001283
1284The following functions need to be implemented by the platform port to enable
1285BL1 to perform the above tasks.
1286
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001287Function : bl1_early_platform_setup() [mandatory]
1288~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001289
1290::
1291
1292 Argument : void
1293 Return : void
1294
1295This function executes with the MMU and data caches disabled. It is only called
1296by the primary CPU.
1297
Dan Handley610e7e12018-03-01 18:44:00 +00001298On Arm standard platforms, this function:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001299
1300- Enables a secure instance of SP805 to act as the Trusted Watchdog.
1301
1302- Initializes a UART (PL011 console), which enables access to the ``printf``
1303 family of functions in BL1.
1304
1305- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to
1306 the CCI slave interface corresponding to the cluster that includes the
1307 primary CPU.
1308
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001309Function : bl1_plat_arch_setup() [mandatory]
1310~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001311
1312::
1313
1314 Argument : void
1315 Return : void
1316
1317This function performs any platform-specific and architectural setup that the
1318platform requires. Platform-specific setup might include configuration of
1319memory controllers and the interconnect.
1320
Dan Handley610e7e12018-03-01 18:44:00 +00001321In Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001322
1323This function helps fulfill requirement 2 above.
1324
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001325Function : bl1_platform_setup() [mandatory]
1326~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001327
1328::
1329
1330 Argument : void
1331 Return : void
1332
1333This function executes with the MMU and data caches enabled. It is responsible
1334for performing any remaining platform-specific setup that can occur after the
1335MMU and data cache have been enabled.
1336
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001337if support for multiple boot sources is required, it initializes the boot
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001338sequence used by plat_try_next_boot_source().
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001339
Dan Handley610e7e12018-03-01 18:44:00 +00001340In Arm standard platforms, this function initializes the storage abstraction
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001341layer used to load the next bootloader image.
1342
1343This function helps fulfill requirement 4 above.
1344
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001345Function : bl1_plat_sec_mem_layout() [mandatory]
1346~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001347
1348::
1349
1350 Argument : void
1351 Return : meminfo *
1352
1353This function should only be called on the cold boot path. It executes with the
1354MMU and data caches enabled. The pointer returned by this function must point to
1355a ``meminfo`` structure containing the extents and availability of secure RAM for
1356the BL1 stage.
1357
1358::
1359
1360 meminfo.total_base = Base address of secure RAM visible to BL1
1361 meminfo.total_size = Size of secure RAM visible to BL1
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001362
1363This information is used by BL1 to load the BL2 image in secure RAM. BL1 also
1364populates a similar structure to tell BL2 the extents of memory available for
1365its own use.
1366
1367This function helps fulfill requirements 4 and 5 above.
1368
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001369Function : bl1_plat_prepare_exit() [optional]
1370~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001371
1372::
1373
1374 Argument : entry_point_info_t *
1375 Return : void
1376
1377This function is called prior to exiting BL1 in response to the
1378``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform
1379platform specific clean up or bookkeeping operations before transferring
1380control to the next image. It receives the address of the ``entry_point_info_t``
1381structure passed from BL2. This function runs with MMU disabled.
1382
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001383Function : bl1_plat_set_ep_info() [optional]
1384~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001385
1386::
1387
1388 Argument : unsigned int image_id, entry_point_info_t *ep_info
1389 Return : void
1390
1391This function allows platforms to override ``ep_info`` for the given ``image_id``.
1392
1393The default implementation just returns.
1394
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001395Function : bl1_plat_get_next_image_id() [optional]
1396~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001397
1398::
1399
1400 Argument : void
1401 Return : unsigned int
1402
1403This and the following function must be overridden to enable the FWU feature.
1404
1405BL1 calls this function after platform setup to identify the next image to be
1406loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds
1407with the normal boot sequence, which loads and executes BL2. If the platform
1408returns a different image id, BL1 assumes that Firmware Update is required.
1409
Dan Handley610e7e12018-03-01 18:44:00 +00001410The default implementation always returns ``BL2_IMAGE_ID``. The Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001411platforms override this function to detect if firmware update is required, and
1412if so, return the first image in the firmware update process.
1413
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001414Function : bl1_plat_get_image_desc() [optional]
1415~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001416
1417::
1418
1419 Argument : unsigned int image_id
1420 Return : image_desc_t *
1421
1422BL1 calls this function to get the image descriptor information ``image_desc_t``
1423for the provided ``image_id`` from the platform.
1424
Dan Handley610e7e12018-03-01 18:44:00 +00001425The default implementation always returns a common BL2 image descriptor. Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001426standard platforms return an image descriptor corresponding to BL2 or one of
1427the firmware update images defined in the Trusted Board Boot Requirements
1428specification.
1429
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001430Function : bl1_plat_handle_pre_image_load() [optional]
1431~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001432
1433::
1434
Soby Mathew2f38ce32018-02-08 17:45:12 +00001435 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001436 Return : int
1437
1438This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001439corresponding to ``image_id``. This function is invoked in BL1, both in cold
1440boot and FWU code path, before loading the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001441
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001442Function : bl1_plat_handle_post_image_load() [optional]
1443~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001444
1445::
1446
Soby Mathew2f38ce32018-02-08 17:45:12 +00001447 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001448 Return : int
1449
1450This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001451corresponding to ``image_id``. This function is invoked in BL1, both in cold
1452boot and FWU code path, after loading and authenticating the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001453
Soby Mathewb1bf0442018-02-16 14:52:52 +00001454The default weak implementation of this function calculates the amount of
1455Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t``
1456structure at the beginning of this free memory and populates it. The address
1457of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint
1458information to BL2.
1459
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001460Function : bl1_plat_fwu_done() [optional]
1461~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001462
1463::
1464
1465 Argument : unsigned int image_id, uintptr_t image_src,
1466 unsigned int image_size
1467 Return : void
1468
1469BL1 calls this function when the FWU process is complete. It must not return.
1470The platform may override this function to take platform specific action, for
1471example to initiate the normal boot flow.
1472
1473The default implementation spins forever.
1474
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001475Function : bl1_plat_mem_check() [mandatory]
1476~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001477
1478::
1479
1480 Argument : uintptr_t mem_base, unsigned int mem_size,
1481 unsigned int flags
1482 Return : int
1483
1484BL1 calls this function while handling FWU related SMCs, more specifically when
1485copying or authenticating an image. Its responsibility is to ensure that the
1486region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and
1487that this memory corresponds to either a secure or non-secure memory region as
1488indicated by the security state of the ``flags`` argument.
1489
1490This function can safely assume that the value resulting from the addition of
1491``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not
1492overflow.
1493
1494This function must return 0 on success, a non-null error code otherwise.
1495
1496The default implementation of this function asserts therefore platforms must
1497override it when using the FWU feature.
1498
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001499Function : bl1_plat_mboot_init() [optional]
1500~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1501
1502::
1503
1504 Argument : void
1505 Return : void
1506
1507When the MEASURED_BOOT flag is enabled:
1508
1509- This function is used to initialize the backend driver(s) of measured boot.
1510- On the Arm FVP port, this function is used to initialize the Event Log
1511 backend driver, and also to write header information in the Event Log buffer.
1512
1513When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1514
1515Function : bl1_plat_mboot_finish() [optional]
1516~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1517
1518::
1519
1520 Argument : void
1521 Return : void
1522
1523When the MEASURED_BOOT flag is enabled:
1524
1525- This function is used to finalize the measured boot backend driver(s),
1526 and also, set the information for the next bootloader component to
1527 extend the measurement if needed.
1528- On the Arm FVP port, this function is used to pass the base address of
1529 the Event Log buffer and its size to BL2 via tb_fw_config to extend the
1530 Event Log buffer with the measurement of various images loaded by BL2.
1531 It results in panic on error.
1532
1533When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1534
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001535Boot Loader Stage 2 (BL2)
1536-------------------------
1537
1538The BL2 stage is executed only by the primary CPU, which is determined in BL1
1539using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at
Soby Mathew97b1bff2018-09-27 16:46:41 +01001540``BL2_BASE``. BL2 executes in Secure EL1 and and invokes
1541``plat_get_bl_image_load_info()`` to retrieve the list of images to load from
1542non-volatile storage to secure/non-secure RAM. After all the images are loaded
1543then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable
1544images to be passed to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001545
1546The following functions must be implemented by the platform port to enable BL2
1547to perform the above tasks.
1548
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001549Function : bl2_early_platform_setup2() [mandatory]
1550~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001551
1552::
1553
Soby Mathew97b1bff2018-09-27 16:46:41 +01001554 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001555 Return : void
1556
1557This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001558by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments
1559are platform specific.
1560
1561On Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001562
Manish V Badarkhe81414512020-06-24 15:58:38 +01001563 arg0 - Points to load address of FW_CONFIG
Soby Mathew97b1bff2018-09-27 16:46:41 +01001564
1565 arg1 - ``meminfo`` structure populated by BL1. The platform copies
1566 the contents of ``meminfo`` as it may be subsequently overwritten by BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001567
Dan Handley610e7e12018-03-01 18:44:00 +00001568On Arm standard platforms, this function also:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001569
1570- Initializes a UART (PL011 console), which enables access to the ``printf``
1571 family of functions in BL2.
1572
1573- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001574 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1575 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001576
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001577Function : bl2_plat_arch_setup() [mandatory]
1578~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001579
1580::
1581
1582 Argument : void
1583 Return : void
1584
1585This function executes with the MMU and data caches disabled. It is only called
1586by the primary CPU.
1587
1588The purpose of this function is to perform any architectural initialization
1589that varies across platforms.
1590
Dan Handley610e7e12018-03-01 18:44:00 +00001591On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001592
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001593Function : bl2_platform_setup() [mandatory]
1594~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001595
1596::
1597
1598 Argument : void
1599 Return : void
1600
1601This function may execute with the MMU and data caches enabled if the platform
1602port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only
1603called by the primary CPU.
1604
1605The purpose of this function is to perform any platform initialization
1606specific to BL2.
1607
Dan Handley610e7e12018-03-01 18:44:00 +00001608In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001609configuration of the TrustZone controller to allow non-secure masters access
1610to most of DRAM. Part of DRAM is reserved for secure world use.
1611
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001612Function : bl2_plat_handle_pre_image_load() [optional]
1613~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001614
1615::
1616
1617 Argument : unsigned int
1618 Return : int
1619
1620This function can be used by the platforms to update/use image information
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001621for given ``image_id``. This function is currently invoked in BL2 before
Soby Mathew97b1bff2018-09-27 16:46:41 +01001622loading each image.
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001623
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001624Function : bl2_plat_handle_post_image_load() [optional]
1625~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001626
1627::
1628
1629 Argument : unsigned int
1630 Return : int
1631
1632This function can be used by the platforms to update/use image information
1633for given ``image_id``. This function is currently invoked in BL2 after
Soby Mathew97b1bff2018-09-27 16:46:41 +01001634loading each image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001635
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001636Function : bl2_plat_preload_setup [optional]
1637~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001638
1639::
John Tsichritzisee10e792018-06-06 09:38:10 +01001640
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001641 Argument : void
1642 Return : void
1643
1644This optional function performs any BL2 platform initialization
1645required before image loading, that is not done later in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001646bl2_platform_setup(). Specifically, if support for multiple
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001647boot sources is required, it initializes the boot sequence used by
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001648plat_try_next_boot_source().
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001649
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001650Function : plat_try_next_boot_source() [optional]
1651~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001652
1653::
John Tsichritzisee10e792018-06-06 09:38:10 +01001654
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001655 Argument : void
1656 Return : int
1657
1658This optional function passes to the next boot source in the redundancy
1659sequence.
1660
1661This function moves the current boot redundancy source to the next
1662element in the boot sequence. If there are no more boot sources then it
1663must return 0, otherwise it must return 1. The default implementation
1664of this always returns 0.
1665
Roberto Vargasb1584272017-11-20 13:36:10 +00001666Boot Loader Stage 2 (BL2) at EL3
1667--------------------------------
1668
Dan Handley610e7e12018-03-01 18:44:00 +00001669When the platform has a non-TF-A Boot ROM it is desirable to jump
1670directly to BL2 instead of TF-A BL1. In this case BL2 is expected to
Paul Beesleyf8640672019-04-12 14:19:42 +01001671execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design`
1672document for more information.
Roberto Vargasb1584272017-11-20 13:36:10 +00001673
1674All mandatory functions of BL2 must be implemented, except the functions
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001675bl2_early_platform_setup and bl2_el3_plat_arch_setup, because
1676their work is done now by bl2_el3_early_platform_setup and
1677bl2_el3_plat_arch_setup. These functions should generally implement
1678the bl1_plat_xxx() and bl2_plat_xxx() functionality combined.
Roberto Vargasb1584272017-11-20 13:36:10 +00001679
1680
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001681Function : bl2_el3_early_platform_setup() [mandatory]
1682~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001683
1684::
John Tsichritzisee10e792018-06-06 09:38:10 +01001685
Roberto Vargasb1584272017-11-20 13:36:10 +00001686 Argument : u_register_t, u_register_t, u_register_t, u_register_t
1687 Return : void
1688
1689This function executes with the MMU and data caches disabled. It is only called
1690by the primary CPU. This function receives four parameters which can be used
1691by the platform to pass any needed information from the Boot ROM to BL2.
1692
Dan Handley610e7e12018-03-01 18:44:00 +00001693On Arm standard platforms, this function does the following:
Roberto Vargasb1584272017-11-20 13:36:10 +00001694
1695- Initializes a UART (PL011 console), which enables access to the ``printf``
1696 family of functions in BL2.
1697
1698- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001699 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1700 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Roberto Vargasb1584272017-11-20 13:36:10 +00001701
1702- Initializes the private variables that define the memory layout used.
1703
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001704Function : bl2_el3_plat_arch_setup() [mandatory]
1705~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001706
1707::
John Tsichritzisee10e792018-06-06 09:38:10 +01001708
Roberto Vargasb1584272017-11-20 13:36:10 +00001709 Argument : void
1710 Return : void
1711
1712This function executes with the MMU and data caches disabled. It is only called
1713by the primary CPU.
1714
1715The purpose of this function is to perform any architectural initialization
1716that varies across platforms.
1717
Dan Handley610e7e12018-03-01 18:44:00 +00001718On Arm standard platforms, this function enables the MMU.
Roberto Vargasb1584272017-11-20 13:36:10 +00001719
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001720Function : bl2_el3_plat_prepare_exit() [optional]
1721~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001722
1723::
John Tsichritzisee10e792018-06-06 09:38:10 +01001724
Roberto Vargasb1584272017-11-20 13:36:10 +00001725 Argument : void
1726 Return : void
1727
1728This function is called prior to exiting BL2 and run the next image.
1729It should be used to perform platform specific clean up or bookkeeping
1730operations before transferring control to the next image. This function
1731runs with MMU disabled.
1732
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001733FWU Boot Loader Stage 2 (BL2U)
1734------------------------------
1735
1736The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU
1737process and is executed only by the primary CPU. BL1 passes control to BL2U at
1738``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for:
1739
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001740#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure
1741 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1.
1742 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U
1743 should be copied from. Subsequent handling of the SCP_BL2U image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001744 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function.
1745 If ``SCP_BL2U_BASE`` is not defined then this step is not performed.
1746
1747#. Any platform specific setup required to perform the FWU process. For
Dan Handley610e7e12018-03-01 18:44:00 +00001748 example, Arm standard platforms initialize the TZC controller so that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001749 normal world can access DDR memory.
1750
1751The following functions must be implemented by the platform port to enable
1752BL2U to perform the tasks mentioned above.
1753
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001754Function : bl2u_early_platform_setup() [mandatory]
1755~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001756
1757::
1758
1759 Argument : meminfo *mem_info, void *plat_info
1760 Return : void
1761
1762This function executes with the MMU and data caches disabled. It is only
1763called by the primary CPU. The arguments to this function is the address
1764of the ``meminfo`` structure and platform specific info provided by BL1.
1765
1766The platform may copy the contents of the ``mem_info`` and ``plat_info`` into
1767private storage as the original memory may be subsequently overwritten by BL2U.
1768
Dan Handley610e7e12018-03-01 18:44:00 +00001769On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001770to extract SCP_BL2U image information, which is then copied into a private
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001771variable.
1772
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001773Function : bl2u_plat_arch_setup() [mandatory]
1774~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001775
1776::
1777
1778 Argument : void
1779 Return : void
1780
1781This function executes with the MMU and data caches disabled. It is only
1782called by the primary CPU.
1783
1784The purpose of this function is to perform any architectural initialization
1785that varies across platforms, for example enabling the MMU (since the memory
1786map differs across platforms).
1787
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001788Function : bl2u_platform_setup() [mandatory]
1789~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001790
1791::
1792
1793 Argument : void
1794 Return : void
1795
1796This function may execute with the MMU and data caches enabled if the platform
1797port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only
1798called by the primary CPU.
1799
1800The purpose of this function is to perform any platform initialization
1801specific to BL2U.
1802
Dan Handley610e7e12018-03-01 18:44:00 +00001803In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001804configuration of the TrustZone controller to allow non-secure masters access
1805to most of DRAM. Part of DRAM is reserved for secure world use.
1806
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001807Function : bl2u_plat_handle_scp_bl2u() [optional]
1808~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001809
1810::
1811
1812 Argument : void
1813 Return : int
1814
1815This function is used to perform any platform-specific actions required to
1816handle the SCP firmware. Typically it transfers the image into SCP memory using
1817a platform-specific protocol and waits until SCP executes it and signals to the
1818Application Processor (AP) for BL2U execution to continue.
1819
1820This function returns 0 on success, a negative error code otherwise.
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001821This function is included if SCP_BL2U_BASE is defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001822
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001823Function : bl2_plat_mboot_init() [optional]
1824~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1825
1826::
1827
1828 Argument : void
1829 Return : void
1830
1831When the MEASURED_BOOT flag is enabled:
1832
1833- This function is used to initialize the backend driver(s) of measured boot.
1834- On the Arm FVP port, this function is used to initialize the Event Log
1835 backend driver with the Event Log buffer information (base address and
1836 size) received from BL1. It results in panic on error.
1837
1838When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1839
1840Function : bl2_plat_mboot_finish() [optional]
1841~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1842
1843::
1844
1845 Argument : void
1846 Return : void
1847
1848When the MEASURED_BOOT flag is enabled:
1849
1850- This function is used to finalize the measured boot backend driver(s),
1851 and also, set the information for the next bootloader component to extend
1852 the measurement if needed.
1853- On the Arm FVP port, this function is used to pass the Event Log buffer
1854 information (base address and size) to non-secure(BL33) and trusted OS(BL32)
1855 via nt_fw and tos_fw config respectively. It results in panic on error.
1856
1857When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1858
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001859Boot Loader Stage 3-1 (BL31)
1860----------------------------
1861
1862During cold boot, the BL31 stage is executed only by the primary CPU. This is
1863determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes
1864control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all
1865CPUs. BL31 executes at EL3 and is responsible for:
1866
1867#. Re-initializing all architectural and platform state. Although BL1 performs
1868 some of this initialization, BL31 remains resident in EL3 and must ensure
1869 that EL3 architectural and platform state is completely initialized. It
1870 should make no assumptions about the system state when it receives control.
1871
1872#. Passing control to a normal world BL image, pre-loaded at a platform-
Soby Mathew97b1bff2018-09-27 16:46:41 +01001873 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list
1874 populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001875
1876#. Providing runtime firmware services. Currently, BL31 only implements a
1877 subset of the Power State Coordination Interface (PSCI) API as a runtime
1878 service. See Section 3.3 below for details of porting the PSCI
1879 implementation.
1880
1881#. Optionally passing control to the BL32 image, pre-loaded at a platform-
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001882 specific address by BL2. BL31 exports a set of APIs that allow runtime
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001883 services to specify the security state in which the next image should be
Soby Mathew97b1bff2018-09-27 16:46:41 +01001884 executed and run the corresponding image. On ARM platforms, BL31 uses the
1885 ``bl_params`` list populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001886
1887If BL31 is a reset vector, It also needs to handle the reset as specified in
1888section 2.2 before the tasks described above.
1889
1890The following functions must be implemented by the platform port to enable BL31
1891to perform the above tasks.
1892
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001893Function : bl31_early_platform_setup2() [mandatory]
1894~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001895
1896::
1897
Soby Mathew97b1bff2018-09-27 16:46:41 +01001898 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001899 Return : void
1900
1901This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001902by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are
1903platform specific.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001904
Soby Mathew97b1bff2018-09-27 16:46:41 +01001905In Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001906
Soby Mathew97b1bff2018-09-27 16:46:41 +01001907 arg0 - The pointer to the head of `bl_params_t` list
1908 which is list of executable images following BL31,
1909
1910 arg1 - Points to load address of SOC_FW_CONFIG if present
Mikael Olsson0232da22021-02-12 17:30:16 +01001911 except in case of Arm FVP and Juno platform.
Manish V Badarkhe81414512020-06-24 15:58:38 +01001912
Mikael Olsson0232da22021-02-12 17:30:16 +01001913 In case of Arm FVP and Juno platform, points to load address
Manish V Badarkhe81414512020-06-24 15:58:38 +01001914 of FW_CONFIG.
Soby Mathew97b1bff2018-09-27 16:46:41 +01001915
1916 arg2 - Points to load address of HW_CONFIG if present
1917
1918 arg3 - A special value to verify platform parameters from BL2 to BL31. Not
1919 used in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001920
Soby Mathew97b1bff2018-09-27 16:46:41 +01001921The function runs through the `bl_param_t` list and extracts the entry point
1922information for BL32 and BL33. It also performs the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001923
1924- Initialize a UART (PL011 console), which enables access to the ``printf``
1925 family of functions in BL31.
1926
1927- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the
1928 CCI slave interface corresponding to the cluster that includes the primary
1929 CPU.
1930
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001931Function : bl31_plat_arch_setup() [mandatory]
1932~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001933
1934::
1935
1936 Argument : void
1937 Return : void
1938
1939This function executes with the MMU and data caches disabled. It is only called
1940by the primary CPU.
1941
1942The purpose of this function is to perform any architectural initialization
1943that varies across platforms.
1944
Dan Handley610e7e12018-03-01 18:44:00 +00001945On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001946
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001947Function : bl31_platform_setup() [mandatory]
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001948~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1949
1950::
1951
1952 Argument : void
1953 Return : void
1954
1955This function may execute with the MMU and data caches enabled if the platform
1956port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only
1957called by the primary CPU.
1958
1959The purpose of this function is to complete platform initialization so that both
1960BL31 runtime services and normal world software can function correctly.
1961
Dan Handley610e7e12018-03-01 18:44:00 +00001962On Arm standard platforms, this function does the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001963
1964- Initialize the generic interrupt controller.
1965
1966 Depending on the GIC driver selected by the platform, the appropriate GICv2
1967 or GICv3 initialization will be done, which mainly consists of:
1968
1969 - Enable secure interrupts in the GIC CPU interface.
1970 - Disable the legacy interrupt bypass mechanism.
1971 - Configure the priority mask register to allow interrupts of all priorities
1972 to be signaled to the CPU interface.
1973 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure.
1974 - Target all secure SPIs to CPU0.
1975 - Enable these secure interrupts in the GIC distributor.
1976 - Configure all other interrupts as non-secure.
1977 - Enable signaling of secure interrupts in the GIC distributor.
1978
1979- Enable system-level implementation of the generic timer counter through the
1980 memory mapped interface.
1981
1982- Grant access to the system counter timer module
1983
1984- Initialize the power controller device.
1985
1986 In particular, initialise the locks that prevent concurrent accesses to the
1987 power controller device.
1988
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001989Function : bl31_plat_runtime_setup() [optional]
1990~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001991
1992::
1993
1994 Argument : void
1995 Return : void
1996
1997The purpose of this function is allow the platform to perform any BL31 runtime
1998setup just prior to BL31 exit during cold boot. The default weak
Julius Werneraae9bb12017-09-18 16:49:48 -07001999implementation of this function will invoke ``console_switch_state()`` to switch
2000console output to consoles marked for use in the ``runtime`` state.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002001
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002002Function : bl31_plat_get_next_image_ep_info() [mandatory]
2003~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002004
2005::
2006
Sandrine Bailleux842117d2018-05-14 14:25:47 +02002007 Argument : uint32_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002008 Return : entry_point_info *
2009
2010This function may execute with the MMU and data caches enabled if the platform
2011port does the necessary initializations in ``bl31_plat_arch_setup()``.
2012
2013This function is called by ``bl31_main()`` to retrieve information provided by
2014BL2 for the next image in the security state specified by the argument. BL31
2015uses this information to pass control to that image in the specified security
2016state. This function must return a pointer to the ``entry_point_info`` structure
2017(that was copied during ``bl31_early_platform_setup()``) if the image exists. It
2018should return NULL otherwise.
2019
Soby Mathew294e1cf2022-03-22 16:19:39 +00002020Function : plat_get_cca_attest_token() [mandatory when ENABLE_RME == 1]
2021~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2022
2023::
2024
2025 Argument : uintptr_t, size_t *, uintptr_t, size_t
2026 Return : int
2027
2028This function returns the Platform attestation token.
2029
2030The parameters of the function are:
2031
2032 arg0 - A pointer to the buffer where the Platform token should be copied by
2033 this function. The buffer must be big enough to hold the Platform
2034 token.
2035
2036 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
2037 function returns the platform token length in this parameter.
2038
2039 arg2 - A pointer to the buffer where the challenge object is stored.
2040
2041 arg3 - The length of the challenge object in bytes. Possible values are 32,
2042 48 and 64.
2043
2044The function returns 0 on success, -EINVAL on failure.
2045
Soby Mathewf05d93a2022-03-22 16:21:19 +00002046Function : plat_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1]
2047~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2048
2049::
2050
2051 Argument : uintptr_t, size_t *, unsigned int
2052 Return : int
2053
2054This function returns the delegated realm attestation key which will be used to
2055sign Realm attestation token. The API currently only supports P-384 ECC curve
2056key.
2057
2058The parameters of the function are:
2059
2060 arg0 - A pointer to the buffer where the attestation key should be copied
2061 by this function. The buffer must be big enough to hold the
2062 attestation key.
2063
2064 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
2065 function returns the attestation key length in this parameter.
2066
2067 arg2 - The type of the elliptic curve to which the requested attestation key
2068 belongs.
2069
2070The function returns 0 on success, -EINVAL on failure.
2071
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01002072Function : bl31_plat_enable_mmu [optional]
2073~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2074
2075::
2076
2077 Argument : uint32_t
2078 Return : void
2079
2080This function enables the MMU. The boot code calls this function with MMU and
2081caches disabled. This function should program necessary registers to enable
2082translation, and upon return, the MMU on the calling PE must be enabled.
2083
2084The function must honor flags passed in the first argument. These flags are
2085defined by the translation library, and can be found in the file
2086``include/lib/xlat_tables/xlat_mmu_helpers.h``.
2087
2088On DynamIQ systems, this function must not use stack while enabling MMU, which
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002089is how the function in xlat table library version 2 is implemented.
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01002090
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002091Function : plat_init_apkey [optional]
2092~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002093
2094::
2095
2096 Argument : void
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002097 Return : uint128_t
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002098
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002099This function returns the 128-bit value which can be used to program ARMv8.3
2100pointer authentication keys.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002101
2102The value should be obtained from a reliable source of randomness.
2103
2104This function is only needed if ARMv8.3 pointer authentication is used in the
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002105Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002106
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002107Function : plat_get_syscnt_freq2() [mandatory]
2108~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002109
2110::
2111
2112 Argument : void
2113 Return : unsigned int
2114
2115This function is used by the architecture setup code to retrieve the counter
2116frequency for the CPU's generic timer. This value will be programmed into the
Dan Handley610e7e12018-03-01 18:44:00 +00002117``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002118of the system counter, which is retrieved from the first entry in the frequency
2119modes table.
2120
johpow013e24c162020-04-22 14:05:13 -05002121Function : plat_arm_set_twedel_scr_el3() [optional]
2122~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2123
2124::
2125
2126 Argument : void
2127 Return : uint32_t
2128
2129This function is used in v8.6+ systems to set the WFE trap delay value in
2130SCR_EL3. If this function returns TWED_DISABLED or is left unimplemented, this
2131feature is not enabled. The only hook provided is to set the TWED fields in
2132SCR_EL3, there are similar fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to adjust
2133the WFE trap delays in lower ELs and these fields should be set by the
2134appropriate EL2 or EL1 code depending on the platform configuration.
2135
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002136#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]
2137~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002138
2139When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in
2140bytes) aligned to the cache line boundary that should be allocated per-cpu to
2141accommodate all the bakery locks.
2142
2143If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker
2144calculates the size of the ``bakery_lock`` input section, aligns it to the
2145nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT``
2146and stores the result in a linker symbol. This constant prevents a platform
2147from relying on the linker and provide a more efficient mechanism for
2148accessing per-cpu bakery lock information.
2149
2150If this constant is defined and its value is not equal to the value
2151calculated by the linker then a link time assertion is raised. A compile time
2152assertion is raised if the value of the constant is not aligned to the cache
2153line boundary.
2154
Paul Beesleyf8640672019-04-12 14:19:42 +01002155.. _porting_guide_sdei_requirements:
2156
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002157SDEI porting requirements
2158~~~~~~~~~~~~~~~~~~~~~~~~~
2159
Paul Beesley606d8072019-03-13 13:58:02 +00002160The |SDEI| dispatcher requires the platform to provide the following macros
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002161and functions, of which some are optional, and some others mandatory.
2162
2163Macros
2164......
2165
2166Macro: PLAT_SDEI_NORMAL_PRI [mandatory]
2167^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2168
2169This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00002170Normal |SDEI| events on the platform. This must have a higher value
2171(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002172
2173Macro: PLAT_SDEI_CRITICAL_PRI [mandatory]
2174^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2175
2176This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00002177Critical |SDEI| events on the platform. This must have a lower value
2178(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002179
Paul Beesley606d8072019-03-13 13:58:02 +00002180**Note**: |SDEI| exception priorities must be the lowest among Secure
2181priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must
2182be higher than Normal |SDEI| priority.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002183
2184Functions
2185.........
2186
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002187Function: int plat_sdei_validate_entry_point() [optional]
2188^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002189
2190::
2191
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002192 Argument: uintptr_t ep, unsigned int client_mode
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002193 Return: int
2194
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002195This function validates the entry point address of the event handler provided by
2196the client for both event registration and *Complete and Resume* |SDEI| calls.
2197The function ensures that the address is valid in the client translation regime.
2198
2199The second argument is the exception level that the client is executing in. It
2200can be Non-Secure EL1 or Non-Secure EL2.
2201
2202The function must return ``0`` for successful validation, or ``-1`` upon failure.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002203
Dan Handley610e7e12018-03-01 18:44:00 +00002204The default implementation always returns ``0``. On Arm platforms, this function
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002205translates the entry point address within the client translation regime and
2206further ensures that the resulting physical address is located in Non-secure
2207DRAM.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002208
2209Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional]
2210^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2211
2212::
2213
2214 Argument: uint64_t
2215 Argument: unsigned int
2216 Return: void
2217
Paul Beesley606d8072019-03-13 13:58:02 +00002218|SDEI| specification requires that a PE comes out of reset with the events
2219masked. The client therefore is expected to call ``PE_UNMASK`` to unmask
2220|SDEI| events on the PE. No |SDEI| events can be dispatched until such
2221time.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002222
Paul Beesley606d8072019-03-13 13:58:02 +00002223Should a PE receive an interrupt that was bound to an |SDEI| event while the
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002224events are masked on the PE, the dispatcher implementation invokes the function
2225``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the
2226interrupt and the interrupt ID are passed as parameters.
2227
2228The default implementation only prints out a warning message.
2229
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -05002230.. _porting_guide_trng_requirements:
2231
2232TRNG porting requirements
2233~~~~~~~~~~~~~~~~~~~~~~~~~
2234
2235The |TRNG| backend requires the platform to provide the following values
2236and mandatory functions.
2237
2238Values
2239......
2240
2241value: uuid_t plat_trng_uuid [mandatory]
2242^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2243
2244This value must be defined to the UUID of the TRNG backend that is specific to
2245the hardware after ``plat_trng_setup`` function is called. This value must
2246conform to the SMCCC calling convention; The most significant 32 bits of the
2247UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in
2248w0 indicates failure to get a TRNG source.
2249
2250Functions
2251.........
2252
2253Function: void plat_entropy_setup(void) [mandatory]
2254^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2255
2256::
2257
2258 Argument: none
2259 Return: none
2260
2261This function is expected to do platform-specific initialization of any TRNG
2262hardware. This may include generating a UUID from a hardware-specific seed.
2263
2264Function: bool plat_get_entropy(uint64_t \*out) [mandatory]
2265^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2266
2267::
2268
2269 Argument: uint64_t *
2270 Return: bool
2271 Out : when the return value is true, the entropy has been written into the
2272 storage pointed to
2273
2274This function writes entropy into storage provided by the caller. If no entropy
2275is available, it must return false and the storage must not be written.
2276
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002277Power State Coordination Interface (in BL31)
2278--------------------------------------------
2279
Dan Handley610e7e12018-03-01 18:44:00 +00002280The TF-A implementation of the PSCI API is based around the concept of a
2281*power domain*. A *power domain* is a CPU or a logical group of CPUs which
2282share some state on which power management operations can be performed as
2283specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is
2284a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The
2285*power domains* are arranged in a hierarchical tree structure and each
2286*power domain* can be identified in a system by the cpu index of any CPU that
2287is part of that domain and a *power domain level*. A processing element (for
2288example, a CPU) is at level 0. If the *power domain* node above a CPU is a
2289logical grouping of CPUs that share some state, then level 1 is that group of
2290CPUs (for example, a cluster), and level 2 is a group of clusters (for
2291example, the system). More details on the power domain topology and its
Paul Beesleyf8640672019-04-12 14:19:42 +01002292organization can be found in :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002293
2294BL31's platform initialization code exports a pointer to the platform-specific
2295power management operations required for the PSCI implementation to function
2296correctly. This information is populated in the ``plat_psci_ops`` structure. The
2297PSCI implementation calls members of the ``plat_psci_ops`` structure for performing
2298power management operations on the power domains. For example, the target
2299CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()``
2300handler (if present) is called for the CPU power domain.
2301
2302The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to
2303describe composite power states specific to a platform. The PSCI implementation
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00002304defines a generic representation of the power-state parameter, which is an
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002305array of local power states where each index corresponds to a power domain
2306level. Each entry contains the local power state the power domain at that power
2307level could enter. It depends on the ``validate_power_state()`` handler to
2308convert the power-state parameter (possibly encoding a composite power state)
2309passed in a PSCI ``CPU_SUSPEND`` call to this representation.
2310
2311The following functions form part of platform port of PSCI functionality.
2312
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002313Function : plat_psci_stat_accounting_start() [optional]
2314~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002315
2316::
2317
2318 Argument : const psci_power_state_t *
2319 Return : void
2320
2321This is an optional hook that platforms can implement for residency statistics
2322accounting before entering a low power state. The ``pwr_domain_state`` field of
2323``state_info`` (first argument) can be inspected if stat accounting is done
2324differently at CPU level versus higher levels. As an example, if the element at
2325index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2326state, special hardware logic may be programmed in order to keep track of the
2327residency statistics. For higher levels (array indices > 0), the residency
2328statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2329default implementation will use PMF to capture timestamps.
2330
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002331Function : plat_psci_stat_accounting_stop() [optional]
2332~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002333
2334::
2335
2336 Argument : const psci_power_state_t *
2337 Return : void
2338
2339This is an optional hook that platforms can implement for residency statistics
2340accounting after exiting from a low power state. The ``pwr_domain_state`` field
2341of ``state_info`` (first argument) can be inspected if stat accounting is done
2342differently at CPU level versus higher levels. As an example, if the element at
2343index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2344state, special hardware logic may be programmed in order to keep track of the
2345residency statistics. For higher levels (array indices > 0), the residency
2346statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2347default implementation will use PMF to capture timestamps.
2348
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002349Function : plat_psci_stat_get_residency() [optional]
2350~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002351
2352::
2353
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -06002354 Argument : unsigned int, const psci_power_state_t *, unsigned int
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002355 Return : u_register_t
2356
2357This is an optional interface that is is invoked after resuming from a low power
2358state and provides the time spent resident in that low power state by the power
2359domain at a particular power domain level. When a CPU wakes up from suspend,
2360all its parent power domain levels are also woken up. The generic PSCI code
2361invokes this function for each parent power domain that is resumed and it
2362identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second
2363argument) describes the low power state that the power domain has resumed from.
2364The current CPU is the first CPU in the power domain to resume from the low
2365power state and the ``last_cpu_idx`` (third parameter) is the index of the last
2366CPU in the power domain to suspend and may be needed to calculate the residency
2367for that power domain.
2368
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002369Function : plat_get_target_pwr_state() [optional]
2370~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002371
2372::
2373
2374 Argument : unsigned int, const plat_local_state_t *, unsigned int
2375 Return : plat_local_state_t
2376
2377The PSCI generic code uses this function to let the platform participate in
2378state coordination during a power management operation. The function is passed
2379a pointer to an array of platform specific local power state ``states`` (second
2380argument) which contains the requested power state for each CPU at a particular
2381power domain level ``lvl`` (first argument) within the power domain. The function
2382is expected to traverse this array of upto ``ncpus`` (third argument) and return
2383a coordinated target power state by the comparing all the requested power
2384states. The target power state should not be deeper than any of the requested
2385power states.
2386
2387A weak definition of this API is provided by default wherein it assumes
2388that the platform assigns a local state value in order of increasing depth
2389of the power state i.e. for two power states X & Y, if X < Y
2390then X represents a shallower power state than Y. As a result, the
2391coordinated target local power state for a power domain will be the minimum
2392of the requested local power state values.
2393
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002394Function : plat_get_power_domain_tree_desc() [mandatory]
2395~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002396
2397::
2398
2399 Argument : void
2400 Return : const unsigned char *
2401
2402This function returns a pointer to the byte array containing the power domain
2403topology tree description. The format and method to construct this array are
Paul Beesleyf8640672019-04-12 14:19:42 +01002404described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI
2405initialization code requires this array to be described by the platform, either
2406statically or dynamically, to initialize the power domain topology tree. In case
2407the array is populated dynamically, then plat_core_pos_by_mpidr() and
2408plat_my_core_pos() should also be implemented suitably so that the topology tree
2409description matches the CPU indices returned by these APIs. These APIs together
2410form the platform interface for the PSCI topology framework.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002411
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002412Function : plat_setup_psci_ops() [mandatory]
2413~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002414
2415::
2416
2417 Argument : uintptr_t, const plat_psci_ops **
2418 Return : int
2419
2420This function may execute with the MMU and data caches enabled if the platform
2421port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
2422called by the primary CPU.
2423
2424This function is called by PSCI initialization code. Its purpose is to let
2425the platform layer know about the warm boot entrypoint through the
2426``sec_entrypoint`` (first argument) and to export handler routines for
2427platform-specific psci power management actions by populating the passed
2428pointer with a pointer to BL31's private ``plat_psci_ops`` structure.
2429
2430A description of each member of this structure is given below. Please refer to
Dan Handley610e7e12018-03-01 18:44:00 +00002431the Arm FVP specific implementation of these handlers in
Paul Beesleyf8640672019-04-12 14:19:42 +01002432``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002433platform wants to support, the associated operation or operations in this
2434structure must be provided and implemented (Refer section 4 of
Paul Beesleyf8640672019-04-12 14:19:42 +01002435:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI
Dan Handley610e7e12018-03-01 18:44:00 +00002436function in a platform port, the operation should be removed from this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002437structure instead of providing an empty implementation.
2438
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002439plat_psci_ops.cpu_standby()
2440...........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002441
2442Perform the platform-specific actions to enter the standby state for a cpu
2443indicated by the passed argument. This provides a fast path for CPU standby
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002444wherein overheads of PSCI state management and lock acquisition is avoided.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002445For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation,
2446the suspend state type specified in the ``power-state`` parameter should be
2447STANDBY and the target power domain level specified should be the CPU. The
2448handler should put the CPU into a low power retention state (usually by
2449issuing a wfi instruction) and ensure that it can be woken up from that
2450state by a normal interrupt. The generic code expects the handler to succeed.
2451
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002452plat_psci_ops.pwr_domain_on()
2453.............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002454
2455Perform the platform specific actions to power on a CPU, specified
2456by the ``MPIDR`` (first argument). The generic code expects the platform to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002457return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002458
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002459plat_psci_ops.pwr_domain_off()
2460..............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002461
2462Perform the platform specific actions to prepare to power off the calling CPU
2463and its higher parent power domain levels as indicated by the ``target_state``
2464(first argument). It is called by the PSCI ``CPU_OFF`` API implementation.
2465
2466The ``target_state`` encodes the platform coordinated target local power states
2467for the CPU power domain and its parent power domain levels. The handler
2468needs to perform power management operation corresponding to the local state
2469at each power level.
2470
2471For this handler, the local power state for the CPU power domain will be a
2472power down state where as it could be either power down, retention or run state
2473for the higher power domain levels depending on the result of state
2474coordination. The generic code expects the handler to succeed.
2475
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002476plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]
2477...........................................................
Varun Wadekarae87f4b2017-07-10 16:02:05 -07002478
2479This optional function may be used as a performance optimization to replace
2480or complement pwr_domain_suspend() on some platforms. Its calling semantics
2481are identical to pwr_domain_suspend(), except the PSCI implementation only
2482calls this function when suspending to a power down state, and it guarantees
2483that data caches are enabled.
2484
2485When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches
2486before calling pwr_domain_suspend(). If the target_state corresponds to a
2487power down state and it is safe to perform some or all of the platform
2488specific actions in that function with data caches enabled, it may be more
2489efficient to move those actions to this function. When HW_ASSISTED_COHERENCY
2490= 1, data caches remain enabled throughout, and so there is no advantage to
2491moving platform specific actions to this function.
2492
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002493plat_psci_ops.pwr_domain_suspend()
2494..................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002495
2496Perform the platform specific actions to prepare to suspend the calling
2497CPU and its higher parent power domain levels as indicated by the
2498``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND``
2499API implementation.
2500
2501The ``target_state`` has a similar meaning as described in
2502the ``pwr_domain_off()`` operation. It encodes the platform coordinated
2503target local power states for the CPU power domain and its parent
2504power domain levels. The handler needs to perform power management operation
2505corresponding to the local state at each power level. The generic code
2506expects the handler to succeed.
2507
Douglas Raillarda84996b2017-08-02 16:57:32 +01002508The difference between turning a power domain off versus suspending it is that
2509in the former case, the power domain is expected to re-initialize its state
2510when it is next powered on (see ``pwr_domain_on_finish()``). In the latter
2511case, the power domain is expected to save enough state so that it can resume
2512execution by restoring this state when its powered on (see
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002513``pwr_domain_suspend_finish()``).
2514
Douglas Raillarda84996b2017-08-02 16:57:32 +01002515When suspending a core, the platform can also choose to power off the GICv3
2516Redistributor and ITS through an implementation-defined sequence. To achieve
2517this safely, the ITS context must be saved first. The architectural part is
2518implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed
2519sequence is implementation defined and it is therefore the responsibility of
2520the platform code to implement the necessary sequence. Then the GIC
2521Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper.
2522Powering off the Redistributor requires the implementation to support it and it
2523is the responsibility of the platform code to execute the right implementation
2524defined sequence.
2525
2526When a system suspend is requested, the platform can also make use of the
2527``gicv3_distif_save()`` helper to save the context of the GIC Distributor after
2528it has saved the context of the Redistributors and ITS of all the cores in the
2529system. The context of the Distributor can be large and may require it to be
2530allocated in a special area if it cannot fit in the platform's global static
2531data, for example in DRAM. The Distributor can then be powered down using an
2532implementation-defined sequence.
2533
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002534plat_psci_ops.pwr_domain_pwr_down_wfi()
2535.......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002536
2537This is an optional function and, if implemented, is expected to perform
2538platform specific actions including the ``wfi`` invocation which allows the
2539CPU to powerdown. Since this function is invoked outside the PSCI locks,
2540the actions performed in this hook must be local to the CPU or the platform
2541must ensure that races between multiple CPUs cannot occur.
2542
2543The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()``
2544operation and it encodes the platform coordinated target local power states for
2545the CPU power domain and its parent power domain levels. This function must
2546not return back to the caller.
2547
2548If this function is not implemented by the platform, PSCI generic
2549implementation invokes ``psci_power_down_wfi()`` for power down.
2550
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002551plat_psci_ops.pwr_domain_on_finish()
2552....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002553
2554This function is called by the PSCI implementation after the calling CPU is
2555powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
2556It performs the platform-specific setup required to initialize enough state for
2557this CPU to enter the normal world and also provide secure runtime firmware
2558services.
2559
2560The ``target_state`` (first argument) is the prior state of the power domains
2561immediately before the CPU was turned on. It indicates which power domains
2562above the CPU might require initialization due to having previously been in
2563low power states. The generic code expects the handler to succeed.
2564
Madhukar Pappireddy33bd5142019-08-12 18:31:33 -05002565plat_psci_ops.pwr_domain_on_finish_late() [optional]
2566...........................................................
2567
2568This optional function is called by the PSCI implementation after the calling
2569CPU is fully powered on with respective data caches enabled. The calling CPU and
2570the associated cluster are guaranteed to be participating in coherency. This
2571function gives the flexibility to perform any platform-specific actions safely,
2572such as initialization or modification of shared data structures, without the
2573overhead of explicit cache maintainace operations.
2574
2575The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()``
2576operation. The generic code expects the handler to succeed.
2577
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002578plat_psci_ops.pwr_domain_suspend_finish()
2579.........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002580
2581This function is called by the PSCI implementation after the calling CPU is
2582powered on and released from reset in response to an asynchronous wakeup
2583event, for example a timer interrupt that was programmed by the CPU during the
2584``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
2585setup required to restore the saved state for this CPU to resume execution
2586in the normal world and also provide secure runtime firmware services.
2587
2588The ``target_state`` (first argument) has a similar meaning as described in
2589the ``pwr_domain_on_finish()`` operation. The generic code expects the platform
2590to succeed.
2591
Douglas Raillarda84996b2017-08-02 16:57:32 +01002592If the Distributor, Redistributors or ITS have been powered off as part of a
2593suspend, their context must be restored in this function in the reverse order
2594to how they were saved during suspend sequence.
2595
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002596plat_psci_ops.system_off()
2597..........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002598
2599This function is called by PSCI implementation in response to a ``SYSTEM_OFF``
2600call. It performs the platform-specific system poweroff sequence after
2601notifying the Secure Payload Dispatcher.
2602
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002603plat_psci_ops.system_reset()
2604............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002605
2606This function is called by PSCI implementation in response to a ``SYSTEM_RESET``
2607call. It performs the platform-specific system reset sequence after
2608notifying the Secure Payload Dispatcher.
2609
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002610plat_psci_ops.validate_power_state()
2611....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002612
2613This function is called by the PSCI implementation during the ``CPU_SUSPEND``
2614call to validate the ``power_state`` parameter of the PSCI API and if valid,
2615populate it in ``req_state`` (second argument) array as power domain level
2616specific local states. If the ``power_state`` is invalid, the platform must
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002617return PSCI_E_INVALID_PARAMS as error, which is propagated back to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002618normal world PSCI client.
2619
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002620plat_psci_ops.validate_ns_entrypoint()
2621......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002622
2623This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
2624``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point``
2625parameter passed by the normal world. If the ``entry_point`` is invalid,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002626the platform must return PSCI_E_INVALID_ADDRESS as error, which is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002627propagated back to the normal world PSCI client.
2628
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002629plat_psci_ops.get_sys_suspend_power_state()
2630...........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002631
2632This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
2633call to get the ``req_state`` parameter from platform which encodes the power
2634domain level specific local states to suspend to system affinity level. The
2635``req_state`` will be utilized to do the PSCI state coordination and
2636``pwr_domain_suspend()`` will be invoked with the coordinated target state to
2637enter system suspend.
2638
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002639plat_psci_ops.get_pwr_lvl_state_idx()
2640.....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002641
2642This is an optional function and, if implemented, is invoked by the PSCI
2643implementation to convert the ``local_state`` (first argument) at a specified
2644``pwr_lvl`` (second argument) to an index between 0 and
2645``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform
2646supports more than two local power states at each power domain level, that is
2647``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these
2648local power states.
2649
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002650plat_psci_ops.translate_power_state_by_mpidr()
2651..............................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002652
2653This is an optional function and, if implemented, verifies the ``power_state``
2654(second argument) parameter of the PSCI API corresponding to a target power
2655domain. The target power domain is identified by using both ``MPIDR`` (first
2656argument) and the power domain level encoded in ``power_state``. The power domain
2657level specific local states are to be extracted from ``power_state`` and be
2658populated in the ``output_state`` (third argument) array. The functionality
2659is similar to the ``validate_power_state`` function described above and is
2660envisaged to be used in case the validity of ``power_state`` depend on the
2661targeted power domain. If the ``power_state`` is invalid for the targeted power
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002662domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002663function is not implemented, then the generic implementation relies on
2664``validate_power_state`` function to translate the ``power_state``.
2665
2666This function can also be used in case the platform wants to support local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002667power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002668APIs as described in Section 5.18 of `PSCI`_.
2669
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002670plat_psci_ops.get_node_hw_state()
2671.................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002672
2673This is an optional function. If implemented this function is intended to return
2674the power state of a node (identified by the first parameter, the ``MPIDR``) in
2675the power domain topology (identified by the second parameter, ``power_level``),
2676as retrieved from a power controller or equivalent component on the platform.
2677Upon successful completion, the implementation must map and return the final
2678status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it
2679must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as
2680appropriate.
2681
2682Implementations are not expected to handle ``power_levels`` greater than
2683``PLAT_MAX_PWR_LVL``.
2684
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002685plat_psci_ops.system_reset2()
2686.............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002687
2688This is an optional function. If implemented this function is
2689called during the ``SYSTEM_RESET2`` call to perform a reset
2690based on the first parameter ``reset_type`` as specified in
2691`PSCI`_. The parameter ``cookie`` can be used to pass additional
2692reset information. If the ``reset_type`` is not supported, the
2693function must return ``PSCI_E_NOT_SUPPORTED``. For architectural
2694resets, all failures must return ``PSCI_E_INVALID_PARAMETERS``
2695and vendor reset can return other PSCI error codes as defined
2696in `PSCI`_. On success this function will not return.
2697
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002698plat_psci_ops.write_mem_protect()
2699.................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002700
2701This is an optional function. If implemented it enables or disables the
2702``MEM_PROTECT`` functionality based on the value of ``val``.
2703A non-zero value enables ``MEM_PROTECT`` and a value of zero
2704disables it. Upon encountering failures it must return a negative value
2705and on success it must return 0.
2706
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002707plat_psci_ops.read_mem_protect()
2708................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002709
2710This is an optional function. If implemented it returns the current
2711state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering
2712failures it must return a negative value and on success it must
2713return 0.
2714
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002715plat_psci_ops.mem_protect_chk()
2716...............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002717
2718This is an optional function. If implemented it checks if a memory
2719region defined by a base address ``base`` and with a size of ``length``
2720bytes is protected by ``MEM_PROTECT``. If the region is protected
2721then it must return 0, otherwise it must return a negative number.
2722
Paul Beesleyf8640672019-04-12 14:19:42 +01002723.. _porting_guide_imf_in_bl31:
2724
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002725Interrupt Management framework (in BL31)
2726----------------------------------------
2727
2728BL31 implements an Interrupt Management Framework (IMF) to manage interrupts
2729generated in either security state and targeted to EL1 or EL2 in the non-secure
2730state or EL3/S-EL1 in the secure state. The design of this framework is
Paul Beesleyf8640672019-04-12 14:19:42 +01002731described in the :ref:`Interrupt Management Framework`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002732
2733A platform should export the following APIs to support the IMF. The following
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002734text briefly describes each API and its implementation in Arm standard
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002735platforms. The API implementation depends upon the type of interrupt controller
Dan Handley610e7e12018-03-01 18:44:00 +00002736present in the platform. Arm standard platform layer supports both
2737`Arm Generic Interrupt Controller version 2.0 (GICv2)`_
2738and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the
2739FVP can be configured to use either GICv2 or GICv3 depending on the build flag
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01002740``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more
2741details).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002742
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05002743See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`.
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002744
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002745Function : plat_interrupt_type_to_line() [mandatory]
2746~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002747
2748::
2749
2750 Argument : uint32_t, uint32_t
2751 Return : uint32_t
2752
Dan Handley610e7e12018-03-01 18:44:00 +00002753The Arm processor signals an interrupt exception either through the IRQ or FIQ
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002754interrupt line. The specific line that is signaled depends on how the interrupt
2755controller (IC) reports different interrupt types from an execution context in
2756either security state. The IMF uses this API to determine which interrupt line
2757the platform IC uses to signal each type of interrupt supported by the framework
2758from a given security state. This API must be invoked at EL3.
2759
2760The first parameter will be one of the ``INTR_TYPE_*`` values (see
Paul Beesleyf8640672019-04-12 14:19:42 +01002761:ref:`Interrupt Management Framework`) indicating the target type of the
2762interrupt, the second parameter is the security state of the originating
2763execution context. The return result is the bit position in the ``SCR_EL3``
2764register of the respective interrupt trap: IRQ=1, FIQ=2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002765
Dan Handley610e7e12018-03-01 18:44:00 +00002766In the case of Arm standard platforms using GICv2, S-EL1 interrupts are
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002767configured as FIQs and Non-secure interrupts as IRQs from either security
2768state.
2769
Dan Handley610e7e12018-03-01 18:44:00 +00002770In the case of Arm standard platforms using GICv3, the interrupt line to be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002771configured depends on the security state of the execution context when the
2772interrupt is signalled and are as follows:
2773
2774- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in
2775 NS-EL0/1/2 context.
2776- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ
2777 in the NS-EL0/1/2 context.
2778- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2
2779 context.
2780
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002781Function : plat_ic_get_pending_interrupt_type() [mandatory]
2782~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002783
2784::
2785
2786 Argument : void
2787 Return : uint32_t
2788
2789This API returns the type of the highest priority pending interrupt at the
2790platform IC. The IMF uses the interrupt type to retrieve the corresponding
2791handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt
2792pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``,
2793``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3.
2794
Dan Handley610e7e12018-03-01 18:44:00 +00002795In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002796Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of
2797the pending interrupt. The type of interrupt depends upon the id value as
2798follows.
2799
2800#. id < 1022 is reported as a S-EL1 interrupt
2801#. id = 1022 is reported as a Non-secure interrupt.
2802#. id = 1023 is reported as an invalid interrupt type.
2803
Dan Handley610e7e12018-03-01 18:44:00 +00002804In the case of Arm standard platforms using GICv3, the system register
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002805``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*,
2806is read to determine the id of the pending interrupt. The type of interrupt
2807depends upon the id value as follows.
2808
2809#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt
2810#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt.
2811#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type.
2812#. All other interrupt id's are reported as EL3 interrupt.
2813
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002814Function : plat_ic_get_pending_interrupt_id() [mandatory]
2815~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002816
2817::
2818
2819 Argument : void
2820 Return : uint32_t
2821
2822This API returns the id of the highest priority pending interrupt at the
2823platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt
2824pending.
2825
Dan Handley610e7e12018-03-01 18:44:00 +00002826In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002827Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the
2828pending interrupt. The id that is returned by API depends upon the value of
2829the id read from the interrupt controller as follows.
2830
2831#. id < 1022. id is returned as is.
2832#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register*
2833 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt.
2834 This id is returned by the API.
2835#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned.
2836
Dan Handley610e7e12018-03-01 18:44:00 +00002837In the case of Arm standard platforms using GICv3, if the API is invoked from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002838EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt
2839group 0 Register*, is read to determine the id of the pending interrupt. The id
2840that is returned by API depends upon the value of the id read from the
2841interrupt controller as follows.
2842
2843#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is.
2844#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system
2845 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1
2846 Register* is read to determine the id of the group 1 interrupt. This id
2847 is returned by the API as long as it is a valid interrupt id
2848#. If the id is any of the special interrupt identifiers,
2849 ``INTR_ID_UNAVAILABLE`` is returned.
2850
2851When the API invoked from S-EL1 for GICv3 systems, the id read from system
2852register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002853Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002854``INTR_ID_UNAVAILABLE`` is returned.
2855
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002856Function : plat_ic_acknowledge_interrupt() [mandatory]
2857~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002858
2859::
2860
2861 Argument : void
2862 Return : uint32_t
2863
2864This API is used by the CPU to indicate to the platform IC that processing of
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002865the highest pending interrupt has begun. It should return the raw, unmodified
2866value obtained from the interrupt controller when acknowledging an interrupt.
2867The actual interrupt number shall be extracted from this raw value using the API
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05002868`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002869
Dan Handley610e7e12018-03-01 18:44:00 +00002870This function in Arm standard platforms using GICv2, reads the *Interrupt
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002871Acknowledge Register* (``GICC_IAR``). This changes the state of the highest
2872priority pending interrupt from pending to active in the interrupt controller.
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002873It returns the value read from the ``GICC_IAR``, unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002874
Dan Handley610e7e12018-03-01 18:44:00 +00002875In the case of Arm standard platforms using GICv3, if the API is invoked
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002876from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt
2877Acknowledge Register group 0*. If the API is invoked from S-EL1, the function
2878reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register
2879group 1*. The read changes the state of the highest pending interrupt from
2880pending to active in the interrupt controller. The value read is returned
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002881unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002882
2883The TSP uses this API to start processing of the secure physical timer
2884interrupt.
2885
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002886Function : plat_ic_end_of_interrupt() [mandatory]
2887~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002888
2889::
2890
2891 Argument : uint32_t
2892 Return : void
2893
2894This API is used by the CPU to indicate to the platform IC that processing of
2895the interrupt corresponding to the id (passed as the parameter) has
2896finished. The id should be the same as the id returned by the
2897``plat_ic_acknowledge_interrupt()`` API.
2898
Dan Handley610e7e12018-03-01 18:44:00 +00002899Arm standard platforms write the id to the *End of Interrupt Register*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002900(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1``
2901system register in case of GICv3 depending on where the API is invoked from,
2902EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt
2903controller.
2904
2905The TSP uses this API to finish processing of the secure physical timer
2906interrupt.
2907
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002908Function : plat_ic_get_interrupt_type() [mandatory]
2909~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002910
2911::
2912
2913 Argument : uint32_t
2914 Return : uint32_t
2915
2916This API returns the type of the interrupt id passed as the parameter.
2917``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid
2918interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is
2919returned depending upon how the interrupt has been configured by the platform
2920IC. This API must be invoked at EL3.
2921
Dan Handley610e7e12018-03-01 18:44:00 +00002922Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002923and Non-secure interrupts as Group1 interrupts. It reads the group value
2924corresponding to the interrupt id from the relevant *Interrupt Group Register*
2925(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt.
2926
Dan Handley610e7e12018-03-01 18:44:00 +00002927In the case of Arm standard platforms using GICv3, both the *Interrupt Group
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002928Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register*
2929(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured
2930as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt.
2931
2932Crash Reporting mechanism (in BL31)
2933-----------------------------------
2934
2935BL31 implements a crash reporting mechanism which prints the various registers
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002936of the CPU to enable quick crash analysis and debugging. This mechanism relies
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002937on the platform implementing ``plat_crash_console_init``,
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002938``plat_crash_console_putc`` and ``plat_crash_console_flush``.
2939
2940The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample
2941implementation of all of them. Platforms may include this file to their
2942makefiles in order to benefit from them. By default, they will cause the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07002943output to be routed over the normal console infrastructure and get printed on
2944consoles configured to output in crash state. ``console_set_scope()`` can be
2945used to control whether a console is used for crash output.
Paul Beesleyba3ed402019-03-13 16:20:44 +00002946
2947.. note::
2948 Platforms are responsible for making sure that they only mark consoles for
2949 use in the crash scope that are able to support this, i.e. that are written
2950 in assembly and conform with the register clobber rules for putc()
2951 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002952
Julius Werneraae9bb12017-09-18 16:49:48 -07002953In some cases (such as debugging very early crashes that happen before the
2954normal boot console can be set up), platforms may want to control crash output
Julius Werner1338c9c2018-11-19 14:25:55 -08002955more explicitly. These platforms may instead provide custom implementations for
2956these. They are executed outside of a C environment and without a stack. Many
2957console drivers provide functions named ``console_xxx_core_init/putc/flush``
2958that are designed to be used by these functions. See Arm platforms (like juno)
2959for an example of this.
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002960
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002961Function : plat_crash_console_init [mandatory]
2962~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002963
2964::
2965
2966 Argument : void
2967 Return : int
2968
2969This API is used by the crash reporting mechanism to initialize the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07002970console. It must only use the general purpose registers x0 through x7 to do the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002971initialization and returns 1 on success.
2972
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002973Function : plat_crash_console_putc [mandatory]
2974~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002975
2976::
2977
2978 Argument : int
2979 Return : int
2980
2981This API is used by the crash reporting mechanism to print a character on the
2982designated crash console. It must only use general purpose registers x1 and
2983x2 to do its work. The parameter and the return value are in general purpose
2984register x0.
2985
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002986Function : plat_crash_console_flush [mandatory]
2987~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002988
2989::
2990
2991 Argument : void
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05002992 Return : void
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002993
2994This API is used by the crash reporting mechanism to force write of all buffered
2995data on the designated crash console. It should only use general purpose
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05002996registers x0 through x5 to do its work.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002997
Manish Pandey9c9f38a2020-06-30 00:46:08 +01002998.. _External Abort handling and RAS Support:
2999
Jeenu Viswambharane34bf582018-10-12 08:48:36 +01003000External Abort handling and RAS Support
3001---------------------------------------
Jeenu Viswambharanbf235bc2018-07-12 10:00:01 +01003002
3003Function : plat_ea_handler
3004~~~~~~~~~~~~~~~~~~~~~~~~~~
3005
3006::
3007
3008 Argument : int
3009 Argument : uint64_t
3010 Argument : void *
3011 Argument : void *
3012 Argument : uint64_t
3013 Return : void
3014
3015This function is invoked by the RAS framework for the platform to handle an
3016External Abort received at EL3. The intention of the function is to attempt to
3017resolve the cause of External Abort and return; if that's not possible, to
3018initiate orderly shutdown of the system.
3019
3020The first parameter (``int ea_reason``) indicates the reason for External Abort.
3021Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``.
3022
3023The second parameter (``uint64_t syndrome``) is the respective syndrome
3024presented to EL3 after having received the External Abort. Depending on the
3025nature of the abort (as can be inferred from the ``ea_reason`` parameter), this
3026can be the content of either ``ESR_EL3`` or ``DISR_EL1``.
3027
3028The third parameter (``void *cookie``) is unused for now. The fourth parameter
3029(``void *handle``) is a pointer to the preempted context. The fifth parameter
3030(``uint64_t flags``) indicates the preempted security state. These parameters
3031are received from the top-level exception handler.
3032
3033If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this
3034function iterates through RAS handlers registered by the platform. If any of the
3035RAS handlers resolve the External Abort, no further action is taken.
3036
3037If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers
3038could resolve the External Abort, the default implementation prints an error
3039message, and panics.
3040
3041Function : plat_handle_uncontainable_ea
3042~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3043
3044::
3045
3046 Argument : int
3047 Argument : uint64_t
3048 Return : void
3049
3050This function is invoked by the RAS framework when an External Abort of
3051Uncontainable type is received at EL3. Due to the critical nature of
3052Uncontainable errors, the intention of this function is to initiate orderly
3053shutdown of the system, and is not expected to return.
3054
3055This function must be implemented in assembly.
3056
3057The first and second parameters are the same as that of ``plat_ea_handler``.
3058
3059The default implementation of this function calls
3060``report_unhandled_exception``.
3061
3062Function : plat_handle_double_fault
3063~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3064
3065::
3066
3067 Argument : int
3068 Argument : uint64_t
3069 Return : void
3070
3071This function is invoked by the RAS framework when another External Abort is
3072received at EL3 while one is already being handled. I.e., a call to
3073``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of
3074this function is to initiate orderly shutdown of the system, and is not expected
3075recover or return.
3076
3077This function must be implemented in assembly.
3078
3079The first and second parameters are the same as that of ``plat_ea_handler``.
3080
3081The default implementation of this function calls
3082``report_unhandled_exception``.
3083
3084Function : plat_handle_el3_ea
3085~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3086
3087::
3088
3089 Return : void
3090
3091This function is invoked when an External Abort is received while executing in
3092EL3. Due to its critical nature, the intention of this function is to initiate
3093orderly shutdown of the system, and is not expected recover or return.
3094
3095This function must be implemented in assembly.
3096
3097The default implementation of this function calls
3098``report_unhandled_exception``.
3099
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003100Build flags
3101-----------
3102
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003103There are some build flags which can be defined by the platform to control
3104inclusion or exclusion of certain BL stages from the FIP image. These flags
3105need to be defined in the platform makefile which will get included by the
3106build system.
3107
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003108- **NEED_BL33**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003109 By default, this flag is defined ``yes`` by the build system and ``BL33``
3110 build option should be supplied as a build option. The platform has the
3111 option of excluding the BL33 image in the ``fip`` image by defining this flag
3112 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE``
3113 are used, this flag will be set to ``no`` automatically.
3114
Paul Beesley07f0a312019-05-16 13:33:18 +01003115Platform include paths
3116----------------------
3117
3118Platforms are allowed to add more include paths to be passed to the compiler.
3119The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in
3120particular for the file ``platform_def.h``.
3121
3122Example:
3123
3124.. code:: c
3125
3126 PLAT_INCLUDES += -Iinclude/plat/myplat/include
3127
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003128C Library
3129---------
3130
3131To avoid subtle toolchain behavioral dependencies, the header files provided
3132by the compiler are not used. The software is built with the ``-nostdinc`` flag
3133to ensure no headers are included from the toolchain inadvertently. Instead the
Dan Handley610e7e12018-03-01 18:44:00 +00003134required headers are included in the TF-A source tree. The library only
3135contains those C library definitions required by the local implementation. If
3136more functionality is required, the needed library functions will need to be
3137added to the local implementation.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003138
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003139Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have
Paul Beesleyf2ec7142019-10-04 16:17:46 +00003140been written specifically for TF-A. Some implementation files have been obtained
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003141from `FreeBSD`_, others have been written specifically for TF-A as well. The
3142files can be found in ``include/lib/libc`` and ``lib/libc``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003143
Sandrine Bailleux6f0ecd72019-02-08 14:46:42 +01003144SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources
3145can be obtained from http://github.com/freebsd/freebsd.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003146
3147Storage abstraction layer
3148-------------------------
3149
Louis Mayencourtb5469002019-07-15 13:56:03 +01003150In order to improve platform independence and portability a storage abstraction
3151layer is used to load data from non-volatile platform storage. Currently
3152storage access is only required by BL1 and BL2 phases and performed inside the
3153``load_image()`` function in ``bl_common.c``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003154
Louis Mayencourtb5469002019-07-15 13:56:03 +01003155.. uml:: ../resources/diagrams/plantuml/io_framework_usage_overview.puml
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003156
Dan Handley610e7e12018-03-01 18:44:00 +00003157It is mandatory to implement at least one storage driver. For the Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003158development platforms the Firmware Image Package (FIP) driver is provided as
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01003159the default means to load data from storage (see :ref:`firmware_design_fip`).
3160The storage layer is described in the header file
3161``include/drivers/io/io_storage.h``. The implementation of the common library is
3162in ``drivers/io/io_storage.c`` and the driver files are located in
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003163``drivers/io/``.
3164
Louis Mayencourtb5469002019-07-15 13:56:03 +01003165.. uml:: ../resources/diagrams/plantuml/io_arm_class_diagram.puml
3166
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003167Each IO driver must provide ``io_dev_*`` structures, as described in
3168``drivers/io/io_driver.h``. These are returned via a mandatory registration
3169function that is called on platform initialization. The semi-hosting driver
3170implementation in ``io_semihosting.c`` can be used as an example.
3171
Louis Mayencourtb5469002019-07-15 13:56:03 +01003172Each platform should register devices and their drivers via the storage
3173abstraction layer. These drivers then need to be initialized by bootloader
3174phases as required in their respective ``blx_platform_setup()`` functions.
3175
3176.. uml:: ../resources/diagrams/plantuml/io_dev_registration.puml
3177
3178The storage abstraction layer provides mechanisms (``io_dev_init()``) to
3179initialize storage devices before IO operations are called.
3180
3181.. uml:: ../resources/diagrams/plantuml/io_dev_init_and_check.puml
3182
3183The basic operations supported by the layer
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003184include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``.
3185Drivers do not have to implement all operations, but each platform must
3186provide at least one driver for a device capable of supporting generic
3187operations such as loading a bootloader image.
3188
3189The current implementation only allows for known images to be loaded by the
3190firmware. These images are specified by using their identifiers, as defined in
Antonio Nino Diaz645feb42019-02-13 14:07:38 +00003191``include/plat/common/common_def.h`` (or a separate header file included from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003192there). The platform layer (``plat_get_image_source()``) then returns a reference
3193to a device and a driver-specific ``spec`` which will be understood by the driver
3194to allow access to the image data.
3195
3196The layer is designed in such a way that is it possible to chain drivers with
3197other drivers. For example, file-system drivers may be implemented on top of
3198physical block devices, both represented by IO devices with corresponding
3199drivers. In such a case, the file-system "binding" with the block device may
3200be deferred until the file-system device is initialised.
3201
3202The abstraction currently depends on structures being statically allocated
3203by the drivers and callers, as the system does not yet provide a means of
3204dynamically allocating memory. This may also have the affect of limiting the
3205amount of open resources per driver.
3206
3207--------------
3208
Soby Mathewf05d93a2022-03-22 16:21:19 +00003209*Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003210
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003211.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
Dan Handley610e7e12018-03-01 18:44:00 +00003212.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003213.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html
Paul Beesley2437ddc2019-02-08 16:43:05 +00003214.. _FreeBSD: https://www.freebsd.org
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003215.. _SCC: http://www.simple-cc.org/