blob: ae3ffb5542d352f716cf994c7bdcd922c7ceafc5 [file] [log] [blame]
Paul Beesleyfc9ee362019-03-07 15:47:15 +00001Porting Guide
2=============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Douglas Raillardd7c21b72017-06-28 15:23:03 +01004Introduction
5------------
6
Dan Handley610e7e12018-03-01 18:44:00 +00007Porting Trusted Firmware-A (TF-A) to a new platform involves making some
Douglas Raillardd7c21b72017-06-28 15:23:03 +01008mandatory and optional modifications for both the cold and warm boot paths.
9Modifications consist of:
10
11- Implementing a platform-specific function or variable,
12- Setting up the execution context in a certain way, or
13- Defining certain constants (for example #defines).
14
15The platform-specific functions and variables are declared in
Paul Beesleyf8640672019-04-12 14:19:42 +010016``include/plat/common/platform.h``. The firmware provides a default
Sandrine Bailleux7a53a912023-02-08 13:55:51 +010017implementation of variables and functions to fulfill the optional requirements
18in order to ease the porting effort. Each platform port can use them as is or
19provide their own implementation if the default implementation is inadequate.
20
21 .. note::
22
23 TF-A historically provided default implementations of platform interfaces
24 as *weak* functions. This practice is now discouraged and new platform
25 interfaces as they get introduced in the code base should be *strongly*
26 defined. We intend to convert existing weak functions over time. Until
27 then, you will find references to *weak* functions in this document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010028
Douglas Raillardd7c21b72017-06-28 15:23:03 +010029Some modifications are common to all Boot Loader (BL) stages. Section 2
30discusses these in detail. The subsequent sections discuss the remaining
31modifications for each BL stage in detail.
32
Sandrine Bailleuxdad35612022-11-08 13:36:42 +010033Please refer to the :ref:`Platform Ports Policy` for the policy regarding
34compatibility and deprecation of these porting interfaces.
Soby Mathew02bdbb92018-09-26 11:17:23 +010035
Antonio Nino Diaz645feb42019-02-13 14:07:38 +000036Only Arm development platforms (such as FVP and Juno) may use the
37functions/definitions in ``include/plat/arm/common/`` and the corresponding
38source files in ``plat/arm/common/``. This is done so that there are no
39dependencies between platforms maintained by different people/companies. If you
40want to use any of the functionality present in ``plat/arm`` files, please
41create a pull request that moves the code to ``plat/common`` so that it can be
42discussed.
43
Douglas Raillardd7c21b72017-06-28 15:23:03 +010044Common modifications
45--------------------
46
47This section covers the modifications that should be made by the platform for
48each BL stage to correctly port the firmware stack. They are categorized as
49either mandatory or optional.
50
51Common mandatory modifications
52------------------------------
53
54A platform port must enable the Memory Management Unit (MMU) as well as the
55instruction and data caches for each BL stage. Setting up the translation
56tables is the responsibility of the platform port because memory maps differ
57across platforms. A memory translation library (see ``lib/xlat_tables/``) is
Sandrine Bailleux1861b7a2017-07-20 16:11:01 +010058provided to help in this setup.
59
60Note that although this library supports non-identity mappings, this is intended
61only for re-mapping peripheral physical addresses and allows platforms with high
62I/O addresses to reduce their virtual address space. All other addresses
63corresponding to code and data must currently use an identity mapping.
64
Dan Handley610e7e12018-03-01 18:44:00 +000065Also, the only translation granule size supported in TF-A is 4KB, as various
66parts of the code assume that is the case. It is not possible to switch to
6716 KB or 64 KB granule sizes at the moment.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010068
Dan Handley610e7e12018-03-01 18:44:00 +000069In Arm standard platforms, each BL stage configures the MMU in the
Douglas Raillardd7c21b72017-06-28 15:23:03 +010070platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses
71an identity mapping for all addresses.
72
73If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a
74block of identity mapped secure memory with Device-nGnRE attributes aligned to
75page boundary (4K) for each BL stage. All sections which allocate coherent
Chris Kay33bfc5e2023-02-14 11:30:04 +000076memory are grouped under ``.coherent_ram``. For ex: Bakery locks are placed in a
77section identified by name ``.bakery_lock`` inside ``.coherent_ram`` so that its
Douglas Raillardd7c21b72017-06-28 15:23:03 +010078possible for the firmware to place variables in it using the following C code
79directive:
80
81::
82
Chris Kay33bfc5e2023-02-14 11:30:04 +000083 __section(".bakery_lock")
Douglas Raillardd7c21b72017-06-28 15:23:03 +010084
85Or alternatively the following assembler code directive:
86
87::
88
Chris Kay33bfc5e2023-02-14 11:30:04 +000089 .section .bakery_lock
Douglas Raillardd7c21b72017-06-28 15:23:03 +010090
Chris Kay33bfc5e2023-02-14 11:30:04 +000091The ``.coherent_ram`` section is a sum of all sections like ``.bakery_lock`` which are
Douglas Raillardd7c21b72017-06-28 15:23:03 +010092used to allocate any data structures that are accessed both when a CPU is
93executing with its MMU and caches enabled, and when it's running with its MMU
94and caches disabled. Examples are given below.
95
96The following variables, functions and constants must be defined by the platform
97for the firmware to work correctly.
98
Javier Almansa Sobrino37bf69c2022-04-07 18:26:49 +010099.. _platform_def_mandatory:
100
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100101File : platform_def.h [mandatory]
102~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100103
104Each platform must ensure that a header file of this name is in the system
Antonio Nino Diaz50a4d1a2019-02-01 12:22:22 +0000105include path with the following constants defined. This will require updating
106the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100107
Paul Beesleyf8640672019-04-12 14:19:42 +0100108Platform ports may optionally use the file ``include/plat/common/common_def.h``,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100109which provides typical values for some of the constants below. These values are
110likely to be suitable for all platform ports.
111
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100112- **#define : PLATFORM_LINKER_FORMAT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100113
114 Defines the linker format used by the platform, for example
115 ``elf64-littleaarch64``.
116
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100117- **#define : PLATFORM_LINKER_ARCH**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100118
119 Defines the processor architecture for the linker by the platform, for
120 example ``aarch64``.
121
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100122- **#define : PLATFORM_STACK_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100123
124 Defines the normal stack memory available to each CPU. This constant is used
Paul Beesleyf8640672019-04-12 14:19:42 +0100125 by ``plat/common/aarch64/platform_mp_stack.S`` and
126 ``plat/common/aarch64/platform_up_stack.S``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100127
David Horstmann051fd6d2020-11-12 15:19:04 +0000128- **#define : CACHE_WRITEBACK_GRANULE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100129
Max Yufa0b4e82022-09-08 23:21:21 +0000130 Defines the size in bytes of the largest cache line across all the cache
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100131 levels in the platform.
132
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100133- **#define : FIRMWARE_WELCOME_STR**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100134
135 Defines the character string printed by BL1 upon entry into the ``bl1_main()``
136 function.
137
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100138- **#define : PLATFORM_CORE_COUNT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100139
140 Defines the total number of CPUs implemented by the platform across all
141 clusters in the system.
142
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100143- **#define : PLAT_NUM_PWR_DOMAINS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100144
145 Defines the total number of nodes in the power domain topology
146 tree at all the power domain levels used by the platform.
147 This macro is used by the PSCI implementation to allocate
148 data structures to represent power domain topology.
149
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100150- **#define : PLAT_MAX_PWR_LVL**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100151
152 Defines the maximum power domain level that the power management operations
153 should apply to. More often, but not always, the power domain level
154 corresponds to affinity level. This macro allows the PSCI implementation
155 to know the highest power domain level that it should consider for power
156 management operations in the system that the platform implements. For
157 example, the Base AEM FVP implements two clusters with a configurable
158 number of CPUs and it reports the maximum power domain level as 1.
159
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100160- **#define : PLAT_MAX_OFF_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100161
162 Defines the local power state corresponding to the deepest power down
163 possible at every power domain level in the platform. The local power
164 states for each level may be sparsely allocated between 0 and this value
165 with 0 being reserved for the RUN state. The PSCI implementation uses this
166 value to initialize the local power states of the power domain nodes and
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100167 to specify the requested power state for a PSCI_CPU_OFF call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100168
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100169- **#define : PLAT_MAX_RET_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100170
171 Defines the local power state corresponding to the deepest retention state
172 possible at every power domain level in the platform. This macro should be
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100173 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100174 PSCI implementation to distinguish between retention and power down local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100175 power states within PSCI_CPU_SUSPEND call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100176
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100177- **#define : PLAT_MAX_PWR_LVL_STATES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100178
179 Defines the maximum number of local power states per power domain level
180 that the platform supports. The default value of this macro is 2 since
181 most platforms just support a maximum of two local power states at each
182 power domain level (power-down and retention). If the platform needs to
183 account for more local power states, then it must redefine this macro.
184
185 Currently, this macro is used by the Generic PSCI implementation to size
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100186 the array used for PSCI_STAT_COUNT/RESIDENCY accounting.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100187
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100188- **#define : BL1_RO_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100189
190 Defines the base address in secure ROM where BL1 originally lives. Must be
191 aligned on a page-size boundary.
192
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100193- **#define : BL1_RO_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100194
195 Defines the maximum address in secure ROM that BL1's actual content (i.e.
196 excluding any data section allocated at runtime) can occupy.
197
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100198- **#define : BL1_RW_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100199
200 Defines the base address in secure RAM where BL1's read-write data will live
201 at runtime. Must be aligned on a page-size boundary.
202
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100203- **#define : BL1_RW_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100204
205 Defines the maximum address in secure RAM that BL1's read-write data can
206 occupy at runtime.
207
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100208- **#define : BL2_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100209
210 Defines the base address in secure RAM where BL1 loads the BL2 binary image.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000211 Must be aligned on a page-size boundary. This constant is not applicable
212 when BL2_IN_XIP_MEM is set to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100213
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100214- **#define : BL2_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100215
216 Defines the maximum address in secure RAM that the BL2 image can occupy.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000217 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'.
218
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100219- **#define : BL2_RO_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000220
221 Defines the base address in secure XIP memory where BL2 RO section originally
222 lives. Must be aligned on a page-size boundary. This constant is only needed
223 when BL2_IN_XIP_MEM is set to '1'.
224
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100225- **#define : BL2_RO_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000226
227 Defines the maximum address in secure XIP memory that BL2's actual content
228 (i.e. excluding any data section allocated at runtime) can occupy. This
229 constant is only needed when BL2_IN_XIP_MEM is set to '1'.
230
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100231- **#define : BL2_RW_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000232
233 Defines the base address in secure RAM where BL2's read-write data will live
234 at runtime. Must be aligned on a page-size boundary. This constant is only
235 needed when BL2_IN_XIP_MEM is set to '1'.
236
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100237- **#define : BL2_RW_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000238
239 Defines the maximum address in secure RAM that BL2's read-write data can
240 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set
241 to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100242
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100243- **#define : BL31_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100244
245 Defines the base address in secure RAM where BL2 loads the BL31 binary
246 image. Must be aligned on a page-size boundary.
247
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100248- **#define : BL31_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100249
250 Defines the maximum address in secure RAM that the BL31 image can occupy.
251
Tamas Ban1d3354e2022-09-16 14:09:30 +0200252- **#define : PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE**
253
254 Defines the maximum message size between AP and RSS. Need to define if
255 platform supports RSS.
256
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100257For every image, the platform must define individual identifiers that will be
258used by BL1 or BL2 to load the corresponding image into memory from non-volatile
259storage. For the sake of performance, integer numbers will be used as
260identifiers. The platform will use those identifiers to return the relevant
261information about the image to be loaded (file handler, load address,
262authentication information, etc.). The following image identifiers are
263mandatory:
264
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100265- **#define : BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100266
267 BL2 image identifier, used by BL1 to load BL2.
268
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100269- **#define : BL31_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100270
271 BL31 image identifier, used by BL2 to load BL31.
272
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100273- **#define : BL33_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100274
275 BL33 image identifier, used by BL2 to load BL33.
276
277If Trusted Board Boot is enabled, the following certificate identifiers must
278also be defined:
279
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100280- **#define : TRUSTED_BOOT_FW_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100281
282 BL2 content certificate identifier, used by BL1 to load the BL2 content
283 certificate.
284
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100285- **#define : TRUSTED_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100286
287 Trusted key certificate identifier, used by BL2 to load the trusted key
288 certificate.
289
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100290- **#define : SOC_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100291
292 BL31 key certificate identifier, used by BL2 to load the BL31 key
293 certificate.
294
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100295- **#define : SOC_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100296
297 BL31 content certificate identifier, used by BL2 to load the BL31 content
298 certificate.
299
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100300- **#define : NON_TRUSTED_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100301
302 BL33 key certificate identifier, used by BL2 to load the BL33 key
303 certificate.
304
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100305- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100306
307 BL33 content certificate identifier, used by BL2 to load the BL33 content
308 certificate.
309
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100310- **#define : FWU_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100311
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100312 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100313 FWU content certificate.
314
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100315- **#define : PLAT_CRYPTOCELL_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100316
Dan Handley610e7e12018-03-01 18:44:00 +0000317 This defines the base address of Arm® TrustZone® CryptoCell and must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100318 defined if CryptoCell crypto driver is used for Trusted Board Boot. For
Dan Handley610e7e12018-03-01 18:44:00 +0000319 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100320 set.
321
322If the AP Firmware Updater Configuration image, BL2U is used, the following
323must also be defined:
324
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100325- **#define : BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100326
327 Defines the base address in secure memory where BL1 copies the BL2U binary
328 image. Must be aligned on a page-size boundary.
329
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100330- **#define : BL2U_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100331
332 Defines the maximum address in secure memory that the BL2U image can occupy.
333
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100334- **#define : BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100335
336 BL2U image identifier, used by BL1 to fetch an image descriptor
337 corresponding to BL2U.
338
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100339If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100340must also be defined:
341
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100342- **#define : SCP_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100343
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100344 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor
345 corresponding to SCP_BL2U.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000346
347 .. note::
348 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100349
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100350If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100351also be defined:
352
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100353- **#define : NS_BL1U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100354
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100355 Defines the base address in non-secure ROM where NS_BL1U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100356 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000357
358 .. note::
359 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100360
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100361- **#define : NS_BL1U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100362
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100363 NS_BL1U image identifier, used by BL1 to fetch an image descriptor
364 corresponding to NS_BL1U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100365
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100366If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100367be defined:
368
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100369- **#define : NS_BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100370
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100371 Defines the base address in non-secure memory where NS_BL2U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100372 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000373
374 .. note::
375 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100376
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100377- **#define : NS_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100378
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100379 NS_BL2U image identifier, used by BL1 to fetch an image descriptor
380 corresponding to NS_BL2U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100381
382For the the Firmware update capability of TRUSTED BOARD BOOT, the following
383macros may also be defined:
384
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100385- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100386
387 Total number of images that can be loaded simultaneously. If the platform
388 doesn't specify any value, it defaults to 10.
389
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100390If a SCP_BL2 image is supported by the platform, the following constants must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100391also be defined:
392
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100393- **#define : SCP_BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100394
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100395 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000396 from platform storage before being transferred to the SCP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100397
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100398- **#define : SCP_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100399
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100400 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100401 certificate (mandatory when Trusted Board Boot is enabled).
402
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100403- **#define : SCP_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100404
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100405 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100406 content certificate (mandatory when Trusted Board Boot is enabled).
407
408If a BL32 image is supported by the platform, the following constants must
409also be defined:
410
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100411- **#define : BL32_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100412
413 BL32 image identifier, used by BL2 to load BL32.
414
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100415- **#define : TRUSTED_OS_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100416
417 BL32 key certificate identifier, used by BL2 to load the BL32 key
418 certificate (mandatory when Trusted Board Boot is enabled).
419
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100420- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100421
422 BL32 content certificate identifier, used by BL2 to load the BL32 content
423 certificate (mandatory when Trusted Board Boot is enabled).
424
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100425- **#define : BL32_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100426
427 Defines the base address in secure memory where BL2 loads the BL32 binary
428 image. Must be aligned on a page-size boundary.
429
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100430- **#define : BL32_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100431
432 Defines the maximum address that the BL32 image can occupy.
433
434If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the
435platform, the following constants must also be defined:
436
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100437- **#define : TSP_SEC_MEM_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100438
439 Defines the base address of the secure memory used by the TSP image on the
440 platform. This must be at the same address or below ``BL32_BASE``.
441
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100442- **#define : TSP_SEC_MEM_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100443
444 Defines the size of the secure memory used by the BL32 image on the
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000445 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully
446 accommodate the memory required by the BL32 image, defined by ``BL32_BASE``
447 and ``BL32_LIMIT``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100448
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100449- **#define : TSP_IRQ_SEC_PHY_TIMER**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100450
451 Defines the ID of the secure physical generic timer interrupt used by the
452 TSP's interrupt handling code.
453
454If the platform port uses the translation table library code, the following
455constants must also be defined:
456
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100457- **#define : PLAT_XLAT_TABLES_DYNAMIC**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100458
459 Optional flag that can be set per-image to enable the dynamic allocation of
460 regions even when the MMU is enabled. If not defined, only static
461 functionality will be available, if defined and set to 1 it will also
462 include the dynamic functionality.
463
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100464- **#define : MAX_XLAT_TABLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100465
466 Defines the maximum number of translation tables that are allocated by the
467 translation table library code. To minimize the amount of runtime memory
468 used, choose the smallest value needed to map the required virtual addresses
469 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL
470 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions
471 as well.
472
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100473- **#define : MAX_MMAP_REGIONS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100474
475 Defines the maximum number of regions that are allocated by the translation
476 table library code. A region consists of physical base address, virtual base
477 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
478 defined in the ``mmap_region_t`` structure. The platform defines the regions
479 that should be mapped. Then, the translation table library will create the
480 corresponding tables and descriptors at runtime. To minimize the amount of
481 runtime memory used, choose the smallest value needed to register the
482 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is
483 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate
484 the dynamic regions as well.
485
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100486- **#define : PLAT_VIRT_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100487
488 Defines the total size of the virtual address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000489 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100490
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100491- **#define : PLAT_PHY_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100492
493 Defines the total size of the physical address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000494 for a 32 bit physical address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100495
496If the platform port uses the IO storage framework, the following constants
497must also be defined:
498
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100499- **#define : MAX_IO_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100500
501 Defines the maximum number of registered IO devices. Attempting to register
502 more devices than this value using ``io_register_device()`` will fail with
503 -ENOMEM.
504
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100505- **#define : MAX_IO_HANDLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100506
507 Defines the maximum number of open IO handles. Attempting to open more IO
508 entities than this value using ``io_open()`` will fail with -ENOMEM.
509
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100510- **#define : MAX_IO_BLOCK_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100511
512 Defines the maximum number of registered IO block devices. Attempting to
513 register more devices this value using ``io_dev_open()`` will fail
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100514 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100515 With this macro, multiple block devices could be supported at the same
516 time.
517
518If the platform needs to allocate data within the per-cpu data framework in
519BL31, it should define the following macro. Currently this is only required if
520the platform decides not to use the coherent memory section by undefining the
521``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
522required memory within the the per-cpu data to minimize wastage.
523
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100524- **#define : PLAT_PCPU_DATA_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100525
526 Defines the memory (in bytes) to be reserved within the per-cpu data
527 structure for use by the platform layer.
528
529The following constants are optional. They should be defined when the platform
Dan Handley610e7e12018-03-01 18:44:00 +0000530memory layout implies some image overlaying like in Arm standard platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100531
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100532- **#define : BL31_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100533
534 Defines the maximum address in secure RAM that the BL31's progbits sections
535 can occupy.
536
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100537- **#define : TSP_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100538
539 Defines the maximum address that the TSP's progbits sections can occupy.
540
Wing Li2c556f32022-09-14 13:18:17 -0700541If the platform supports OS-initiated mode, i.e. the build option
542``PSCI_OS_INIT_MODE`` is enabled, and if the platform's maximum power domain
543level for PSCI_CPU_SUSPEND differs from ``PLAT_MAX_PWR_LVL``, the following
544constant must be defined.
545
546- **#define : PLAT_MAX_CPU_SUSPEND_PWR_LVL**
547
548 Defines the maximum power domain level that PSCI_CPU_SUSPEND should apply to.
549
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100550If the platform port uses the PL061 GPIO driver, the following constant may
551optionally be defined:
552
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100553- **PLAT_PL061_MAX_GPIOS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100554 Maximum number of GPIOs required by the platform. This allows control how
555 much memory is allocated for PL061 GPIO controllers. The default value is
556
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100557 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100558
559If the platform port uses the partition driver, the following constant may
560optionally be defined:
561
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100562- **PLAT_PARTITION_MAX_ENTRIES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100563 Maximum number of partition entries required by the platform. This allows
564 control how much memory is allocated for partition entries. The default
565 value is 128.
Paul Beesleyf8640672019-04-12 14:19:42 +0100566 For example, define the build flag in ``platform.mk``:
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100567 PLAT_PARTITION_MAX_ENTRIES := 12
568 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100569
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800570- **PLAT_PARTITION_BLOCK_SIZE**
571 The size of partition block. It could be either 512 bytes or 4096 bytes.
572 The default value is 512.
Paul Beesleyf2ec7142019-10-04 16:17:46 +0000573 For example, define the build flag in ``platform.mk``:
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800574 PLAT_PARTITION_BLOCK_SIZE := 4096
575 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE))
576
Rob Hughes7a354bd2023-02-20 12:03:52 +0000577If the platform port uses the Arm® Ethos™-N NPU driver, the following
578configuration must be performed:
579
580- The NPU SiP service handler must be hooked up. This consists of both the
581 initial setup (``ethosn_smc_setup``) and the handler itself
582 (``ethosn_smc_handler``)
583
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100584If the platform port uses the Arm® Ethos™-N NPU driver with TZMP1 support
Rob Hughes7a354bd2023-02-20 12:03:52 +0000585enabled, the following constants and configuration must also be defined:
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100586
587- **ARM_ETHOSN_NPU_PROT_FW_NSAID**
588
589 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to
590 access the protected memory that contains the NPU's firmware.
591
Mikael Olsson80b61f52023-03-14 18:29:06 +0100592- **ARM_ETHOSN_NPU_PROT_DATA_RW_NSAID**
593
594 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
595 read/write access to the protected memory that contains inference data.
596
597- **ARM_ETHOSN_NPU_PROT_DATA_RO_NSAID**
598
599 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
600 read-only access to the protected memory that contains inference data.
601
602- **ARM_ETHOSN_NPU_NS_RW_DATA_NSAID**
603
604 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
605 read/write access to the non-protected memory.
606
607- **ARM_ETHOSN_NPU_NS_RO_DATA_NSAID**
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100608
Mikael Olsson80b61f52023-03-14 18:29:06 +0100609 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
610 read-only access to the non-protected memory.
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100611
Rob Hughes9a2177a2023-01-17 16:10:26 +0000612- **ARM_ETHOSN_NPU_FW_IMAGE_BASE** and **ARM_ETHOSN_NPU_FW_IMAGE_LIMIT**
613
Rob Hughes7a354bd2023-02-20 12:03:52 +0000614 Defines the physical address range that the NPU's firmware will be loaded
615 into and executed from.
616
617- Configure the platforms TrustZone Controller (TZC) with appropriate regions
618 of protected memory. At minimum this must include a region for the NPU's
619 firmware code and a region for protected inference data, and these must be
620 accessible using the NSAIDs defined above.
621
622- Include the NPU firmware and certificates in the FIP.
623
624- Provide FCONF entries to configure the image source for the NPU firmware
625 and certificates.
Rob Hughes9a2177a2023-01-17 16:10:26 +0000626
627- Add MMU mappings such that:
628
629 - BL2 can write the NPU firmware into the region defined by
630 ``ARM_ETHOSN_NPU_FW_IMAGE_BASE`` and ``ARM_ETHOSN_NPU_FW_IMAGE_LIMIT``
631 - BL31 (SiP service) can read the NPU firmware from the same region
632
Rob Hughes7a354bd2023-02-20 12:03:52 +0000633- Add the firmware image ID ``ARM_ETHOSN_NPU_FW_IMAGE_ID`` to the list of images
634 loaded by BL2.
Rob Hughes9a2177a2023-01-17 16:10:26 +0000635
636Please see the reference implementation code for the Juno platform as an example.
637
638
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100639The following constant is optional. It should be defined to override the default
640behaviour of the ``assert()`` function (for example, to save memory).
641
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100642- **PLAT_LOG_LEVEL_ASSERT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100643 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``,
644 ``assert()`` prints the name of the file, the line number and the asserted
645 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file
646 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it
647 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't
648 defined, it defaults to ``LOG_LEVEL``.
649
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +0100650If the platform port uses the DRTM feature, the following constants must be
651defined:
652
653- **#define : PLAT_DRTM_EVENT_LOG_MAX_SIZE**
654
655 Maximum Event Log size used by the platform. Platform can decide the maximum
656 size of the Event Log buffer, depending upon the highest hash algorithm
657 chosen and the number of components selected to measure during the DRTM
658 execution flow.
659
660- **#define : PLAT_DRTM_MMAP_ENTRIES**
661
662 Number of the MMAP entries used by the DRTM implementation to calculate the
663 size of address map region of the platform.
664
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100665File : plat_macros.S [mandatory]
666~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100667
668Each platform must ensure a file of this name is in the system include path with
Dan Handley610e7e12018-03-01 18:44:00 +0000669the following macro defined. In the Arm development platforms, this file is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100670found in ``plat/arm/board/<plat_name>/include/plat_macros.S``.
671
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100672- **Macro : plat_crash_print_regs**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100673
674 This macro allows the crash reporting routine to print relevant platform
675 registers in case of an unhandled exception in BL31. This aids in debugging
676 and this macro can be defined to be empty in case register reporting is not
677 desired.
678
679 For instance, GIC or interconnect registers may be helpful for
680 troubleshooting.
681
682Handling Reset
683--------------
684
685BL1 by default implements the reset vector where execution starts from a cold
686or warm boot. BL31 can be optionally set as a reset vector using the
687``RESET_TO_BL31`` make variable.
688
689For each CPU, the reset vector code is responsible for the following tasks:
690
691#. Distinguishing between a cold boot and a warm boot.
692
693#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
694 the CPU is placed in a platform-specific state until the primary CPU
695 performs the necessary steps to remove it from this state.
696
697#. In the case of a warm boot, ensuring that the CPU jumps to a platform-
698 specific address in the BL31 image in the same processor mode as it was
699 when released from reset.
700
701The following functions need to be implemented by the platform port to enable
702reset vector code to perform the above tasks.
703
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100704Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0]
705~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100706
707::
708
709 Argument : void
710 Return : uintptr_t
711
712This function is called with the MMU and caches disabled
713(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for
714distinguishing between a warm and cold reset for the current CPU using
715platform-specific means. If it's a warm reset, then it returns the warm
716reset entrypoint point provided to ``plat_setup_psci_ops()`` during
717BL31 initialization. If it's a cold reset then this function must return zero.
718
719This function does not follow the Procedure Call Standard used by the
Dan Handley610e7e12018-03-01 18:44:00 +0000720Application Binary Interface for the Arm 64-bit architecture. The caller should
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100721not assume that callee saved registers are preserved across a call to this
722function.
723
724This function fulfills requirement 1 and 3 listed above.
725
726Note that for platforms that support programming the reset address, it is
727expected that a CPU will start executing code directly at the right address,
728both on a cold and warm reset. In this case, there is no need to identify the
729type of reset nor to query the warm reset entrypoint. Therefore, implementing
730this function is not required on such platforms.
731
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100732Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
733~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100734
735::
736
737 Argument : void
738
739This function is called with the MMU and data caches disabled. It is responsible
740for placing the executing secondary CPU in a platform-specific state until the
741primary CPU performs the necessary actions to bring it out of that state and
742allow entry into the OS. This function must not return.
743
Dan Handley610e7e12018-03-01 18:44:00 +0000744In the Arm FVP port, when using the normal boot flow, each secondary CPU powers
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100745itself off. The primary CPU is responsible for powering up the secondary CPUs
746when normal world software requires them. When booting an EL3 payload instead,
747they stay powered on and are put in a holding pen until their mailbox gets
748populated.
749
750This function fulfills requirement 2 above.
751
752Note that for platforms that can't release secondary CPUs out of reset, only the
753primary CPU will execute the cold boot code. Therefore, implementing this
754function is not required on such platforms.
755
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100756Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
757~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100758
759::
760
761 Argument : void
762 Return : unsigned int
763
764This function identifies whether the current CPU is the primary CPU or a
765secondary CPU. A return value of zero indicates that the CPU is not the
766primary CPU, while a non-zero return value indicates that the CPU is the
767primary CPU.
768
769Note that for platforms that can't release secondary CPUs out of reset, only the
770primary CPU will execute the cold boot code. Therefore, there is no need to
771distinguish between primary and secondary CPUs and implementing this function is
772not required.
773
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100774Function : platform_mem_init() [mandatory]
775~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100776
777::
778
779 Argument : void
780 Return : void
781
782This function is called before any access to data is made by the firmware, in
783order to carry out any essential memory initialization.
784
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100785Function: plat_get_rotpk_info()
786~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100787
788::
789
790 Argument : void *, void **, unsigned int *, unsigned int *
791 Return : int
792
793This function is mandatory when Trusted Board Boot is enabled. It returns a
794pointer to the ROTPK stored in the platform (or a hash of it) and its length.
795The ROTPK must be encoded in DER format according to the following ASN.1
796structure:
797
798::
799
800 AlgorithmIdentifier ::= SEQUENCE {
801 algorithm OBJECT IDENTIFIER,
802 parameters ANY DEFINED BY algorithm OPTIONAL
803 }
804
805 SubjectPublicKeyInfo ::= SEQUENCE {
806 algorithm AlgorithmIdentifier,
807 subjectPublicKey BIT STRING
808 }
809
810In case the function returns a hash of the key:
811
812::
813
814 DigestInfo ::= SEQUENCE {
815 digestAlgorithm AlgorithmIdentifier,
816 digest OCTET STRING
817 }
818
819The function returns 0 on success. Any other value is treated as error by the
820Trusted Board Boot. The function also reports extra information related
821to the ROTPK in the flags parameter:
822
823::
824
825 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a
826 hash.
827 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK
828 verification while the platform ROTPK is not deployed.
829 When this flag is set, the function does not need to
830 return a platform ROTPK, and the authentication
831 framework uses the ROTPK in the certificate without
832 verifying it against the platform value. This flag
833 must not be used in a deployed production environment.
834
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100835Function: plat_get_nv_ctr()
836~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100837
838::
839
840 Argument : void *, unsigned int *
841 Return : int
842
843This function is mandatory when Trusted Board Boot is enabled. It returns the
844non-volatile counter value stored in the platform in the second argument. The
845cookie in the first argument may be used to select the counter in case the
846platform provides more than one (for example, on platforms that use the default
847TBBR CoT, the cookie will correspond to the OID values defined in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100848TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100849
850The function returns 0 on success. Any other value means the counter value could
851not be retrieved from the platform.
852
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100853Function: plat_set_nv_ctr()
854~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100855
856::
857
858 Argument : void *, unsigned int
859 Return : int
860
861This function is mandatory when Trusted Board Boot is enabled. It sets a new
862counter value in the platform. The cookie in the first argument may be used to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100863select the counter (as explained in plat_get_nv_ctr()). The second argument is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100864the updated counter value to be written to the NV counter.
865
866The function returns 0 on success. Any other value means the counter value could
867not be updated.
868
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100869Function: plat_set_nv_ctr2()
870~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100871
872::
873
874 Argument : void *, const auth_img_desc_t *, unsigned int
875 Return : int
876
877This function is optional when Trusted Board Boot is enabled. If this
878interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The
879first argument passed is a cookie and is typically used to
880differentiate between a Non Trusted NV Counter and a Trusted NV
881Counter. The second argument is a pointer to an authentication image
882descriptor and may be used to decide if the counter is allowed to be
883updated or not. The third argument is the updated counter value to
884be written to the NV counter.
885
886The function returns 0 on success. Any other value means the counter value
887either could not be updated or the authentication image descriptor indicates
888that it is not allowed to be updated.
889
Nicolas Toromanoff7f95ac82020-11-09 12:14:52 +0100890Function: plat_convert_pk()
891~~~~~~~~~~~~~~~~~~~~~~~~~~~
892
893::
894
895 Argument : void *, unsigned int, void **, unsigned int *
896 Return : int
897
898This function is optional when Trusted Board Boot is enabled, and only
899used if the platform saves a hash of the ROTPK.
900First argument is the Distinguished Encoding Rules (DER) ROTPK.
901Second argument is its size.
902Third argument is used to return a pointer to a buffer, which hash should
903be the one saved in OTP.
904Fourth argument is a pointer to return its size.
905
906Most platforms save the hash of the ROTPK, but some may save slightly different
907information - e.g the hash of the ROTPK plus some related information.
908Defining this function allows to transform the ROTPK used to verify
909the signature to the buffer (a platform specific public key) which
910hash is saved in OTP.
911
912The default implementation copies the input key and length to the output without
913modification.
914
915The function returns 0 on success. Any other value means the expected
916public key buffer cannot be extracted.
917
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +0100918Dynamic Root of Trust for Measurement support (in BL31)
919-------------------------------------------------------
920
921The functions mentioned in this section are mandatory, when platform enables
922DRTM_SUPPORT build flag.
923
924Function : plat_get_addr_mmap()
925~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
926
927::
928
929 Argument : void
930 Return : const mmap_region_t *
931
932This function is used to return the address of the platform *address-map* table,
933which describes the regions of normal memory, memory mapped I/O
934and non-volatile memory.
935
936Function : plat_has_non_host_platforms()
937~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
938
939::
940
941 Argument : void
942 Return : bool
943
944This function returns *true* if the platform has any trusted devices capable of
945DMA, otherwise returns *false*.
946
947Function : plat_has_unmanaged_dma_peripherals()
948~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
949
950::
951
952 Argument : void
953 Return : bool
954
955This function returns *true* if platform uses peripherals whose DMA is not
956managed by an SMMU, otherwise returns *false*.
957
958Note -
959If the platform has peripherals that are not managed by the SMMU, then the
960platform should investigate such peripherals to determine whether they can
961be trusted, and such peripherals should be moved under "Non-host platforms"
962if they can be trusted.
963
964Function : plat_get_total_num_smmus()
965~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
966
967::
968
969 Argument : void
970 Return : unsigned int
971
972This function returns the total number of SMMUs in the platform.
973
974Function : plat_enumerate_smmus()
975~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
976::
977
978
979 Argument : void
980 Return : const uintptr_t *, size_t
981
982This function returns an array of SMMU addresses and the actual number of SMMUs
983reported by the platform.
984
985Function : plat_drtm_get_dma_prot_features()
986~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
987
988::
989
990 Argument : void
991 Return : const plat_drtm_dma_prot_features_t*
992
993This function returns the address of plat_drtm_dma_prot_features_t structure
994containing the maximum number of protected regions and bitmap with the types
995of DMA protection supported by the platform.
996For more details see section 3.3 Table 6 of `DRTM`_ specification.
997
998Function : plat_drtm_dma_prot_get_max_table_bytes()
999~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1000
1001::
1002
1003 Argument : void
1004 Return : uint64_t
1005
1006This function returns the maximum size of DMA protected regions table in
1007bytes.
1008
1009Function : plat_drtm_get_tpm_features()
1010~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1011
1012::
1013
1014 Argument : void
1015 Return : const plat_drtm_tpm_features_t*
1016
1017This function returns the address of *plat_drtm_tpm_features_t* structure
1018containing PCR usage schema, TPM-based hash, and firmware hash algorithm
1019supported by the platform.
1020
1021Function : plat_drtm_get_min_size_normal_world_dce()
1022~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1023
1024::
1025
1026 Argument : void
1027 Return : uint64_t
1028
1029This function returns the size normal-world DCE of the platform.
1030
1031Function : plat_drtm_get_imp_def_dlme_region_size()
1032~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1033
1034::
1035
1036 Argument : void
1037 Return : uint64_t
1038
1039This function returns the size of implementation defined DLME region
1040of the platform.
1041
1042Function : plat_drtm_get_tcb_hash_table_size()
1043~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1044
1045::
1046
1047 Argument : void
1048 Return : uint64_t
1049
1050This function returns the size of TCB hash table of the platform.
1051
1052Function : plat_drtm_get_tcb_hash_features()
1053~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1054
1055::
1056
1057 Argument : void
1058 Return : uint64_t
1059
1060This function returns the Maximum number of TCB hashes recorded by the
1061platform.
1062For more details see section 3.3 Table 6 of `DRTM`_ specification.
1063
1064Function : plat_drtm_validate_ns_region()
1065~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1066
1067::
1068
1069 Argument : uintptr_t, uintptr_t
1070 Return : int
1071
1072This function validates that given region is within the Non-Secure region
1073of DRAM. This function takes a region start address and size an input
1074arguments, and returns 0 on success and -1 on failure.
1075
1076Function : plat_set_drtm_error()
1077~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1078
1079::
1080
1081 Argument : uint64_t
1082 Return : int
1083
1084This function writes a 64 bit error code received as input into
1085non-volatile storage and returns 0 on success and -1 on failure.
1086
1087Function : plat_get_drtm_error()
1088~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1089
1090::
1091
1092 Argument : uint64_t*
1093 Return : int
1094
1095This function reads a 64 bit error code from the non-volatile storage
1096into the received address, and returns 0 on success and -1 on failure.
1097
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001098Common mandatory function modifications
1099---------------------------------------
1100
1101The following functions are mandatory functions which need to be implemented
1102by the platform port.
1103
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001104Function : plat_my_core_pos()
1105~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001106
1107::
1108
1109 Argument : void
1110 Return : unsigned int
1111
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001112This function returns the index of the calling CPU which is used as a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001113CPU-specific linear index into blocks of memory (for example while allocating
1114per-CPU stacks). This function will be invoked very early in the
1115initialization sequence which mandates that this function should be
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001116implemented in assembly and should not rely on the availability of a C
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001117runtime environment. This function can clobber x0 - x8 and must preserve
1118x9 - x29.
1119
1120This function plays a crucial role in the power domain topology framework in
Paul Beesleyf8640672019-04-12 14:19:42 +01001121PSCI and details of this can be found in
1122:ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001123
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001124Function : plat_core_pos_by_mpidr()
1125~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001126
1127::
1128
1129 Argument : u_register_t
1130 Return : int
1131
1132This function validates the ``MPIDR`` of a CPU and converts it to an index,
1133which can be used as a CPU-specific linear index into blocks of memory. In
1134case the ``MPIDR`` is invalid, this function returns -1. This function will only
1135be invoked by BL31 after the power domain topology is initialized and can
Dan Handley610e7e12018-03-01 18:44:00 +00001136utilize the C runtime environment. For further details about how TF-A
1137represents the power domain topology and how this relates to the linear CPU
Paul Beesleyf8640672019-04-12 14:19:42 +01001138index, please refer :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001139
Ambroise Vincentd207f562019-04-10 12:50:27 +01001140Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1]
1141~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1142
1143::
1144
1145 Arguments : void **heap_addr, size_t *heap_size
1146 Return : int
1147
1148This function is invoked during Mbed TLS library initialisation to get a heap,
1149by means of a starting address and a size. This heap will then be used
1150internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS
1151must be able to provide a heap to it.
1152
1153A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in
1154which a heap is statically reserved during compile time inside every image
1155(i.e. every BL stage) that utilises Mbed TLS. In this default implementation,
1156the function simply returns the address and size of this "pre-allocated" heap.
1157For a platform to use this default implementation, only a call to the helper
1158from inside plat_get_mbedtls_heap() body is enough and nothing else is needed.
1159
1160However, by writting their own implementation, platforms have the potential to
1161optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is
1162shared between BL1 and BL2 stages and, thus, the necessary space is not reserved
1163twice.
1164
1165On success the function should return 0 and a negative error code otherwise.
1166
Sumit Gargc0c369c2019-11-15 18:47:53 +05301167Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1]
1168~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1169
1170::
1171
1172 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key,
1173 size_t *key_len, unsigned int *flags, const uint8_t *img_id,
1174 size_t img_id_len
1175 Return : int
1176
1177This function provides a symmetric key (either SSK or BSSK depending on
1178fw_enc_status) which is invoked during runtime decryption of encrypted
1179firmware images. `plat/common/plat_bl_common.c` provides a dummy weak
1180implementation for testing purposes which must be overridden by the platform
1181trying to implement a real world firmware encryption use-case.
1182
1183It also allows the platform to pass symmetric key identifier rather than
1184actual symmetric key which is useful in cases where the crypto backend provides
1185secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER``
1186flag must be set in ``flags``.
1187
1188In addition to above a platform may also choose to provide an image specific
1189symmetric key/identifier using img_id.
1190
1191On success the function should return 0 and a negative error code otherwise.
1192
Manish Pandey34a305e2021-10-21 21:53:49 +01001193Note that this API depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +05301194
Manish V Badarkheda87af12021-06-20 21:14:46 +01001195Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1]
1196~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1197
1198::
1199
Sughosh Ganuf40154f2021-11-17 17:08:10 +05301200 Argument : const struct fwu_metadata *metadata
Manish V Badarkheda87af12021-06-20 21:14:46 +01001201 Return : void
1202
1203This function is mandatory when PSA_FWU_SUPPORT is enabled.
1204It provides a means to retrieve image specification (offset in
1205non-volatile storage and length) of active/updated images using the passed
1206FWU metadata, and update I/O policies of active/updated images using retrieved
1207image specification information.
1208Further I/O layer operations such as I/O open, I/O read, etc. on these
1209images rely on this function call.
1210
1211In Arm platforms, this function is used to set an I/O policy of the FIP image,
1212container of all active/updated secure and non-secure images.
1213
1214Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1]
1215~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1216
1217::
1218
1219 Argument : unsigned int image_id, uintptr_t *dev_handle,
1220 uintptr_t *image_spec
1221 Return : int
1222
1223This function is mandatory when PSA_FWU_SUPPORT is enabled. It is
1224responsible for setting up the platform I/O policy of the requested metadata
1225image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will
1226be used to load this image from the platform's non-volatile storage.
1227
1228FWU metadata can not be always stored as a raw image in non-volatile storage
1229to define its image specification (offset in non-volatile storage and length)
1230statically in I/O policy.
1231For example, the FWU metadata image is stored as a partition inside the GUID
1232partition table image. Its specification is defined in the partition table
1233that needs to be parsed dynamically.
1234This function provides a means to retrieve such dynamic information to set
1235the I/O policy of the FWU metadata image.
1236Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata
1237image relies on this function call.
1238
1239It returns '0' on success, otherwise a negative error value on error.
1240Alongside, returns device handle and image specification from the I/O policy
1241of the requested FWU metadata image.
1242
Sughosh Ganu4e336a62021-12-01 15:53:32 +05301243Function : plat_fwu_get_boot_idx() [when PSA_FWU_SUPPORT == 1]
1244~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1245
1246::
1247
1248 Argument : void
1249 Return : uint32_t
1250
1251This function is mandatory when PSA_FWU_SUPPORT is enabled. It provides the
1252means to retrieve the boot index value from the platform. The boot index is the
1253bank from which the platform has booted the firmware images.
1254
1255By default, the platform will read the metadata structure and try to boot from
1256the active bank. If the platform fails to boot from the active bank due to
1257reasons like an Authentication failure, or on crossing a set number of watchdog
1258resets while booting from the active bank, the platform can then switch to boot
1259from a different bank. This function then returns the bank that the platform
1260should boot its images from.
1261
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001262Common optional modifications
1263-----------------------------
1264
1265The following are helper functions implemented by the firmware that perform
1266common platform-specific tasks. A platform may choose to override these
1267definitions.
1268
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001269Function : plat_set_my_stack()
1270~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001271
1272::
1273
1274 Argument : void
1275 Return : void
1276
1277This function sets the current stack pointer to the normal memory stack that
1278has been allocated for the current CPU. For BL images that only require a
1279stack for the primary CPU, the UP version of the function is used. The size
1280of the stack allocated to each CPU is specified by the platform defined
1281constant ``PLATFORM_STACK_SIZE``.
1282
1283Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +01001284provided in ``plat/common/aarch64/platform_up_stack.S`` and
1285``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001286
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001287Function : plat_get_my_stack()
1288~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001289
1290::
1291
1292 Argument : void
1293 Return : uintptr_t
1294
1295This function returns the base address of the normal memory stack that
1296has been allocated for the current CPU. For BL images that only require a
1297stack for the primary CPU, the UP version of the function is used. The size
1298of the stack allocated to each CPU is specified by the platform defined
1299constant ``PLATFORM_STACK_SIZE``.
1300
1301Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +01001302provided in ``plat/common/aarch64/platform_up_stack.S`` and
1303``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001304
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001305Function : plat_report_exception()
1306~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001307
1308::
1309
1310 Argument : unsigned int
1311 Return : void
1312
1313A platform may need to report various information about its status when an
1314exception is taken, for example the current exception level, the CPU security
1315state (secure/non-secure), the exception type, and so on. This function is
1316called in the following circumstances:
1317
1318- In BL1, whenever an exception is taken.
1319- In BL2, whenever an exception is taken.
1320
1321The default implementation doesn't do anything, to avoid making assumptions
1322about the way the platform displays its status information.
1323
1324For AArch64, this function receives the exception type as its argument.
1325Possible values for exceptions types are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +01001326``include/common/bl_common.h`` header file. Note that these constants are not
Dan Handley610e7e12018-03-01 18:44:00 +00001327related to any architectural exception code; they are just a TF-A convention.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001328
1329For AArch32, this function receives the exception mode as its argument.
1330Possible values for exception modes are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +01001331``include/lib/aarch32/arch.h`` header file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001332
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001333Function : plat_reset_handler()
1334~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001335
1336::
1337
1338 Argument : void
1339 Return : void
1340
1341A platform may need to do additional initialization after reset. This function
Paul Beesleyf2ec7142019-10-04 16:17:46 +00001342allows the platform to do the platform specific initializations. Platform
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001343specific errata workarounds could also be implemented here. The API should
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001344preserve the values of callee saved registers x19 to x29.
1345
1346The default implementation doesn't do anything. If a platform needs to override
Paul Beesleyf8640672019-04-12 14:19:42 +01001347the default implementation, refer to the :ref:`Firmware Design` for general
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001348guidelines.
1349
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001350Function : plat_disable_acp()
1351~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001352
1353::
1354
1355 Argument : void
1356 Return : void
1357
John Tsichritzis6dda9762018-07-23 09:18:04 +01001358This API allows a platform to disable the Accelerator Coherency Port (if
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001359present) during a cluster power down sequence. The default weak implementation
John Tsichritzis6dda9762018-07-23 09:18:04 +01001360doesn't do anything. Since this API is called during the power down sequence,
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001361it has restrictions for stack usage and it can use the registers x0 - x17 as
1362scratch registers. It should preserve the value in x18 register as it is used
1363by the caller to store the return address.
1364
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001365Function : plat_error_handler()
1366~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001367
1368::
1369
1370 Argument : int
1371 Return : void
1372
1373This API is called when the generic code encounters an error situation from
1374which it cannot continue. It allows the platform to perform error reporting or
1375recovery actions (for example, reset the system). This function must not return.
1376
1377The parameter indicates the type of error using standard codes from ``errno.h``.
1378Possible errors reported by the generic code are:
1379
1380- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted
1381 Board Boot is enabled)
1382- ``-ENOENT``: the requested image or certificate could not be found or an IO
1383 error was detected
Dan Handley610e7e12018-03-01 18:44:00 +00001384- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this
1385 error is usually an indication of an incorrect array size
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001386
1387The default implementation simply spins.
1388
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001389Function : plat_panic_handler()
1390~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001391
1392::
1393
1394 Argument : void
1395 Return : void
1396
1397This API is called when the generic code encounters an unexpected error
1398situation from which it cannot recover. This function must not return,
1399and must be implemented in assembly because it may be called before the C
1400environment is initialized.
1401
Paul Beesleyba3ed402019-03-13 16:20:44 +00001402.. note::
1403 The address from where it was called is stored in x30 (Link Register).
1404 The default implementation simply spins.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001405
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +01001406Function : plat_system_reset()
1407~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1408
1409::
1410
1411 Argument : void
1412 Return : void
1413
1414This function is used by the platform to resets the system. It can be used
1415in any specific use-case where system needs to be resetted. For example,
1416in case of DRTM implementation this function reset the system after
1417writing the DRTM error code in the non-volatile storage. This function
1418never returns. Failure in reset results in panic.
1419
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001420Function : plat_get_bl_image_load_info()
1421~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001422
1423::
1424
1425 Argument : void
1426 Return : bl_load_info_t *
1427
1428This function returns pointer to the list of images that the platform has
Soby Mathew97b1bff2018-09-27 16:46:41 +01001429populated to load. This function is invoked in BL2 to load the
1430BL3xx images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001431
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001432Function : plat_get_next_bl_params()
1433~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001434
1435::
1436
1437 Argument : void
1438 Return : bl_params_t *
1439
1440This function returns a pointer to the shared memory that the platform has
Dan Handley610e7e12018-03-01 18:44:00 +00001441kept aside to pass TF-A related information that next BL image needs. This
Soby Mathew97b1bff2018-09-27 16:46:41 +01001442function is invoked in BL2 to pass this information to the next BL
1443image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001444
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001445Function : plat_get_stack_protector_canary()
1446~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001447
1448::
1449
1450 Argument : void
1451 Return : u_register_t
1452
1453This function returns a random value that is used to initialize the canary used
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001454when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001455value will weaken the protection as the attacker could easily write the right
1456value as part of the attack most of the time. Therefore, it should return a
1457true random number.
1458
Paul Beesleyba3ed402019-03-13 16:20:44 +00001459.. warning::
1460 For the protection to be effective, the global data need to be placed at
1461 a lower address than the stack bases. Failure to do so would allow an
1462 attacker to overwrite the canary as part of the stack buffer overflow attack.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001463
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001464Function : plat_flush_next_bl_params()
1465~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001466
1467::
1468
1469 Argument : void
1470 Return : void
1471
1472This function flushes to main memory all the image params that are passed to
Soby Mathew97b1bff2018-09-27 16:46:41 +01001473next image. This function is invoked in BL2 to flush this information
1474to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001475
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001476Function : plat_log_get_prefix()
1477~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewaaf15f52017-09-04 11:49:29 +01001478
1479::
1480
1481 Argument : unsigned int
1482 Return : const char *
1483
1484This function defines the prefix string corresponding to the `log_level` to be
Dan Handley610e7e12018-03-01 18:44:00 +00001485prepended to all the log output from TF-A. The `log_level` (argument) will
1486correspond to one of the standard log levels defined in debug.h. The platform
1487can override the common implementation to define a different prefix string for
John Tsichritzis30f89642018-06-07 16:31:34 +01001488the log output. The implementation should be robust to future changes that
Dan Handley610e7e12018-03-01 18:44:00 +00001489increase the number of log levels.
Soby Mathewaaf15f52017-09-04 11:49:29 +01001490
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001491Function : plat_get_soc_version()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001492~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001493
1494::
1495
1496 Argument : void
1497 Return : int32_t
1498
1499This function returns soc version which mainly consist of below fields
1500
1501::
1502
1503 soc_version[30:24] = JEP-106 continuation code for the SiP
1504 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001505 soc_version[15:0] = Implementation defined SoC ID
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001506
1507Function : plat_get_soc_revision()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001508~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001509
1510::
1511
1512 Argument : void
1513 Return : int32_t
1514
1515This function returns soc revision in below format
1516
1517::
1518
1519 soc_revision[0:30] = SOC revision of specific SOC
1520
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001521Function : plat_is_smccc_feature_available()
1522~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1523
1524::
1525
1526 Argument : u_register_t
1527 Return : int32_t
1528
1529This function returns SMC_ARCH_CALL_SUCCESS if the platform supports
1530the SMCCC function specified in the argument; otherwise returns
1531SMC_ARCH_CALL_NOT_SUPPORTED.
1532
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001533Function : plat_mboot_measure_image()
1534~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1535
1536::
1537
1538 Argument : unsigned int, image_info_t *
Manish V Badarkhe931c6ef2021-10-21 09:06:18 +01001539 Return : int
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001540
1541When the MEASURED_BOOT flag is enabled:
1542
1543- This function measures the given image and records its measurement using
1544 the measured boot backend driver.
1545- On the Arm FVP port, this function measures the given image using its
1546 passed id and information and then records that measurement in the
1547 Event Log buffer.
Manish V Badarkhe931c6ef2021-10-21 09:06:18 +01001548- This function must return 0 on success, a signed integer error code
1549 otherwise.
1550
1551When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1552
1553Function : plat_mboot_measure_critical_data()
1554~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1555
1556::
1557
1558 Argument : unsigned int, const void *, size_t
1559 Return : int
1560
1561When the MEASURED_BOOT flag is enabled:
1562
1563- This function measures the given critical data structure and records its
1564 measurement using the measured boot backend driver.
1565- This function must return 0 on success, a signed integer error code
1566 otherwise.
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001567
1568When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1569
Okash Khawaja037b56e2022-11-04 12:38:01 +00001570Function : plat_can_cmo()
1571~~~~~~~~~~~~~~~~~~~~~~~~~
1572
1573::
1574
1575 Argument : void
1576 Return : uint64_t
1577
1578When CONDITIONAL_CMO flag is enabled:
1579
1580- This function indicates whether cache management operations should be
1581 performed. It returns 0 if CMOs should be skipped and non-zero
1582 otherwise.
Okash Khawaja94532202022-11-14 12:50:30 +00001583- The function must not clobber x1, x2 and x3. It's also not safe to rely on
1584 stack. Otherwise obey AAPCS.
Okash Khawaja037b56e2022-11-04 12:38:01 +00001585
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001586Modifications specific to a Boot Loader stage
1587---------------------------------------------
1588
1589Boot Loader Stage 1 (BL1)
1590-------------------------
1591
1592BL1 implements the reset vector where execution starts from after a cold or
1593warm boot. For each CPU, BL1 is responsible for the following tasks:
1594
1595#. Handling the reset as described in section 2.2
1596
1597#. In the case of a cold boot and the CPU being the primary CPU, ensuring that
1598 only this CPU executes the remaining BL1 code, including loading and passing
1599 control to the BL2 stage.
1600
1601#. Identifying and starting the Firmware Update process (if required).
1602
1603#. Loading the BL2 image from non-volatile storage into secure memory at the
1604 address specified by the platform defined constant ``BL2_BASE``.
1605
1606#. Populating a ``meminfo`` structure with the following information in memory,
1607 accessible by BL2 immediately upon entry.
1608
1609 ::
1610
1611 meminfo.total_base = Base address of secure RAM visible to BL2
1612 meminfo.total_size = Size of secure RAM visible to BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001613
Soby Mathew97b1bff2018-09-27 16:46:41 +01001614 By default, BL1 places this ``meminfo`` structure at the end of secure
1615 memory visible to BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001616
Soby Mathewb1bf0442018-02-16 14:52:52 +00001617 It is possible for the platform to decide where it wants to place the
1618 ``meminfo`` structure for BL2 or restrict the amount of memory visible to
1619 BL2 by overriding the weak default implementation of
1620 ``bl1_plat_handle_post_image_load`` API.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001621
1622The following functions need to be implemented by the platform port to enable
1623BL1 to perform the above tasks.
1624
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001625Function : bl1_early_platform_setup() [mandatory]
1626~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001627
1628::
1629
1630 Argument : void
1631 Return : void
1632
1633This function executes with the MMU and data caches disabled. It is only called
1634by the primary CPU.
1635
Dan Handley610e7e12018-03-01 18:44:00 +00001636On Arm standard platforms, this function:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001637
1638- Enables a secure instance of SP805 to act as the Trusted Watchdog.
1639
1640- Initializes a UART (PL011 console), which enables access to the ``printf``
1641 family of functions in BL1.
1642
1643- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to
1644 the CCI slave interface corresponding to the cluster that includes the
1645 primary CPU.
1646
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001647Function : bl1_plat_arch_setup() [mandatory]
1648~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001649
1650::
1651
1652 Argument : void
1653 Return : void
1654
1655This function performs any platform-specific and architectural setup that the
1656platform requires. Platform-specific setup might include configuration of
1657memory controllers and the interconnect.
1658
Dan Handley610e7e12018-03-01 18:44:00 +00001659In Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001660
1661This function helps fulfill requirement 2 above.
1662
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001663Function : bl1_platform_setup() [mandatory]
1664~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001665
1666::
1667
1668 Argument : void
1669 Return : void
1670
1671This function executes with the MMU and data caches enabled. It is responsible
1672for performing any remaining platform-specific setup that can occur after the
1673MMU and data cache have been enabled.
1674
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001675if support for multiple boot sources is required, it initializes the boot
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001676sequence used by plat_try_next_boot_source().
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001677
Dan Handley610e7e12018-03-01 18:44:00 +00001678In Arm standard platforms, this function initializes the storage abstraction
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001679layer used to load the next bootloader image.
1680
1681This function helps fulfill requirement 4 above.
1682
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001683Function : bl1_plat_sec_mem_layout() [mandatory]
1684~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001685
1686::
1687
1688 Argument : void
1689 Return : meminfo *
1690
1691This function should only be called on the cold boot path. It executes with the
1692MMU and data caches enabled. The pointer returned by this function must point to
1693a ``meminfo`` structure containing the extents and availability of secure RAM for
1694the BL1 stage.
1695
1696::
1697
1698 meminfo.total_base = Base address of secure RAM visible to BL1
1699 meminfo.total_size = Size of secure RAM visible to BL1
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001700
1701This information is used by BL1 to load the BL2 image in secure RAM. BL1 also
1702populates a similar structure to tell BL2 the extents of memory available for
1703its own use.
1704
1705This function helps fulfill requirements 4 and 5 above.
1706
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001707Function : bl1_plat_prepare_exit() [optional]
1708~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001709
1710::
1711
1712 Argument : entry_point_info_t *
1713 Return : void
1714
1715This function is called prior to exiting BL1 in response to the
1716``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform
1717platform specific clean up or bookkeeping operations before transferring
1718control to the next image. It receives the address of the ``entry_point_info_t``
1719structure passed from BL2. This function runs with MMU disabled.
1720
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001721Function : bl1_plat_set_ep_info() [optional]
1722~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001723
1724::
1725
1726 Argument : unsigned int image_id, entry_point_info_t *ep_info
1727 Return : void
1728
1729This function allows platforms to override ``ep_info`` for the given ``image_id``.
1730
1731The default implementation just returns.
1732
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001733Function : bl1_plat_get_next_image_id() [optional]
1734~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001735
1736::
1737
1738 Argument : void
1739 Return : unsigned int
1740
1741This and the following function must be overridden to enable the FWU feature.
1742
1743BL1 calls this function after platform setup to identify the next image to be
1744loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds
1745with the normal boot sequence, which loads and executes BL2. If the platform
1746returns a different image id, BL1 assumes that Firmware Update is required.
1747
Dan Handley610e7e12018-03-01 18:44:00 +00001748The default implementation always returns ``BL2_IMAGE_ID``. The Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001749platforms override this function to detect if firmware update is required, and
1750if so, return the first image in the firmware update process.
1751
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001752Function : bl1_plat_get_image_desc() [optional]
1753~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001754
1755::
1756
1757 Argument : unsigned int image_id
1758 Return : image_desc_t *
1759
1760BL1 calls this function to get the image descriptor information ``image_desc_t``
1761for the provided ``image_id`` from the platform.
1762
Dan Handley610e7e12018-03-01 18:44:00 +00001763The default implementation always returns a common BL2 image descriptor. Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001764standard platforms return an image descriptor corresponding to BL2 or one of
1765the firmware update images defined in the Trusted Board Boot Requirements
1766specification.
1767
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001768Function : bl1_plat_handle_pre_image_load() [optional]
1769~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001770
1771::
1772
Soby Mathew2f38ce32018-02-08 17:45:12 +00001773 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001774 Return : int
1775
1776This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001777corresponding to ``image_id``. This function is invoked in BL1, both in cold
1778boot and FWU code path, before loading the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001779
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001780Function : bl1_plat_handle_post_image_load() [optional]
1781~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001782
1783::
1784
Soby Mathew2f38ce32018-02-08 17:45:12 +00001785 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001786 Return : int
1787
1788This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001789corresponding to ``image_id``. This function is invoked in BL1, both in cold
1790boot and FWU code path, after loading and authenticating the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001791
Soby Mathewb1bf0442018-02-16 14:52:52 +00001792The default weak implementation of this function calculates the amount of
1793Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t``
1794structure at the beginning of this free memory and populates it. The address
1795of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint
1796information to BL2.
1797
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001798Function : bl1_plat_fwu_done() [optional]
1799~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001800
1801::
1802
1803 Argument : unsigned int image_id, uintptr_t image_src,
1804 unsigned int image_size
1805 Return : void
1806
1807BL1 calls this function when the FWU process is complete. It must not return.
1808The platform may override this function to take platform specific action, for
1809example to initiate the normal boot flow.
1810
1811The default implementation spins forever.
1812
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001813Function : bl1_plat_mem_check() [mandatory]
1814~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001815
1816::
1817
1818 Argument : uintptr_t mem_base, unsigned int mem_size,
1819 unsigned int flags
1820 Return : int
1821
1822BL1 calls this function while handling FWU related SMCs, more specifically when
1823copying or authenticating an image. Its responsibility is to ensure that the
1824region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and
1825that this memory corresponds to either a secure or non-secure memory region as
1826indicated by the security state of the ``flags`` argument.
1827
1828This function can safely assume that the value resulting from the addition of
1829``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not
1830overflow.
1831
1832This function must return 0 on success, a non-null error code otherwise.
1833
1834The default implementation of this function asserts therefore platforms must
1835override it when using the FWU feature.
1836
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001837Function : bl1_plat_mboot_init() [optional]
1838~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1839
1840::
1841
1842 Argument : void
1843 Return : void
1844
1845When the MEASURED_BOOT flag is enabled:
1846
1847- This function is used to initialize the backend driver(s) of measured boot.
1848- On the Arm FVP port, this function is used to initialize the Event Log
1849 backend driver, and also to write header information in the Event Log buffer.
1850
1851When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1852
1853Function : bl1_plat_mboot_finish() [optional]
1854~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1855
1856::
1857
1858 Argument : void
1859 Return : void
1860
1861When the MEASURED_BOOT flag is enabled:
1862
1863- This function is used to finalize the measured boot backend driver(s),
1864 and also, set the information for the next bootloader component to
1865 extend the measurement if needed.
1866- On the Arm FVP port, this function is used to pass the base address of
1867 the Event Log buffer and its size to BL2 via tb_fw_config to extend the
1868 Event Log buffer with the measurement of various images loaded by BL2.
1869 It results in panic on error.
1870
1871When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1872
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001873Boot Loader Stage 2 (BL2)
1874-------------------------
1875
1876The BL2 stage is executed only by the primary CPU, which is determined in BL1
1877using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at
Soby Mathew97b1bff2018-09-27 16:46:41 +01001878``BL2_BASE``. BL2 executes in Secure EL1 and and invokes
1879``plat_get_bl_image_load_info()`` to retrieve the list of images to load from
1880non-volatile storage to secure/non-secure RAM. After all the images are loaded
1881then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable
1882images to be passed to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001883
1884The following functions must be implemented by the platform port to enable BL2
1885to perform the above tasks.
1886
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001887Function : bl2_early_platform_setup2() [mandatory]
1888~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001889
1890::
1891
Soby Mathew97b1bff2018-09-27 16:46:41 +01001892 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001893 Return : void
1894
1895This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001896by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments
1897are platform specific.
1898
1899On Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001900
Manish V Badarkhe81414512020-06-24 15:58:38 +01001901 arg0 - Points to load address of FW_CONFIG
Soby Mathew97b1bff2018-09-27 16:46:41 +01001902
1903 arg1 - ``meminfo`` structure populated by BL1. The platform copies
1904 the contents of ``meminfo`` as it may be subsequently overwritten by BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001905
Dan Handley610e7e12018-03-01 18:44:00 +00001906On Arm standard platforms, this function also:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001907
1908- Initializes a UART (PL011 console), which enables access to the ``printf``
1909 family of functions in BL2.
1910
1911- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001912 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1913 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001914
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001915Function : bl2_plat_arch_setup() [mandatory]
1916~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001917
1918::
1919
1920 Argument : void
1921 Return : void
1922
1923This function executes with the MMU and data caches disabled. It is only called
1924by the primary CPU.
1925
1926The purpose of this function is to perform any architectural initialization
1927that varies across platforms.
1928
Dan Handley610e7e12018-03-01 18:44:00 +00001929On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001930
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001931Function : bl2_platform_setup() [mandatory]
1932~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001933
1934::
1935
1936 Argument : void
1937 Return : void
1938
1939This function may execute with the MMU and data caches enabled if the platform
1940port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only
1941called by the primary CPU.
1942
1943The purpose of this function is to perform any platform initialization
1944specific to BL2.
1945
Dan Handley610e7e12018-03-01 18:44:00 +00001946In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001947configuration of the TrustZone controller to allow non-secure masters access
1948to most of DRAM. Part of DRAM is reserved for secure world use.
1949
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001950Function : bl2_plat_handle_pre_image_load() [optional]
1951~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001952
1953::
1954
1955 Argument : unsigned int
1956 Return : int
1957
1958This function can be used by the platforms to update/use image information
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001959for given ``image_id``. This function is currently invoked in BL2 before
Soby Mathew97b1bff2018-09-27 16:46:41 +01001960loading each image.
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001961
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001962Function : bl2_plat_handle_post_image_load() [optional]
1963~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001964
1965::
1966
1967 Argument : unsigned int
1968 Return : int
1969
1970This function can be used by the platforms to update/use image information
1971for given ``image_id``. This function is currently invoked in BL2 after
Soby Mathew97b1bff2018-09-27 16:46:41 +01001972loading each image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001973
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001974Function : bl2_plat_preload_setup [optional]
1975~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001976
1977::
John Tsichritzisee10e792018-06-06 09:38:10 +01001978
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001979 Argument : void
1980 Return : void
1981
1982This optional function performs any BL2 platform initialization
1983required before image loading, that is not done later in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001984bl2_platform_setup(). Specifically, if support for multiple
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001985boot sources is required, it initializes the boot sequence used by
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001986plat_try_next_boot_source().
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001987
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001988Function : plat_try_next_boot_source() [optional]
1989~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001990
1991::
John Tsichritzisee10e792018-06-06 09:38:10 +01001992
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001993 Argument : void
1994 Return : int
1995
1996This optional function passes to the next boot source in the redundancy
1997sequence.
1998
1999This function moves the current boot redundancy source to the next
2000element in the boot sequence. If there are no more boot sources then it
2001must return 0, otherwise it must return 1. The default implementation
2002of this always returns 0.
2003
Sandrine Bailleuxeb5fadc2022-07-13 10:07:54 +02002004Function : bl2_plat_mboot_init() [optional]
2005~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2006
2007::
2008
2009 Argument : void
2010 Return : void
2011
2012When the MEASURED_BOOT flag is enabled:
2013
2014- This function is used to initialize the backend driver(s) of measured boot.
2015- On the Arm FVP port, this function is used to initialize the Event Log
2016 backend driver with the Event Log buffer information (base address and
2017 size) received from BL1. It results in panic on error.
2018
2019When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
2020
2021Function : bl2_plat_mboot_finish() [optional]
2022~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2023
2024::
2025
2026 Argument : void
2027 Return : void
2028
2029When the MEASURED_BOOT flag is enabled:
2030
2031- This function is used to finalize the measured boot backend driver(s),
2032 and also, set the information for the next bootloader component to extend
2033 the measurement if needed.
2034- On the Arm FVP port, this function is used to pass the Event Log buffer
2035 information (base address and size) to non-secure(BL33) and trusted OS(BL32)
2036 via nt_fw and tos_fw config respectively. It results in panic on error.
2037
2038When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
2039
Roberto Vargasb1584272017-11-20 13:36:10 +00002040Boot Loader Stage 2 (BL2) at EL3
2041--------------------------------
2042
Dan Handley610e7e12018-03-01 18:44:00 +00002043When the platform has a non-TF-A Boot ROM it is desirable to jump
2044directly to BL2 instead of TF-A BL1. In this case BL2 is expected to
Paul Beesleyf8640672019-04-12 14:19:42 +01002045execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design`
2046document for more information.
Roberto Vargasb1584272017-11-20 13:36:10 +00002047
2048All mandatory functions of BL2 must be implemented, except the functions
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002049bl2_early_platform_setup and bl2_el3_plat_arch_setup, because
2050their work is done now by bl2_el3_early_platform_setup and
2051bl2_el3_plat_arch_setup. These functions should generally implement
2052the bl1_plat_xxx() and bl2_plat_xxx() functionality combined.
Roberto Vargasb1584272017-11-20 13:36:10 +00002053
2054
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002055Function : bl2_el3_early_platform_setup() [mandatory]
2056~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00002057
2058::
John Tsichritzisee10e792018-06-06 09:38:10 +01002059
Roberto Vargasb1584272017-11-20 13:36:10 +00002060 Argument : u_register_t, u_register_t, u_register_t, u_register_t
2061 Return : void
2062
2063This function executes with the MMU and data caches disabled. It is only called
2064by the primary CPU. This function receives four parameters which can be used
2065by the platform to pass any needed information from the Boot ROM to BL2.
2066
Dan Handley610e7e12018-03-01 18:44:00 +00002067On Arm standard platforms, this function does the following:
Roberto Vargasb1584272017-11-20 13:36:10 +00002068
2069- Initializes a UART (PL011 console), which enables access to the ``printf``
2070 family of functions in BL2.
2071
2072- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002073 images. It is necessary to do this early on platforms with a SCP_BL2 image,
2074 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Roberto Vargasb1584272017-11-20 13:36:10 +00002075
2076- Initializes the private variables that define the memory layout used.
2077
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002078Function : bl2_el3_plat_arch_setup() [mandatory]
2079~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00002080
2081::
John Tsichritzisee10e792018-06-06 09:38:10 +01002082
Roberto Vargasb1584272017-11-20 13:36:10 +00002083 Argument : void
2084 Return : void
2085
2086This function executes with the MMU and data caches disabled. It is only called
2087by the primary CPU.
2088
2089The purpose of this function is to perform any architectural initialization
2090that varies across platforms.
2091
Dan Handley610e7e12018-03-01 18:44:00 +00002092On Arm standard platforms, this function enables the MMU.
Roberto Vargasb1584272017-11-20 13:36:10 +00002093
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002094Function : bl2_el3_plat_prepare_exit() [optional]
2095~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00002096
2097::
John Tsichritzisee10e792018-06-06 09:38:10 +01002098
Roberto Vargasb1584272017-11-20 13:36:10 +00002099 Argument : void
2100 Return : void
2101
2102This function is called prior to exiting BL2 and run the next image.
2103It should be used to perform platform specific clean up or bookkeeping
2104operations before transferring control to the next image. This function
2105runs with MMU disabled.
2106
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002107FWU Boot Loader Stage 2 (BL2U)
2108------------------------------
2109
2110The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU
2111process and is executed only by the primary CPU. BL1 passes control to BL2U at
2112``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for:
2113
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002114#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure
2115 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1.
2116 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U
2117 should be copied from. Subsequent handling of the SCP_BL2U image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002118 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function.
2119 If ``SCP_BL2U_BASE`` is not defined then this step is not performed.
2120
2121#. Any platform specific setup required to perform the FWU process. For
Dan Handley610e7e12018-03-01 18:44:00 +00002122 example, Arm standard platforms initialize the TZC controller so that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002123 normal world can access DDR memory.
2124
2125The following functions must be implemented by the platform port to enable
2126BL2U to perform the tasks mentioned above.
2127
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002128Function : bl2u_early_platform_setup() [mandatory]
2129~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002130
2131::
2132
2133 Argument : meminfo *mem_info, void *plat_info
2134 Return : void
2135
2136This function executes with the MMU and data caches disabled. It is only
2137called by the primary CPU. The arguments to this function is the address
2138of the ``meminfo`` structure and platform specific info provided by BL1.
2139
2140The platform may copy the contents of the ``mem_info`` and ``plat_info`` into
2141private storage as the original memory may be subsequently overwritten by BL2U.
2142
Dan Handley610e7e12018-03-01 18:44:00 +00002143On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002144to extract SCP_BL2U image information, which is then copied into a private
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002145variable.
2146
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002147Function : bl2u_plat_arch_setup() [mandatory]
2148~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002149
2150::
2151
2152 Argument : void
2153 Return : void
2154
2155This function executes with the MMU and data caches disabled. It is only
2156called by the primary CPU.
2157
2158The purpose of this function is to perform any architectural initialization
2159that varies across platforms, for example enabling the MMU (since the memory
2160map differs across platforms).
2161
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002162Function : bl2u_platform_setup() [mandatory]
2163~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002164
2165::
2166
2167 Argument : void
2168 Return : void
2169
2170This function may execute with the MMU and data caches enabled if the platform
2171port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only
2172called by the primary CPU.
2173
2174The purpose of this function is to perform any platform initialization
2175specific to BL2U.
2176
Dan Handley610e7e12018-03-01 18:44:00 +00002177In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002178configuration of the TrustZone controller to allow non-secure masters access
2179to most of DRAM. Part of DRAM is reserved for secure world use.
2180
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002181Function : bl2u_plat_handle_scp_bl2u() [optional]
2182~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002183
2184::
2185
2186 Argument : void
2187 Return : int
2188
2189This function is used to perform any platform-specific actions required to
2190handle the SCP firmware. Typically it transfers the image into SCP memory using
2191a platform-specific protocol and waits until SCP executes it and signals to the
2192Application Processor (AP) for BL2U execution to continue.
2193
2194This function returns 0 on success, a negative error code otherwise.
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002195This function is included if SCP_BL2U_BASE is defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002196
2197Boot Loader Stage 3-1 (BL31)
2198----------------------------
2199
2200During cold boot, the BL31 stage is executed only by the primary CPU. This is
2201determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes
2202control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all
2203CPUs. BL31 executes at EL3 and is responsible for:
2204
2205#. Re-initializing all architectural and platform state. Although BL1 performs
2206 some of this initialization, BL31 remains resident in EL3 and must ensure
2207 that EL3 architectural and platform state is completely initialized. It
2208 should make no assumptions about the system state when it receives control.
2209
2210#. Passing control to a normal world BL image, pre-loaded at a platform-
Soby Mathew97b1bff2018-09-27 16:46:41 +01002211 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list
2212 populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002213
2214#. Providing runtime firmware services. Currently, BL31 only implements a
2215 subset of the Power State Coordination Interface (PSCI) API as a runtime
Boyan Karatotev907d38b2022-11-22 12:01:09 +00002216 service. See :ref:`psci_in_bl31` below for details of porting the PSCI
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002217 implementation.
2218
2219#. Optionally passing control to the BL32 image, pre-loaded at a platform-
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002220 specific address by BL2. BL31 exports a set of APIs that allow runtime
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002221 services to specify the security state in which the next image should be
Soby Mathew97b1bff2018-09-27 16:46:41 +01002222 executed and run the corresponding image. On ARM platforms, BL31 uses the
2223 ``bl_params`` list populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002224
2225If BL31 is a reset vector, It also needs to handle the reset as specified in
2226section 2.2 before the tasks described above.
2227
2228The following functions must be implemented by the platform port to enable BL31
2229to perform the above tasks.
2230
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002231Function : bl31_early_platform_setup2() [mandatory]
2232~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002233
2234::
2235
Soby Mathew97b1bff2018-09-27 16:46:41 +01002236 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002237 Return : void
2238
2239This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01002240by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are
2241platform specific.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002242
Soby Mathew97b1bff2018-09-27 16:46:41 +01002243In Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002244
Soby Mathew97b1bff2018-09-27 16:46:41 +01002245 arg0 - The pointer to the head of `bl_params_t` list
2246 which is list of executable images following BL31,
2247
2248 arg1 - Points to load address of SOC_FW_CONFIG if present
Mikael Olsson0232da22021-02-12 17:30:16 +01002249 except in case of Arm FVP and Juno platform.
Manish V Badarkhe81414512020-06-24 15:58:38 +01002250
Mikael Olsson0232da22021-02-12 17:30:16 +01002251 In case of Arm FVP and Juno platform, points to load address
Manish V Badarkhe81414512020-06-24 15:58:38 +01002252 of FW_CONFIG.
Soby Mathew97b1bff2018-09-27 16:46:41 +01002253
2254 arg2 - Points to load address of HW_CONFIG if present
2255
2256 arg3 - A special value to verify platform parameters from BL2 to BL31. Not
2257 used in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002258
Soby Mathew97b1bff2018-09-27 16:46:41 +01002259The function runs through the `bl_param_t` list and extracts the entry point
2260information for BL32 and BL33. It also performs the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002261
2262- Initialize a UART (PL011 console), which enables access to the ``printf``
2263 family of functions in BL31.
2264
2265- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the
2266 CCI slave interface corresponding to the cluster that includes the primary
2267 CPU.
2268
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002269Function : bl31_plat_arch_setup() [mandatory]
2270~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002271
2272::
2273
2274 Argument : void
2275 Return : void
2276
2277This function executes with the MMU and data caches disabled. It is only called
2278by the primary CPU.
2279
2280The purpose of this function is to perform any architectural initialization
2281that varies across platforms.
2282
Dan Handley610e7e12018-03-01 18:44:00 +00002283On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002284
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002285Function : bl31_platform_setup() [mandatory]
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002286~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2287
2288::
2289
2290 Argument : void
2291 Return : void
2292
2293This function may execute with the MMU and data caches enabled if the platform
2294port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only
2295called by the primary CPU.
2296
2297The purpose of this function is to complete platform initialization so that both
2298BL31 runtime services and normal world software can function correctly.
2299
Dan Handley610e7e12018-03-01 18:44:00 +00002300On Arm standard platforms, this function does the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002301
2302- Initialize the generic interrupt controller.
2303
2304 Depending on the GIC driver selected by the platform, the appropriate GICv2
2305 or GICv3 initialization will be done, which mainly consists of:
2306
2307 - Enable secure interrupts in the GIC CPU interface.
2308 - Disable the legacy interrupt bypass mechanism.
2309 - Configure the priority mask register to allow interrupts of all priorities
2310 to be signaled to the CPU interface.
2311 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure.
2312 - Target all secure SPIs to CPU0.
2313 - Enable these secure interrupts in the GIC distributor.
2314 - Configure all other interrupts as non-secure.
2315 - Enable signaling of secure interrupts in the GIC distributor.
2316
2317- Enable system-level implementation of the generic timer counter through the
2318 memory mapped interface.
2319
2320- Grant access to the system counter timer module
2321
2322- Initialize the power controller device.
2323
2324 In particular, initialise the locks that prevent concurrent accesses to the
2325 power controller device.
2326
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002327Function : bl31_plat_runtime_setup() [optional]
2328~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002329
2330::
2331
2332 Argument : void
2333 Return : void
2334
2335The purpose of this function is allow the platform to perform any BL31 runtime
2336setup just prior to BL31 exit during cold boot. The default weak
Julius Werneraae9bb12017-09-18 16:49:48 -07002337implementation of this function will invoke ``console_switch_state()`` to switch
2338console output to consoles marked for use in the ``runtime`` state.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002339
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002340Function : bl31_plat_get_next_image_ep_info() [mandatory]
2341~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002342
2343::
2344
Sandrine Bailleux842117d2018-05-14 14:25:47 +02002345 Argument : uint32_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002346 Return : entry_point_info *
2347
2348This function may execute with the MMU and data caches enabled if the platform
2349port does the necessary initializations in ``bl31_plat_arch_setup()``.
2350
2351This function is called by ``bl31_main()`` to retrieve information provided by
2352BL2 for the next image in the security state specified by the argument. BL31
2353uses this information to pass control to that image in the specified security
2354state. This function must return a pointer to the ``entry_point_info`` structure
2355(that was copied during ``bl31_early_platform_setup()``) if the image exists. It
2356should return NULL otherwise.
2357
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002358Function : plat_rmmd_get_cca_attest_token() [mandatory when ENABLE_RME == 1]
Soby Mathew294e1cf2022-03-22 16:19:39 +00002359~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2360
2361::
2362
2363 Argument : uintptr_t, size_t *, uintptr_t, size_t
2364 Return : int
2365
2366This function returns the Platform attestation token.
2367
2368The parameters of the function are:
2369
2370 arg0 - A pointer to the buffer where the Platform token should be copied by
2371 this function. The buffer must be big enough to hold the Platform
2372 token.
2373
2374 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
2375 function returns the platform token length in this parameter.
2376
2377 arg2 - A pointer to the buffer where the challenge object is stored.
2378
2379 arg3 - The length of the challenge object in bytes. Possible values are 32,
2380 48 and 64.
2381
2382The function returns 0 on success, -EINVAL on failure.
2383
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002384Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1]
2385~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewf05d93a2022-03-22 16:21:19 +00002386
2387::
2388
2389 Argument : uintptr_t, size_t *, unsigned int
2390 Return : int
2391
2392This function returns the delegated realm attestation key which will be used to
2393sign Realm attestation token. The API currently only supports P-384 ECC curve
2394key.
2395
2396The parameters of the function are:
2397
2398 arg0 - A pointer to the buffer where the attestation key should be copied
2399 by this function. The buffer must be big enough to hold the
2400 attestation key.
2401
2402 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
2403 function returns the attestation key length in this parameter.
2404
2405 arg2 - The type of the elliptic curve to which the requested attestation key
2406 belongs.
2407
2408The function returns 0 on success, -EINVAL on failure.
2409
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002410Function : plat_rmmd_get_el3_rmm_shared_mem() [when ENABLE_RME == 1]
2411~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2412
2413::
2414
2415 Argument : uintptr_t *
2416 Return : size_t
2417
2418This function returns the size of the shared area between EL3 and RMM (or 0 on
2419failure). A pointer to the shared area (or a NULL pointer on failure) is stored
2420in the pointer passed as argument.
2421
Javier Almansa Sobrino4165e842022-04-25 17:18:15 +01002422Function : plat_rmmd_load_manifest() [when ENABLE_RME == 1]
2423~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2424
2425::
2426
2427 Arguments : rmm_manifest_t *manifest
2428 Return : int
2429
2430When ENABLE_RME is enabled, this function populates a boot manifest for the
2431RMM image and stores it in the area specified by manifest.
2432
2433When ENABLE_RME is disabled, this function is not used.
2434
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01002435Function : bl31_plat_enable_mmu [optional]
2436~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2437
2438::
2439
2440 Argument : uint32_t
2441 Return : void
2442
2443This function enables the MMU. The boot code calls this function with MMU and
2444caches disabled. This function should program necessary registers to enable
2445translation, and upon return, the MMU on the calling PE must be enabled.
2446
2447The function must honor flags passed in the first argument. These flags are
2448defined by the translation library, and can be found in the file
2449``include/lib/xlat_tables/xlat_mmu_helpers.h``.
2450
2451On DynamIQ systems, this function must not use stack while enabling MMU, which
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002452is how the function in xlat table library version 2 is implemented.
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01002453
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002454Function : plat_init_apkey [optional]
2455~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002456
2457::
2458
2459 Argument : void
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002460 Return : uint128_t
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002461
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002462This function returns the 128-bit value which can be used to program ARMv8.3
2463pointer authentication keys.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002464
2465The value should be obtained from a reliable source of randomness.
2466
2467This function is only needed if ARMv8.3 pointer authentication is used in the
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002468Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002469
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002470Function : plat_get_syscnt_freq2() [mandatory]
2471~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002472
2473::
2474
2475 Argument : void
2476 Return : unsigned int
2477
2478This function is used by the architecture setup code to retrieve the counter
2479frequency for the CPU's generic timer. This value will be programmed into the
Dan Handley610e7e12018-03-01 18:44:00 +00002480``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002481of the system counter, which is retrieved from the first entry in the frequency
2482modes table.
2483
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002484#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]
2485~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002486
2487When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in
2488bytes) aligned to the cache line boundary that should be allocated per-cpu to
2489accommodate all the bakery locks.
2490
2491If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker
Chris Kay33bfc5e2023-02-14 11:30:04 +00002492calculates the size of the ``.bakery_lock`` input section, aligns it to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002493nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT``
2494and stores the result in a linker symbol. This constant prevents a platform
2495from relying on the linker and provide a more efficient mechanism for
2496accessing per-cpu bakery lock information.
2497
2498If this constant is defined and its value is not equal to the value
2499calculated by the linker then a link time assertion is raised. A compile time
2500assertion is raised if the value of the constant is not aligned to the cache
2501line boundary.
2502
Paul Beesleyf8640672019-04-12 14:19:42 +01002503.. _porting_guide_sdei_requirements:
2504
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002505SDEI porting requirements
2506~~~~~~~~~~~~~~~~~~~~~~~~~
2507
Paul Beesley606d8072019-03-13 13:58:02 +00002508The |SDEI| dispatcher requires the platform to provide the following macros
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002509and functions, of which some are optional, and some others mandatory.
2510
2511Macros
2512......
2513
2514Macro: PLAT_SDEI_NORMAL_PRI [mandatory]
2515^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2516
2517This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00002518Normal |SDEI| events on the platform. This must have a higher value
2519(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002520
2521Macro: PLAT_SDEI_CRITICAL_PRI [mandatory]
2522^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2523
2524This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00002525Critical |SDEI| events on the platform. This must have a lower value
2526(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002527
Paul Beesley606d8072019-03-13 13:58:02 +00002528**Note**: |SDEI| exception priorities must be the lowest among Secure
2529priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must
2530be higher than Normal |SDEI| priority.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002531
2532Functions
2533.........
2534
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002535Function: int plat_sdei_validate_entry_point() [optional]
2536^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002537
2538::
2539
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002540 Argument: uintptr_t ep, unsigned int client_mode
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002541 Return: int
2542
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002543This function validates the entry point address of the event handler provided by
2544the client for both event registration and *Complete and Resume* |SDEI| calls.
2545The function ensures that the address is valid in the client translation regime.
2546
2547The second argument is the exception level that the client is executing in. It
2548can be Non-Secure EL1 or Non-Secure EL2.
2549
2550The function must return ``0`` for successful validation, or ``-1`` upon failure.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002551
Dan Handley610e7e12018-03-01 18:44:00 +00002552The default implementation always returns ``0``. On Arm platforms, this function
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002553translates the entry point address within the client translation regime and
2554further ensures that the resulting physical address is located in Non-secure
2555DRAM.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002556
2557Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional]
2558^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2559
2560::
2561
2562 Argument: uint64_t
2563 Argument: unsigned int
2564 Return: void
2565
Paul Beesley606d8072019-03-13 13:58:02 +00002566|SDEI| specification requires that a PE comes out of reset with the events
2567masked. The client therefore is expected to call ``PE_UNMASK`` to unmask
2568|SDEI| events on the PE. No |SDEI| events can be dispatched until such
2569time.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002570
Paul Beesley606d8072019-03-13 13:58:02 +00002571Should a PE receive an interrupt that was bound to an |SDEI| event while the
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002572events are masked on the PE, the dispatcher implementation invokes the function
2573``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the
2574interrupt and the interrupt ID are passed as parameters.
2575
2576The default implementation only prints out a warning message.
2577
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -05002578.. _porting_guide_trng_requirements:
2579
2580TRNG porting requirements
2581~~~~~~~~~~~~~~~~~~~~~~~~~
2582
2583The |TRNG| backend requires the platform to provide the following values
2584and mandatory functions.
2585
2586Values
2587......
2588
2589value: uuid_t plat_trng_uuid [mandatory]
2590^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2591
2592This value must be defined to the UUID of the TRNG backend that is specific to
Jayanth Dodderi Chidanand7c7faff2022-10-11 17:16:07 +01002593the hardware after ``plat_entropy_setup`` function is called. This value must
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -05002594conform to the SMCCC calling convention; The most significant 32 bits of the
2595UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in
2596w0 indicates failure to get a TRNG source.
2597
2598Functions
2599.........
2600
2601Function: void plat_entropy_setup(void) [mandatory]
2602^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2603
2604::
2605
2606 Argument: none
2607 Return: none
2608
2609This function is expected to do platform-specific initialization of any TRNG
2610hardware. This may include generating a UUID from a hardware-specific seed.
2611
2612Function: bool plat_get_entropy(uint64_t \*out) [mandatory]
2613^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2614
2615::
2616
2617 Argument: uint64_t *
2618 Return: bool
2619 Out : when the return value is true, the entropy has been written into the
2620 storage pointed to
2621
2622This function writes entropy into storage provided by the caller. If no entropy
2623is available, it must return false and the storage must not be written.
2624
Boyan Karatotev907d38b2022-11-22 12:01:09 +00002625.. _psci_in_bl31:
2626
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002627Power State Coordination Interface (in BL31)
2628--------------------------------------------
2629
Dan Handley610e7e12018-03-01 18:44:00 +00002630The TF-A implementation of the PSCI API is based around the concept of a
2631*power domain*. A *power domain* is a CPU or a logical group of CPUs which
2632share some state on which power management operations can be performed as
2633specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is
2634a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The
2635*power domains* are arranged in a hierarchical tree structure and each
2636*power domain* can be identified in a system by the cpu index of any CPU that
2637is part of that domain and a *power domain level*. A processing element (for
2638example, a CPU) is at level 0. If the *power domain* node above a CPU is a
2639logical grouping of CPUs that share some state, then level 1 is that group of
2640CPUs (for example, a cluster), and level 2 is a group of clusters (for
2641example, the system). More details on the power domain topology and its
Paul Beesleyf8640672019-04-12 14:19:42 +01002642organization can be found in :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002643
2644BL31's platform initialization code exports a pointer to the platform-specific
2645power management operations required for the PSCI implementation to function
2646correctly. This information is populated in the ``plat_psci_ops`` structure. The
2647PSCI implementation calls members of the ``plat_psci_ops`` structure for performing
2648power management operations on the power domains. For example, the target
2649CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()``
2650handler (if present) is called for the CPU power domain.
2651
2652The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to
2653describe composite power states specific to a platform. The PSCI implementation
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00002654defines a generic representation of the power-state parameter, which is an
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002655array of local power states where each index corresponds to a power domain
2656level. Each entry contains the local power state the power domain at that power
2657level could enter. It depends on the ``validate_power_state()`` handler to
2658convert the power-state parameter (possibly encoding a composite power state)
2659passed in a PSCI ``CPU_SUSPEND`` call to this representation.
2660
2661The following functions form part of platform port of PSCI functionality.
2662
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002663Function : plat_psci_stat_accounting_start() [optional]
2664~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002665
2666::
2667
2668 Argument : const psci_power_state_t *
2669 Return : void
2670
2671This is an optional hook that platforms can implement for residency statistics
2672accounting before entering a low power state. The ``pwr_domain_state`` field of
2673``state_info`` (first argument) can be inspected if stat accounting is done
2674differently at CPU level versus higher levels. As an example, if the element at
2675index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2676state, special hardware logic may be programmed in order to keep track of the
2677residency statistics. For higher levels (array indices > 0), the residency
2678statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2679default implementation will use PMF to capture timestamps.
2680
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002681Function : plat_psci_stat_accounting_stop() [optional]
2682~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002683
2684::
2685
2686 Argument : const psci_power_state_t *
2687 Return : void
2688
2689This is an optional hook that platforms can implement for residency statistics
2690accounting after exiting from a low power state. The ``pwr_domain_state`` field
2691of ``state_info`` (first argument) can be inspected if stat accounting is done
2692differently at CPU level versus higher levels. As an example, if the element at
2693index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2694state, special hardware logic may be programmed in order to keep track of the
2695residency statistics. For higher levels (array indices > 0), the residency
2696statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2697default implementation will use PMF to capture timestamps.
2698
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002699Function : plat_psci_stat_get_residency() [optional]
2700~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002701
2702::
2703
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -06002704 Argument : unsigned int, const psci_power_state_t *, unsigned int
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002705 Return : u_register_t
2706
2707This is an optional interface that is is invoked after resuming from a low power
2708state and provides the time spent resident in that low power state by the power
2709domain at a particular power domain level. When a CPU wakes up from suspend,
2710all its parent power domain levels are also woken up. The generic PSCI code
2711invokes this function for each parent power domain that is resumed and it
2712identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second
2713argument) describes the low power state that the power domain has resumed from.
2714The current CPU is the first CPU in the power domain to resume from the low
2715power state and the ``last_cpu_idx`` (third parameter) is the index of the last
2716CPU in the power domain to suspend and may be needed to calculate the residency
2717for that power domain.
2718
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002719Function : plat_get_target_pwr_state() [optional]
2720~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002721
2722::
2723
2724 Argument : unsigned int, const plat_local_state_t *, unsigned int
2725 Return : plat_local_state_t
2726
2727The PSCI generic code uses this function to let the platform participate in
2728state coordination during a power management operation. The function is passed
2729a pointer to an array of platform specific local power state ``states`` (second
2730argument) which contains the requested power state for each CPU at a particular
2731power domain level ``lvl`` (first argument) within the power domain. The function
2732is expected to traverse this array of upto ``ncpus`` (third argument) and return
2733a coordinated target power state by the comparing all the requested power
2734states. The target power state should not be deeper than any of the requested
2735power states.
2736
2737A weak definition of this API is provided by default wherein it assumes
2738that the platform assigns a local state value in order of increasing depth
2739of the power state i.e. for two power states X & Y, if X < Y
2740then X represents a shallower power state than Y. As a result, the
2741coordinated target local power state for a power domain will be the minimum
2742of the requested local power state values.
2743
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002744Function : plat_get_power_domain_tree_desc() [mandatory]
2745~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002746
2747::
2748
2749 Argument : void
2750 Return : const unsigned char *
2751
2752This function returns a pointer to the byte array containing the power domain
2753topology tree description. The format and method to construct this array are
Paul Beesleyf8640672019-04-12 14:19:42 +01002754described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI
2755initialization code requires this array to be described by the platform, either
2756statically or dynamically, to initialize the power domain topology tree. In case
2757the array is populated dynamically, then plat_core_pos_by_mpidr() and
2758plat_my_core_pos() should also be implemented suitably so that the topology tree
2759description matches the CPU indices returned by these APIs. These APIs together
2760form the platform interface for the PSCI topology framework.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002761
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002762Function : plat_setup_psci_ops() [mandatory]
2763~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002764
2765::
2766
2767 Argument : uintptr_t, const plat_psci_ops **
2768 Return : int
2769
2770This function may execute with the MMU and data caches enabled if the platform
2771port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
2772called by the primary CPU.
2773
2774This function is called by PSCI initialization code. Its purpose is to let
2775the platform layer know about the warm boot entrypoint through the
2776``sec_entrypoint`` (first argument) and to export handler routines for
2777platform-specific psci power management actions by populating the passed
2778pointer with a pointer to BL31's private ``plat_psci_ops`` structure.
2779
2780A description of each member of this structure is given below. Please refer to
Dan Handley610e7e12018-03-01 18:44:00 +00002781the Arm FVP specific implementation of these handlers in
Paul Beesleyf8640672019-04-12 14:19:42 +01002782``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002783platform wants to support, the associated operation or operations in this
2784structure must be provided and implemented (Refer section 4 of
Paul Beesleyf8640672019-04-12 14:19:42 +01002785:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI
Dan Handley610e7e12018-03-01 18:44:00 +00002786function in a platform port, the operation should be removed from this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002787structure instead of providing an empty implementation.
2788
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002789plat_psci_ops.cpu_standby()
2790...........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002791
2792Perform the platform-specific actions to enter the standby state for a cpu
2793indicated by the passed argument. This provides a fast path for CPU standby
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002794wherein overheads of PSCI state management and lock acquisition is avoided.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002795For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation,
2796the suspend state type specified in the ``power-state`` parameter should be
2797STANDBY and the target power domain level specified should be the CPU. The
2798handler should put the CPU into a low power retention state (usually by
2799issuing a wfi instruction) and ensure that it can be woken up from that
2800state by a normal interrupt. The generic code expects the handler to succeed.
2801
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002802plat_psci_ops.pwr_domain_on()
2803.............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002804
2805Perform the platform specific actions to power on a CPU, specified
2806by the ``MPIDR`` (first argument). The generic code expects the platform to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002807return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002808
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002809plat_psci_ops.pwr_domain_off()
2810..............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002811
2812Perform the platform specific actions to prepare to power off the calling CPU
2813and its higher parent power domain levels as indicated by the ``target_state``
2814(first argument). It is called by the PSCI ``CPU_OFF`` API implementation.
2815
2816The ``target_state`` encodes the platform coordinated target local power states
2817for the CPU power domain and its parent power domain levels. The handler
2818needs to perform power management operation corresponding to the local state
2819at each power level.
2820
2821For this handler, the local power state for the CPU power domain will be a
2822power down state where as it could be either power down, retention or run state
2823for the higher power domain levels depending on the result of state
2824coordination. The generic code expects the handler to succeed.
2825
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002826plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]
2827...........................................................
Varun Wadekarae87f4b2017-07-10 16:02:05 -07002828
2829This optional function may be used as a performance optimization to replace
2830or complement pwr_domain_suspend() on some platforms. Its calling semantics
2831are identical to pwr_domain_suspend(), except the PSCI implementation only
2832calls this function when suspending to a power down state, and it guarantees
2833that data caches are enabled.
2834
2835When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches
2836before calling pwr_domain_suspend(). If the target_state corresponds to a
2837power down state and it is safe to perform some or all of the platform
2838specific actions in that function with data caches enabled, it may be more
2839efficient to move those actions to this function. When HW_ASSISTED_COHERENCY
2840= 1, data caches remain enabled throughout, and so there is no advantage to
2841moving platform specific actions to this function.
2842
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002843plat_psci_ops.pwr_domain_suspend()
2844..................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002845
2846Perform the platform specific actions to prepare to suspend the calling
2847CPU and its higher parent power domain levels as indicated by the
2848``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND``
2849API implementation.
2850
2851The ``target_state`` has a similar meaning as described in
2852the ``pwr_domain_off()`` operation. It encodes the platform coordinated
2853target local power states for the CPU power domain and its parent
2854power domain levels. The handler needs to perform power management operation
2855corresponding to the local state at each power level. The generic code
2856expects the handler to succeed.
2857
Douglas Raillarda84996b2017-08-02 16:57:32 +01002858The difference between turning a power domain off versus suspending it is that
2859in the former case, the power domain is expected to re-initialize its state
2860when it is next powered on (see ``pwr_domain_on_finish()``). In the latter
2861case, the power domain is expected to save enough state so that it can resume
2862execution by restoring this state when its powered on (see
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002863``pwr_domain_suspend_finish()``).
2864
Douglas Raillarda84996b2017-08-02 16:57:32 +01002865When suspending a core, the platform can also choose to power off the GICv3
2866Redistributor and ITS through an implementation-defined sequence. To achieve
2867this safely, the ITS context must be saved first. The architectural part is
2868implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed
2869sequence is implementation defined and it is therefore the responsibility of
2870the platform code to implement the necessary sequence. Then the GIC
2871Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper.
2872Powering off the Redistributor requires the implementation to support it and it
2873is the responsibility of the platform code to execute the right implementation
2874defined sequence.
2875
2876When a system suspend is requested, the platform can also make use of the
2877``gicv3_distif_save()`` helper to save the context of the GIC Distributor after
2878it has saved the context of the Redistributors and ITS of all the cores in the
2879system. The context of the Distributor can be large and may require it to be
2880allocated in a special area if it cannot fit in the platform's global static
2881data, for example in DRAM. The Distributor can then be powered down using an
2882implementation-defined sequence.
2883
Wing Li2c556f32022-09-14 13:18:17 -07002884If the build option ``PSCI_OS_INIT_MODE`` is enabled, the generic code expects
2885the platform to return PSCI_E_SUCCESS on success, or either PSCI_E_DENIED or
2886PSCI_E_INVALID_PARAMS as appropriate for any invalid requests.
2887
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002888plat_psci_ops.pwr_domain_pwr_down_wfi()
2889.......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002890
2891This is an optional function and, if implemented, is expected to perform
2892platform specific actions including the ``wfi`` invocation which allows the
2893CPU to powerdown. Since this function is invoked outside the PSCI locks,
2894the actions performed in this hook must be local to the CPU or the platform
2895must ensure that races between multiple CPUs cannot occur.
2896
2897The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()``
2898operation and it encodes the platform coordinated target local power states for
2899the CPU power domain and its parent power domain levels. This function must
Boyan Karatotev43771f32022-10-05 13:41:56 +01002900not return back to the caller (by calling wfi in an infinite loop to ensure
2901some CPUs power down mitigations work properly).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002902
2903If this function is not implemented by the platform, PSCI generic
2904implementation invokes ``psci_power_down_wfi()`` for power down.
2905
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002906plat_psci_ops.pwr_domain_on_finish()
2907....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002908
2909This function is called by the PSCI implementation after the calling CPU is
2910powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
2911It performs the platform-specific setup required to initialize enough state for
2912this CPU to enter the normal world and also provide secure runtime firmware
2913services.
2914
2915The ``target_state`` (first argument) is the prior state of the power domains
2916immediately before the CPU was turned on. It indicates which power domains
2917above the CPU might require initialization due to having previously been in
2918low power states. The generic code expects the handler to succeed.
2919
Madhukar Pappireddy33bd5142019-08-12 18:31:33 -05002920plat_psci_ops.pwr_domain_on_finish_late() [optional]
2921...........................................................
2922
2923This optional function is called by the PSCI implementation after the calling
2924CPU is fully powered on with respective data caches enabled. The calling CPU and
2925the associated cluster are guaranteed to be participating in coherency. This
2926function gives the flexibility to perform any platform-specific actions safely,
2927such as initialization or modification of shared data structures, without the
2928overhead of explicit cache maintainace operations.
2929
2930The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()``
2931operation. The generic code expects the handler to succeed.
2932
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002933plat_psci_ops.pwr_domain_suspend_finish()
2934.........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002935
2936This function is called by the PSCI implementation after the calling CPU is
2937powered on and released from reset in response to an asynchronous wakeup
2938event, for example a timer interrupt that was programmed by the CPU during the
2939``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
2940setup required to restore the saved state for this CPU to resume execution
2941in the normal world and also provide secure runtime firmware services.
2942
2943The ``target_state`` (first argument) has a similar meaning as described in
2944the ``pwr_domain_on_finish()`` operation. The generic code expects the platform
2945to succeed.
2946
Douglas Raillarda84996b2017-08-02 16:57:32 +01002947If the Distributor, Redistributors or ITS have been powered off as part of a
2948suspend, their context must be restored in this function in the reverse order
2949to how they were saved during suspend sequence.
2950
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002951plat_psci_ops.system_off()
2952..........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002953
2954This function is called by PSCI implementation in response to a ``SYSTEM_OFF``
2955call. It performs the platform-specific system poweroff sequence after
2956notifying the Secure Payload Dispatcher.
2957
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002958plat_psci_ops.system_reset()
2959............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002960
2961This function is called by PSCI implementation in response to a ``SYSTEM_RESET``
2962call. It performs the platform-specific system reset sequence after
2963notifying the Secure Payload Dispatcher.
2964
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002965plat_psci_ops.validate_power_state()
2966....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002967
2968This function is called by the PSCI implementation during the ``CPU_SUSPEND``
2969call to validate the ``power_state`` parameter of the PSCI API and if valid,
2970populate it in ``req_state`` (second argument) array as power domain level
2971specific local states. If the ``power_state`` is invalid, the platform must
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002972return PSCI_E_INVALID_PARAMS as error, which is propagated back to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002973normal world PSCI client.
2974
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002975plat_psci_ops.validate_ns_entrypoint()
2976......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002977
2978This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
2979``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point``
2980parameter passed by the normal world. If the ``entry_point`` is invalid,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002981the platform must return PSCI_E_INVALID_ADDRESS as error, which is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002982propagated back to the normal world PSCI client.
2983
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002984plat_psci_ops.get_sys_suspend_power_state()
2985...........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002986
2987This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
2988call to get the ``req_state`` parameter from platform which encodes the power
2989domain level specific local states to suspend to system affinity level. The
2990``req_state`` will be utilized to do the PSCI state coordination and
2991``pwr_domain_suspend()`` will be invoked with the coordinated target state to
2992enter system suspend.
2993
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002994plat_psci_ops.get_pwr_lvl_state_idx()
2995.....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002996
2997This is an optional function and, if implemented, is invoked by the PSCI
2998implementation to convert the ``local_state`` (first argument) at a specified
2999``pwr_lvl`` (second argument) to an index between 0 and
3000``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform
3001supports more than two local power states at each power domain level, that is
3002``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these
3003local power states.
3004
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003005plat_psci_ops.translate_power_state_by_mpidr()
3006..............................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003007
3008This is an optional function and, if implemented, verifies the ``power_state``
3009(second argument) parameter of the PSCI API corresponding to a target power
3010domain. The target power domain is identified by using both ``MPIDR`` (first
3011argument) and the power domain level encoded in ``power_state``. The power domain
3012level specific local states are to be extracted from ``power_state`` and be
3013populated in the ``output_state`` (third argument) array. The functionality
3014is similar to the ``validate_power_state`` function described above and is
3015envisaged to be used in case the validity of ``power_state`` depend on the
3016targeted power domain. If the ``power_state`` is invalid for the targeted power
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003017domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003018function is not implemented, then the generic implementation relies on
3019``validate_power_state`` function to translate the ``power_state``.
3020
3021This function can also be used in case the platform wants to support local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003022power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003023APIs as described in Section 5.18 of `PSCI`_.
3024
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003025plat_psci_ops.get_node_hw_state()
3026.................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003027
3028This is an optional function. If implemented this function is intended to return
3029the power state of a node (identified by the first parameter, the ``MPIDR``) in
3030the power domain topology (identified by the second parameter, ``power_level``),
3031as retrieved from a power controller or equivalent component on the platform.
3032Upon successful completion, the implementation must map and return the final
3033status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it
3034must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as
3035appropriate.
3036
3037Implementations are not expected to handle ``power_levels`` greater than
3038``PLAT_MAX_PWR_LVL``.
3039
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003040plat_psci_ops.system_reset2()
3041.............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01003042
3043This is an optional function. If implemented this function is
3044called during the ``SYSTEM_RESET2`` call to perform a reset
3045based on the first parameter ``reset_type`` as specified in
3046`PSCI`_. The parameter ``cookie`` can be used to pass additional
3047reset information. If the ``reset_type`` is not supported, the
3048function must return ``PSCI_E_NOT_SUPPORTED``. For architectural
3049resets, all failures must return ``PSCI_E_INVALID_PARAMETERS``
3050and vendor reset can return other PSCI error codes as defined
3051in `PSCI`_. On success this function will not return.
3052
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003053plat_psci_ops.write_mem_protect()
3054.................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01003055
3056This is an optional function. If implemented it enables or disables the
3057``MEM_PROTECT`` functionality based on the value of ``val``.
3058A non-zero value enables ``MEM_PROTECT`` and a value of zero
3059disables it. Upon encountering failures it must return a negative value
3060and on success it must return 0.
3061
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003062plat_psci_ops.read_mem_protect()
3063................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01003064
3065This is an optional function. If implemented it returns the current
3066state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering
3067failures it must return a negative value and on success it must
3068return 0.
3069
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003070plat_psci_ops.mem_protect_chk()
3071...............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01003072
3073This is an optional function. If implemented it checks if a memory
3074region defined by a base address ``base`` and with a size of ``length``
3075bytes is protected by ``MEM_PROTECT``. If the region is protected
3076then it must return 0, otherwise it must return a negative number.
3077
Paul Beesleyf8640672019-04-12 14:19:42 +01003078.. _porting_guide_imf_in_bl31:
3079
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003080Interrupt Management framework (in BL31)
3081----------------------------------------
3082
3083BL31 implements an Interrupt Management Framework (IMF) to manage interrupts
3084generated in either security state and targeted to EL1 or EL2 in the non-secure
3085state or EL3/S-EL1 in the secure state. The design of this framework is
Paul Beesleyf8640672019-04-12 14:19:42 +01003086described in the :ref:`Interrupt Management Framework`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003087
3088A platform should export the following APIs to support the IMF. The following
Paul Beesley1fbc97b2019-01-11 18:26:51 +00003089text briefly describes each API and its implementation in Arm standard
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003090platforms. The API implementation depends upon the type of interrupt controller
Dan Handley610e7e12018-03-01 18:44:00 +00003091present in the platform. Arm standard platform layer supports both
3092`Arm Generic Interrupt Controller version 2.0 (GICv2)`_
3093and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the
3094FVP can be configured to use either GICv2 or GICv3 depending on the build flag
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01003095``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more
3096details).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003097
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05003098See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`.
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01003099
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003100Function : plat_interrupt_type_to_line() [mandatory]
3101~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003102
3103::
3104
3105 Argument : uint32_t, uint32_t
3106 Return : uint32_t
3107
Dan Handley610e7e12018-03-01 18:44:00 +00003108The Arm processor signals an interrupt exception either through the IRQ or FIQ
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003109interrupt line. The specific line that is signaled depends on how the interrupt
3110controller (IC) reports different interrupt types from an execution context in
3111either security state. The IMF uses this API to determine which interrupt line
3112the platform IC uses to signal each type of interrupt supported by the framework
3113from a given security state. This API must be invoked at EL3.
3114
3115The first parameter will be one of the ``INTR_TYPE_*`` values (see
Paul Beesleyf8640672019-04-12 14:19:42 +01003116:ref:`Interrupt Management Framework`) indicating the target type of the
3117interrupt, the second parameter is the security state of the originating
3118execution context. The return result is the bit position in the ``SCR_EL3``
3119register of the respective interrupt trap: IRQ=1, FIQ=2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003120
Dan Handley610e7e12018-03-01 18:44:00 +00003121In the case of Arm standard platforms using GICv2, S-EL1 interrupts are
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003122configured as FIQs and Non-secure interrupts as IRQs from either security
3123state.
3124
Dan Handley610e7e12018-03-01 18:44:00 +00003125In the case of Arm standard platforms using GICv3, the interrupt line to be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003126configured depends on the security state of the execution context when the
3127interrupt is signalled and are as follows:
3128
3129- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in
3130 NS-EL0/1/2 context.
3131- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ
3132 in the NS-EL0/1/2 context.
3133- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2
3134 context.
3135
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003136Function : plat_ic_get_pending_interrupt_type() [mandatory]
3137~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003138
3139::
3140
3141 Argument : void
3142 Return : uint32_t
3143
3144This API returns the type of the highest priority pending interrupt at the
3145platform IC. The IMF uses the interrupt type to retrieve the corresponding
3146handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt
3147pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``,
3148``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3.
3149
Dan Handley610e7e12018-03-01 18:44:00 +00003150In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003151Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of
3152the pending interrupt. The type of interrupt depends upon the id value as
3153follows.
3154
3155#. id < 1022 is reported as a S-EL1 interrupt
3156#. id = 1022 is reported as a Non-secure interrupt.
3157#. id = 1023 is reported as an invalid interrupt type.
3158
Dan Handley610e7e12018-03-01 18:44:00 +00003159In the case of Arm standard platforms using GICv3, the system register
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003160``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*,
3161is read to determine the id of the pending interrupt. The type of interrupt
3162depends upon the id value as follows.
3163
3164#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt
3165#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt.
3166#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type.
3167#. All other interrupt id's are reported as EL3 interrupt.
3168
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003169Function : plat_ic_get_pending_interrupt_id() [mandatory]
3170~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003171
3172::
3173
3174 Argument : void
3175 Return : uint32_t
3176
3177This API returns the id of the highest priority pending interrupt at the
3178platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt
3179pending.
3180
Dan Handley610e7e12018-03-01 18:44:00 +00003181In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003182Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the
3183pending interrupt. The id that is returned by API depends upon the value of
3184the id read from the interrupt controller as follows.
3185
3186#. id < 1022. id is returned as is.
3187#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register*
3188 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt.
3189 This id is returned by the API.
3190#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned.
3191
Dan Handley610e7e12018-03-01 18:44:00 +00003192In the case of Arm standard platforms using GICv3, if the API is invoked from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003193EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt
3194group 0 Register*, is read to determine the id of the pending interrupt. The id
3195that is returned by API depends upon the value of the id read from the
3196interrupt controller as follows.
3197
3198#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is.
3199#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system
3200 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1
3201 Register* is read to determine the id of the group 1 interrupt. This id
3202 is returned by the API as long as it is a valid interrupt id
3203#. If the id is any of the special interrupt identifiers,
3204 ``INTR_ID_UNAVAILABLE`` is returned.
3205
3206When the API invoked from S-EL1 for GICv3 systems, the id read from system
3207register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003208Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003209``INTR_ID_UNAVAILABLE`` is returned.
3210
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003211Function : plat_ic_acknowledge_interrupt() [mandatory]
3212~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003213
3214::
3215
3216 Argument : void
3217 Return : uint32_t
3218
3219This API is used by the CPU to indicate to the platform IC that processing of
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01003220the highest pending interrupt has begun. It should return the raw, unmodified
3221value obtained from the interrupt controller when acknowledging an interrupt.
3222The actual interrupt number shall be extracted from this raw value using the API
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05003223`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003224
Dan Handley610e7e12018-03-01 18:44:00 +00003225This function in Arm standard platforms using GICv2, reads the *Interrupt
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003226Acknowledge Register* (``GICC_IAR``). This changes the state of the highest
3227priority pending interrupt from pending to active in the interrupt controller.
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01003228It returns the value read from the ``GICC_IAR``, unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003229
Dan Handley610e7e12018-03-01 18:44:00 +00003230In the case of Arm standard platforms using GICv3, if the API is invoked
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003231from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt
3232Acknowledge Register group 0*. If the API is invoked from S-EL1, the function
3233reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register
3234group 1*. The read changes the state of the highest pending interrupt from
3235pending to active in the interrupt controller. The value read is returned
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01003236unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003237
3238The TSP uses this API to start processing of the secure physical timer
3239interrupt.
3240
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003241Function : plat_ic_end_of_interrupt() [mandatory]
3242~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003243
3244::
3245
3246 Argument : uint32_t
3247 Return : void
3248
3249This API is used by the CPU to indicate to the platform IC that processing of
3250the interrupt corresponding to the id (passed as the parameter) has
3251finished. The id should be the same as the id returned by the
3252``plat_ic_acknowledge_interrupt()`` API.
3253
Dan Handley610e7e12018-03-01 18:44:00 +00003254Arm standard platforms write the id to the *End of Interrupt Register*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003255(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1``
3256system register in case of GICv3 depending on where the API is invoked from,
3257EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt
3258controller.
3259
3260The TSP uses this API to finish processing of the secure physical timer
3261interrupt.
3262
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003263Function : plat_ic_get_interrupt_type() [mandatory]
3264~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003265
3266::
3267
3268 Argument : uint32_t
3269 Return : uint32_t
3270
3271This API returns the type of the interrupt id passed as the parameter.
3272``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid
3273interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is
3274returned depending upon how the interrupt has been configured by the platform
3275IC. This API must be invoked at EL3.
3276
Dan Handley610e7e12018-03-01 18:44:00 +00003277Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003278and Non-secure interrupts as Group1 interrupts. It reads the group value
3279corresponding to the interrupt id from the relevant *Interrupt Group Register*
3280(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt.
3281
Dan Handley610e7e12018-03-01 18:44:00 +00003282In the case of Arm standard platforms using GICv3, both the *Interrupt Group
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003283Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register*
3284(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured
3285as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt.
3286
Manish Pandey3161fa52022-11-02 16:30:09 +00003287Common helper functions
3288-----------------------
Govindraj Rajab6709b02023-02-21 17:43:55 +00003289Function : elx_panic()
3290~~~~~~~~~~~~~~~~~~~~~~
Manish Pandey3161fa52022-11-02 16:30:09 +00003291
Govindraj Rajab6709b02023-02-21 17:43:55 +00003292::
3293
3294 Argument : void
3295 Return : void
3296
3297This API is called from assembly files when reporting a critical failure
3298that has occured in lower EL and is been trapped in EL3. This call
3299**must not** return.
Manish Pandey3161fa52022-11-02 16:30:09 +00003300
Govindraj Rajaa796b1b2023-01-16 17:35:07 +00003301Function : el3_panic()
3302~~~~~~~~~~~~~~~~~~~~~~
Manish Pandey3161fa52022-11-02 16:30:09 +00003303
3304::
3305
3306 Argument : void
3307 Return : void
3308
3309This API is called from assembly files when encountering a critical failure that
Govindraj Rajaa796b1b2023-01-16 17:35:07 +00003310cannot be recovered from. This function assumes that it is invoked from a C
3311runtime environment i.e. valid stack exists. This call **must not** return.
Manish Pandey3161fa52022-11-02 16:30:09 +00003312
3313Function : panic()
3314~~~~~~~~~~~~~~~~~~
3315
3316::
3317
3318 Argument : void
3319 Return : void
3320
3321This API called from C files when encountering a critical failure that cannot
3322be recovered from. This function in turn prints backtrace (if enabled) and calls
Govindraj Rajaa796b1b2023-01-16 17:35:07 +00003323el3_panic(). This call **must not** return.
Manish Pandey3161fa52022-11-02 16:30:09 +00003324
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003325Crash Reporting mechanism (in BL31)
3326-----------------------------------
3327
3328BL31 implements a crash reporting mechanism which prints the various registers
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01003329of the CPU to enable quick crash analysis and debugging. This mechanism relies
Paul Beesley1fbc97b2019-01-11 18:26:51 +00003330on the platform implementing ``plat_crash_console_init``,
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01003331``plat_crash_console_putc`` and ``plat_crash_console_flush``.
3332
3333The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample
3334implementation of all of them. Platforms may include this file to their
3335makefiles in order to benefit from them. By default, they will cause the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07003336output to be routed over the normal console infrastructure and get printed on
3337consoles configured to output in crash state. ``console_set_scope()`` can be
3338used to control whether a console is used for crash output.
Paul Beesleyba3ed402019-03-13 16:20:44 +00003339
3340.. note::
3341 Platforms are responsible for making sure that they only mark consoles for
3342 use in the crash scope that are able to support this, i.e. that are written
3343 in assembly and conform with the register clobber rules for putc()
3344 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003345
Julius Werneraae9bb12017-09-18 16:49:48 -07003346In some cases (such as debugging very early crashes that happen before the
3347normal boot console can be set up), platforms may want to control crash output
Julius Werner1338c9c2018-11-19 14:25:55 -08003348more explicitly. These platforms may instead provide custom implementations for
3349these. They are executed outside of a C environment and without a stack. Many
3350console drivers provide functions named ``console_xxx_core_init/putc/flush``
3351that are designed to be used by these functions. See Arm platforms (like juno)
3352for an example of this.
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01003353
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003354Function : plat_crash_console_init [mandatory]
3355~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003356
3357::
3358
3359 Argument : void
3360 Return : int
3361
3362This API is used by the crash reporting mechanism to initialize the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07003363console. It must only use the general purpose registers x0 through x7 to do the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003364initialization and returns 1 on success.
3365
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003366Function : plat_crash_console_putc [mandatory]
3367~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003368
3369::
3370
3371 Argument : int
3372 Return : int
3373
3374This API is used by the crash reporting mechanism to print a character on the
3375designated crash console. It must only use general purpose registers x1 and
3376x2 to do its work. The parameter and the return value are in general purpose
3377register x0.
3378
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003379Function : plat_crash_console_flush [mandatory]
3380~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003381
3382::
3383
3384 Argument : void
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05003385 Return : void
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003386
3387This API is used by the crash reporting mechanism to force write of all buffered
3388data on the designated crash console. It should only use general purpose
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05003389registers x0 through x5 to do its work.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003390
Manish Pandey9c9f38a2020-06-30 00:46:08 +01003391.. _External Abort handling and RAS Support:
3392
Jeenu Viswambharane34bf582018-10-12 08:48:36 +01003393External Abort handling and RAS Support
3394---------------------------------------
Jeenu Viswambharanbf235bc2018-07-12 10:00:01 +01003395
3396Function : plat_ea_handler
3397~~~~~~~~~~~~~~~~~~~~~~~~~~
3398
3399::
3400
3401 Argument : int
3402 Argument : uint64_t
3403 Argument : void *
3404 Argument : void *
3405 Argument : uint64_t
3406 Return : void
3407
3408This function is invoked by the RAS framework for the platform to handle an
3409External Abort received at EL3. The intention of the function is to attempt to
3410resolve the cause of External Abort and return; if that's not possible, to
3411initiate orderly shutdown of the system.
3412
3413The first parameter (``int ea_reason``) indicates the reason for External Abort.
3414Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``.
3415
3416The second parameter (``uint64_t syndrome``) is the respective syndrome
3417presented to EL3 after having received the External Abort. Depending on the
3418nature of the abort (as can be inferred from the ``ea_reason`` parameter), this
3419can be the content of either ``ESR_EL3`` or ``DISR_EL1``.
3420
3421The third parameter (``void *cookie``) is unused for now. The fourth parameter
3422(``void *handle``) is a pointer to the preempted context. The fifth parameter
3423(``uint64_t flags``) indicates the preempted security state. These parameters
3424are received from the top-level exception handler.
3425
3426If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this
3427function iterates through RAS handlers registered by the platform. If any of the
3428RAS handlers resolve the External Abort, no further action is taken.
3429
3430If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers
3431could resolve the External Abort, the default implementation prints an error
3432message, and panics.
3433
3434Function : plat_handle_uncontainable_ea
3435~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3436
3437::
3438
3439 Argument : int
3440 Argument : uint64_t
3441 Return : void
3442
3443This function is invoked by the RAS framework when an External Abort of
3444Uncontainable type is received at EL3. Due to the critical nature of
3445Uncontainable errors, the intention of this function is to initiate orderly
3446shutdown of the system, and is not expected to return.
3447
3448This function must be implemented in assembly.
3449
3450The first and second parameters are the same as that of ``plat_ea_handler``.
3451
3452The default implementation of this function calls
3453``report_unhandled_exception``.
3454
3455Function : plat_handle_double_fault
3456~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3457
3458::
3459
3460 Argument : int
3461 Argument : uint64_t
3462 Return : void
3463
3464This function is invoked by the RAS framework when another External Abort is
3465received at EL3 while one is already being handled. I.e., a call to
3466``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of
3467this function is to initiate orderly shutdown of the system, and is not expected
3468recover or return.
3469
3470This function must be implemented in assembly.
3471
3472The first and second parameters are the same as that of ``plat_ea_handler``.
3473
3474The default implementation of this function calls
3475``report_unhandled_exception``.
3476
3477Function : plat_handle_el3_ea
3478~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3479
3480::
3481
3482 Return : void
3483
3484This function is invoked when an External Abort is received while executing in
3485EL3. Due to its critical nature, the intention of this function is to initiate
3486orderly shutdown of the system, and is not expected recover or return.
3487
3488This function must be implemented in assembly.
3489
3490The default implementation of this function calls
3491``report_unhandled_exception``.
3492
Andre Przywarabdc76f12022-11-21 17:07:25 +00003493Function : plat_handle_rng_trap
3494~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3495
3496::
3497
3498 Argument : uint64_t
3499 Argument : cpu_context_t *
3500 Return : int
3501
3502This function is invoked by BL31's exception handler when there is a synchronous
3503system register trap caused by access to the RNDR or RNDRRS registers. It allows
3504platforms implementing ``FEAT_RNG_TRAP`` and enabling ``ENABLE_FEAT_RNG_TRAP`` to
3505emulate those system registers by returing back some entropy to the lower EL.
3506
3507The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3
3508syndrome register, which encodes the instruction that was trapped. The interesting
3509information in there is the target register (``get_sysreg_iss_rt()``).
3510
3511The second parameter (``cpu_context_t *ctx``) represents the CPU state in the
3512lower exception level, at the time when the execution of the ``mrs`` instruction
3513was trapped. Its content can be changed, to put the entropy into the target
3514register.
3515
3516The return value indicates how to proceed:
3517
3518- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic.
3519- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return
3520 to the same instruction, so its execution will be repeated.
3521- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return
3522 to the next instruction.
3523
3524This function needs to be implemented by a platform if it enables FEAT_RNG_TRAP.
3525
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003526Build flags
3527-----------
3528
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003529There are some build flags which can be defined by the platform to control
3530inclusion or exclusion of certain BL stages from the FIP image. These flags
3531need to be defined in the platform makefile which will get included by the
3532build system.
3533
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003534- **NEED_BL33**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003535 By default, this flag is defined ``yes`` by the build system and ``BL33``
3536 build option should be supplied as a build option. The platform has the
3537 option of excluding the BL33 image in the ``fip`` image by defining this flag
3538 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE``
3539 are used, this flag will be set to ``no`` automatically.
3540
Paul Beesley07f0a312019-05-16 13:33:18 +01003541Platform include paths
3542----------------------
3543
3544Platforms are allowed to add more include paths to be passed to the compiler.
3545The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in
3546particular for the file ``platform_def.h``.
3547
3548Example:
3549
3550.. code:: c
3551
3552 PLAT_INCLUDES += -Iinclude/plat/myplat/include
3553
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003554C Library
3555---------
3556
3557To avoid subtle toolchain behavioral dependencies, the header files provided
3558by the compiler are not used. The software is built with the ``-nostdinc`` flag
3559to ensure no headers are included from the toolchain inadvertently. Instead the
Dan Handley610e7e12018-03-01 18:44:00 +00003560required headers are included in the TF-A source tree. The library only
3561contains those C library definitions required by the local implementation. If
3562more functionality is required, the needed library functions will need to be
3563added to the local implementation.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003564
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003565Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have
Paul Beesleyf2ec7142019-10-04 16:17:46 +00003566been written specifically for TF-A. Some implementation files have been obtained
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003567from `FreeBSD`_, others have been written specifically for TF-A as well. The
3568files can be found in ``include/lib/libc`` and ``lib/libc``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003569
Sandrine Bailleux6f0ecd72019-02-08 14:46:42 +01003570SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources
3571can be obtained from http://github.com/freebsd/freebsd.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003572
3573Storage abstraction layer
3574-------------------------
3575
Louis Mayencourtb5469002019-07-15 13:56:03 +01003576In order to improve platform independence and portability a storage abstraction
3577layer is used to load data from non-volatile platform storage. Currently
3578storage access is only required by BL1 and BL2 phases and performed inside the
3579``load_image()`` function in ``bl_common.c``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003580
Louis Mayencourtb5469002019-07-15 13:56:03 +01003581.. uml:: ../resources/diagrams/plantuml/io_framework_usage_overview.puml
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003582
Dan Handley610e7e12018-03-01 18:44:00 +00003583It is mandatory to implement at least one storage driver. For the Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003584development platforms the Firmware Image Package (FIP) driver is provided as
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01003585the default means to load data from storage (see :ref:`firmware_design_fip`).
3586The storage layer is described in the header file
3587``include/drivers/io/io_storage.h``. The implementation of the common library is
3588in ``drivers/io/io_storage.c`` and the driver files are located in
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003589``drivers/io/``.
3590
Louis Mayencourtb5469002019-07-15 13:56:03 +01003591.. uml:: ../resources/diagrams/plantuml/io_arm_class_diagram.puml
3592
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003593Each IO driver must provide ``io_dev_*`` structures, as described in
3594``drivers/io/io_driver.h``. These are returned via a mandatory registration
3595function that is called on platform initialization. The semi-hosting driver
3596implementation in ``io_semihosting.c`` can be used as an example.
3597
Louis Mayencourtb5469002019-07-15 13:56:03 +01003598Each platform should register devices and their drivers via the storage
3599abstraction layer. These drivers then need to be initialized by bootloader
3600phases as required in their respective ``blx_platform_setup()`` functions.
3601
3602.. uml:: ../resources/diagrams/plantuml/io_dev_registration.puml
3603
3604The storage abstraction layer provides mechanisms (``io_dev_init()``) to
3605initialize storage devices before IO operations are called.
3606
3607.. uml:: ../resources/diagrams/plantuml/io_dev_init_and_check.puml
3608
3609The basic operations supported by the layer
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003610include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``.
3611Drivers do not have to implement all operations, but each platform must
3612provide at least one driver for a device capable of supporting generic
3613operations such as loading a bootloader image.
3614
3615The current implementation only allows for known images to be loaded by the
3616firmware. These images are specified by using their identifiers, as defined in
Antonio Nino Diaz645feb42019-02-13 14:07:38 +00003617``include/plat/common/common_def.h`` (or a separate header file included from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003618there). The platform layer (``plat_get_image_source()``) then returns a reference
3619to a device and a driver-specific ``spec`` which will be understood by the driver
3620to allow access to the image data.
3621
3622The layer is designed in such a way that is it possible to chain drivers with
3623other drivers. For example, file-system drivers may be implemented on top of
3624physical block devices, both represented by IO devices with corresponding
3625drivers. In such a case, the file-system "binding" with the block device may
3626be deferred until the file-system device is initialised.
3627
3628The abstraction currently depends on structures being statically allocated
3629by the drivers and callers, as the system does not yet provide a means of
3630dynamically allocating memory. This may also have the affect of limiting the
3631amount of open resources per driver.
3632
3633--------------
3634
Chris Kay33bfc5e2023-02-14 11:30:04 +00003635*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003636
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003637.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
Dan Handley610e7e12018-03-01 18:44:00 +00003638.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003639.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html
Paul Beesley2437ddc2019-02-08 16:43:05 +00003640.. _FreeBSD: https://www.freebsd.org
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003641.. _SCC: http://www.simple-cc.org/
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +01003642.. _DRTM: https://developer.arm.com/documentation/den0113/a