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Paul Beesleyfc9ee362019-03-07 15:47:15 +00001Porting Guide
2=============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Douglas Raillardd7c21b72017-06-28 15:23:03 +01004Introduction
5------------
6
Dan Handley610e7e12018-03-01 18:44:00 +00007Porting Trusted Firmware-A (TF-A) to a new platform involves making some
Douglas Raillardd7c21b72017-06-28 15:23:03 +01008mandatory and optional modifications for both the cold and warm boot paths.
9Modifications consist of:
10
11- Implementing a platform-specific function or variable,
12- Setting up the execution context in a certain way, or
13- Defining certain constants (for example #defines).
14
15The platform-specific functions and variables are declared in
Paul Beesleyf8640672019-04-12 14:19:42 +010016``include/plat/common/platform.h``. The firmware provides a default
17implementation of variables and functions to fulfill the optional requirements.
18These implementations are all weakly defined; they are provided to ease the
19porting effort. Each platform port can override them with its own implementation
20if the default implementation is inadequate.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
Douglas Raillardd7c21b72017-06-28 15:23:03 +010022Some modifications are common to all Boot Loader (BL) stages. Section 2
23discusses these in detail. The subsequent sections discuss the remaining
24modifications for each BL stage in detail.
25
Paul Beesleyf8640672019-04-12 14:19:42 +010026Please refer to the :ref:`Platform Compatibility Policy` for the policy
27regarding compatibility and deprecation of these porting interfaces.
Soby Mathew02bdbb92018-09-26 11:17:23 +010028
Antonio Nino Diaz645feb42019-02-13 14:07:38 +000029Only Arm development platforms (such as FVP and Juno) may use the
30functions/definitions in ``include/plat/arm/common/`` and the corresponding
31source files in ``plat/arm/common/``. This is done so that there are no
32dependencies between platforms maintained by different people/companies. If you
33want to use any of the functionality present in ``plat/arm`` files, please
34create a pull request that moves the code to ``plat/common`` so that it can be
35discussed.
36
Douglas Raillardd7c21b72017-06-28 15:23:03 +010037Common modifications
38--------------------
39
40This section covers the modifications that should be made by the platform for
41each BL stage to correctly port the firmware stack. They are categorized as
42either mandatory or optional.
43
44Common mandatory modifications
45------------------------------
46
47A platform port must enable the Memory Management Unit (MMU) as well as the
48instruction and data caches for each BL stage. Setting up the translation
49tables is the responsibility of the platform port because memory maps differ
50across platforms. A memory translation library (see ``lib/xlat_tables/``) is
Sandrine Bailleux1861b7a2017-07-20 16:11:01 +010051provided to help in this setup.
52
53Note that although this library supports non-identity mappings, this is intended
54only for re-mapping peripheral physical addresses and allows platforms with high
55I/O addresses to reduce their virtual address space. All other addresses
56corresponding to code and data must currently use an identity mapping.
57
Dan Handley610e7e12018-03-01 18:44:00 +000058Also, the only translation granule size supported in TF-A is 4KB, as various
59parts of the code assume that is the case. It is not possible to switch to
6016 KB or 64 KB granule sizes at the moment.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010061
Dan Handley610e7e12018-03-01 18:44:00 +000062In Arm standard platforms, each BL stage configures the MMU in the
Douglas Raillardd7c21b72017-06-28 15:23:03 +010063platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses
64an identity mapping for all addresses.
65
66If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a
67block of identity mapped secure memory with Device-nGnRE attributes aligned to
68page boundary (4K) for each BL stage. All sections which allocate coherent
69memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a
70section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its
71possible for the firmware to place variables in it using the following C code
72directive:
73
74::
75
76 __section("bakery_lock")
77
78Or alternatively the following assembler code directive:
79
80::
81
82 .section bakery_lock
83
84The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are
85used to allocate any data structures that are accessed both when a CPU is
86executing with its MMU and caches enabled, and when it's running with its MMU
87and caches disabled. Examples are given below.
88
89The following variables, functions and constants must be defined by the platform
90for the firmware to work correctly.
91
Javier Almansa Sobrino37bf69c2022-04-07 18:26:49 +010092.. _platform_def_mandatory:
93
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +010094File : platform_def.h [mandatory]
95~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +010096
97Each platform must ensure that a header file of this name is in the system
Antonio Nino Diaz50a4d1a2019-02-01 12:22:22 +000098include path with the following constants defined. This will require updating
99the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100100
Paul Beesleyf8640672019-04-12 14:19:42 +0100101Platform ports may optionally use the file ``include/plat/common/common_def.h``,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100102which provides typical values for some of the constants below. These values are
103likely to be suitable for all platform ports.
104
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100105- **#define : PLATFORM_LINKER_FORMAT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100106
107 Defines the linker format used by the platform, for example
108 ``elf64-littleaarch64``.
109
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100110- **#define : PLATFORM_LINKER_ARCH**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100111
112 Defines the processor architecture for the linker by the platform, for
113 example ``aarch64``.
114
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100115- **#define : PLATFORM_STACK_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100116
117 Defines the normal stack memory available to each CPU. This constant is used
Paul Beesleyf8640672019-04-12 14:19:42 +0100118 by ``plat/common/aarch64/platform_mp_stack.S`` and
119 ``plat/common/aarch64/platform_up_stack.S``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100120
David Horstmann051fd6d2020-11-12 15:19:04 +0000121- **#define : CACHE_WRITEBACK_GRANULE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100122
Max Yufa0b4e82022-09-08 23:21:21 +0000123 Defines the size in bytes of the largest cache line across all the cache
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100124 levels in the platform.
125
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100126- **#define : FIRMWARE_WELCOME_STR**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100127
128 Defines the character string printed by BL1 upon entry into the ``bl1_main()``
129 function.
130
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100131- **#define : PLATFORM_CORE_COUNT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100132
133 Defines the total number of CPUs implemented by the platform across all
134 clusters in the system.
135
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100136- **#define : PLAT_NUM_PWR_DOMAINS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100137
138 Defines the total number of nodes in the power domain topology
139 tree at all the power domain levels used by the platform.
140 This macro is used by the PSCI implementation to allocate
141 data structures to represent power domain topology.
142
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100143- **#define : PLAT_MAX_PWR_LVL**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100144
145 Defines the maximum power domain level that the power management operations
146 should apply to. More often, but not always, the power domain level
147 corresponds to affinity level. This macro allows the PSCI implementation
148 to know the highest power domain level that it should consider for power
149 management operations in the system that the platform implements. For
150 example, the Base AEM FVP implements two clusters with a configurable
151 number of CPUs and it reports the maximum power domain level as 1.
152
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100153- **#define : PLAT_MAX_OFF_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100154
155 Defines the local power state corresponding to the deepest power down
156 possible at every power domain level in the platform. The local power
157 states for each level may be sparsely allocated between 0 and this value
158 with 0 being reserved for the RUN state. The PSCI implementation uses this
159 value to initialize the local power states of the power domain nodes and
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100160 to specify the requested power state for a PSCI_CPU_OFF call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100161
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100162- **#define : PLAT_MAX_RET_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100163
164 Defines the local power state corresponding to the deepest retention state
165 possible at every power domain level in the platform. This macro should be
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100166 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100167 PSCI implementation to distinguish between retention and power down local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100168 power states within PSCI_CPU_SUSPEND call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100169
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100170- **#define : PLAT_MAX_PWR_LVL_STATES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100171
172 Defines the maximum number of local power states per power domain level
173 that the platform supports. The default value of this macro is 2 since
174 most platforms just support a maximum of two local power states at each
175 power domain level (power-down and retention). If the platform needs to
176 account for more local power states, then it must redefine this macro.
177
178 Currently, this macro is used by the Generic PSCI implementation to size
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100179 the array used for PSCI_STAT_COUNT/RESIDENCY accounting.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100180
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100181- **#define : BL1_RO_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100182
183 Defines the base address in secure ROM where BL1 originally lives. Must be
184 aligned on a page-size boundary.
185
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100186- **#define : BL1_RO_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100187
188 Defines the maximum address in secure ROM that BL1's actual content (i.e.
189 excluding any data section allocated at runtime) can occupy.
190
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100191- **#define : BL1_RW_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100192
193 Defines the base address in secure RAM where BL1's read-write data will live
194 at runtime. Must be aligned on a page-size boundary.
195
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100196- **#define : BL1_RW_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100197
198 Defines the maximum address in secure RAM that BL1's read-write data can
199 occupy at runtime.
200
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100201- **#define : BL2_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100202
203 Defines the base address in secure RAM where BL1 loads the BL2 binary image.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000204 Must be aligned on a page-size boundary. This constant is not applicable
205 when BL2_IN_XIP_MEM is set to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100206
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100207- **#define : BL2_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100208
209 Defines the maximum address in secure RAM that the BL2 image can occupy.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000210 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'.
211
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100212- **#define : BL2_RO_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000213
214 Defines the base address in secure XIP memory where BL2 RO section originally
215 lives. Must be aligned on a page-size boundary. This constant is only needed
216 when BL2_IN_XIP_MEM is set to '1'.
217
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100218- **#define : BL2_RO_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000219
220 Defines the maximum address in secure XIP memory that BL2's actual content
221 (i.e. excluding any data section allocated at runtime) can occupy. This
222 constant is only needed when BL2_IN_XIP_MEM is set to '1'.
223
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100224- **#define : BL2_RW_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000225
226 Defines the base address in secure RAM where BL2's read-write data will live
227 at runtime. Must be aligned on a page-size boundary. This constant is only
228 needed when BL2_IN_XIP_MEM is set to '1'.
229
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100230- **#define : BL2_RW_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000231
232 Defines the maximum address in secure RAM that BL2's read-write data can
233 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set
234 to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100235
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100236- **#define : BL31_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100237
238 Defines the base address in secure RAM where BL2 loads the BL31 binary
239 image. Must be aligned on a page-size boundary.
240
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100241- **#define : BL31_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100242
243 Defines the maximum address in secure RAM that the BL31 image can occupy.
244
Tamas Ban1d3354e2022-09-16 14:09:30 +0200245- **#define : PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE**
246
247 Defines the maximum message size between AP and RSS. Need to define if
248 platform supports RSS.
249
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100250For every image, the platform must define individual identifiers that will be
251used by BL1 or BL2 to load the corresponding image into memory from non-volatile
252storage. For the sake of performance, integer numbers will be used as
253identifiers. The platform will use those identifiers to return the relevant
254information about the image to be loaded (file handler, load address,
255authentication information, etc.). The following image identifiers are
256mandatory:
257
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100258- **#define : BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100259
260 BL2 image identifier, used by BL1 to load BL2.
261
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100262- **#define : BL31_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100263
264 BL31 image identifier, used by BL2 to load BL31.
265
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100266- **#define : BL33_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100267
268 BL33 image identifier, used by BL2 to load BL33.
269
270If Trusted Board Boot is enabled, the following certificate identifiers must
271also be defined:
272
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100273- **#define : TRUSTED_BOOT_FW_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100274
275 BL2 content certificate identifier, used by BL1 to load the BL2 content
276 certificate.
277
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100278- **#define : TRUSTED_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100279
280 Trusted key certificate identifier, used by BL2 to load the trusted key
281 certificate.
282
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100283- **#define : SOC_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100284
285 BL31 key certificate identifier, used by BL2 to load the BL31 key
286 certificate.
287
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100288- **#define : SOC_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100289
290 BL31 content certificate identifier, used by BL2 to load the BL31 content
291 certificate.
292
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100293- **#define : NON_TRUSTED_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100294
295 BL33 key certificate identifier, used by BL2 to load the BL33 key
296 certificate.
297
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100298- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100299
300 BL33 content certificate identifier, used by BL2 to load the BL33 content
301 certificate.
302
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100303- **#define : FWU_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100304
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100305 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100306 FWU content certificate.
307
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100308- **#define : PLAT_CRYPTOCELL_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100309
Dan Handley610e7e12018-03-01 18:44:00 +0000310 This defines the base address of Arm® TrustZone® CryptoCell and must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100311 defined if CryptoCell crypto driver is used for Trusted Board Boot. For
Dan Handley610e7e12018-03-01 18:44:00 +0000312 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100313 set.
314
315If the AP Firmware Updater Configuration image, BL2U is used, the following
316must also be defined:
317
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100318- **#define : BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100319
320 Defines the base address in secure memory where BL1 copies the BL2U binary
321 image. Must be aligned on a page-size boundary.
322
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100323- **#define : BL2U_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100324
325 Defines the maximum address in secure memory that the BL2U image can occupy.
326
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100327- **#define : BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100328
329 BL2U image identifier, used by BL1 to fetch an image descriptor
330 corresponding to BL2U.
331
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100332If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100333must also be defined:
334
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100335- **#define : SCP_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100336
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100337 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor
338 corresponding to SCP_BL2U.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000339
340 .. note::
341 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100342
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100343If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100344also be defined:
345
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100346- **#define : NS_BL1U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100347
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100348 Defines the base address in non-secure ROM where NS_BL1U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100349 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000350
351 .. note::
352 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100353
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100354- **#define : NS_BL1U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100355
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100356 NS_BL1U image identifier, used by BL1 to fetch an image descriptor
357 corresponding to NS_BL1U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100358
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100359If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100360be defined:
361
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100362- **#define : NS_BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100363
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100364 Defines the base address in non-secure memory where NS_BL2U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100365 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000366
367 .. note::
368 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100369
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100370- **#define : NS_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100371
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100372 NS_BL2U image identifier, used by BL1 to fetch an image descriptor
373 corresponding to NS_BL2U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100374
375For the the Firmware update capability of TRUSTED BOARD BOOT, the following
376macros may also be defined:
377
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100378- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100379
380 Total number of images that can be loaded simultaneously. If the platform
381 doesn't specify any value, it defaults to 10.
382
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100383If a SCP_BL2 image is supported by the platform, the following constants must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100384also be defined:
385
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100386- **#define : SCP_BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100387
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100388 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000389 from platform storage before being transferred to the SCP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100390
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100391- **#define : SCP_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100392
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100393 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100394 certificate (mandatory when Trusted Board Boot is enabled).
395
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100396- **#define : SCP_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100397
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100398 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100399 content certificate (mandatory when Trusted Board Boot is enabled).
400
401If a BL32 image is supported by the platform, the following constants must
402also be defined:
403
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100404- **#define : BL32_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100405
406 BL32 image identifier, used by BL2 to load BL32.
407
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100408- **#define : TRUSTED_OS_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100409
410 BL32 key certificate identifier, used by BL2 to load the BL32 key
411 certificate (mandatory when Trusted Board Boot is enabled).
412
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100413- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100414
415 BL32 content certificate identifier, used by BL2 to load the BL32 content
416 certificate (mandatory when Trusted Board Boot is enabled).
417
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100418- **#define : BL32_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100419
420 Defines the base address in secure memory where BL2 loads the BL32 binary
421 image. Must be aligned on a page-size boundary.
422
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100423- **#define : BL32_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100424
425 Defines the maximum address that the BL32 image can occupy.
426
427If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the
428platform, the following constants must also be defined:
429
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100430- **#define : TSP_SEC_MEM_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100431
432 Defines the base address of the secure memory used by the TSP image on the
433 platform. This must be at the same address or below ``BL32_BASE``.
434
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100435- **#define : TSP_SEC_MEM_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100436
437 Defines the size of the secure memory used by the BL32 image on the
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000438 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully
439 accommodate the memory required by the BL32 image, defined by ``BL32_BASE``
440 and ``BL32_LIMIT``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100441
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100442- **#define : TSP_IRQ_SEC_PHY_TIMER**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100443
444 Defines the ID of the secure physical generic timer interrupt used by the
445 TSP's interrupt handling code.
446
447If the platform port uses the translation table library code, the following
448constants must also be defined:
449
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100450- **#define : PLAT_XLAT_TABLES_DYNAMIC**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100451
452 Optional flag that can be set per-image to enable the dynamic allocation of
453 regions even when the MMU is enabled. If not defined, only static
454 functionality will be available, if defined and set to 1 it will also
455 include the dynamic functionality.
456
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100457- **#define : MAX_XLAT_TABLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100458
459 Defines the maximum number of translation tables that are allocated by the
460 translation table library code. To minimize the amount of runtime memory
461 used, choose the smallest value needed to map the required virtual addresses
462 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL
463 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions
464 as well.
465
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100466- **#define : MAX_MMAP_REGIONS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100467
468 Defines the maximum number of regions that are allocated by the translation
469 table library code. A region consists of physical base address, virtual base
470 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
471 defined in the ``mmap_region_t`` structure. The platform defines the regions
472 that should be mapped. Then, the translation table library will create the
473 corresponding tables and descriptors at runtime. To minimize the amount of
474 runtime memory used, choose the smallest value needed to register the
475 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is
476 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate
477 the dynamic regions as well.
478
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100479- **#define : PLAT_VIRT_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100480
481 Defines the total size of the virtual address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000482 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100483
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100484- **#define : PLAT_PHY_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100485
486 Defines the total size of the physical address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000487 for a 32 bit physical address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100488
489If the platform port uses the IO storage framework, the following constants
490must also be defined:
491
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100492- **#define : MAX_IO_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100493
494 Defines the maximum number of registered IO devices. Attempting to register
495 more devices than this value using ``io_register_device()`` will fail with
496 -ENOMEM.
497
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100498- **#define : MAX_IO_HANDLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100499
500 Defines the maximum number of open IO handles. Attempting to open more IO
501 entities than this value using ``io_open()`` will fail with -ENOMEM.
502
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100503- **#define : MAX_IO_BLOCK_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100504
505 Defines the maximum number of registered IO block devices. Attempting to
506 register more devices this value using ``io_dev_open()`` will fail
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100507 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100508 With this macro, multiple block devices could be supported at the same
509 time.
510
511If the platform needs to allocate data within the per-cpu data framework in
512BL31, it should define the following macro. Currently this is only required if
513the platform decides not to use the coherent memory section by undefining the
514``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
515required memory within the the per-cpu data to minimize wastage.
516
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100517- **#define : PLAT_PCPU_DATA_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100518
519 Defines the memory (in bytes) to be reserved within the per-cpu data
520 structure for use by the platform layer.
521
522The following constants are optional. They should be defined when the platform
Dan Handley610e7e12018-03-01 18:44:00 +0000523memory layout implies some image overlaying like in Arm standard platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100524
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100525- **#define : BL31_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100526
527 Defines the maximum address in secure RAM that the BL31's progbits sections
528 can occupy.
529
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100530- **#define : TSP_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100531
532 Defines the maximum address that the TSP's progbits sections can occupy.
533
534If the platform port uses the PL061 GPIO driver, the following constant may
535optionally be defined:
536
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100537- **PLAT_PL061_MAX_GPIOS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100538 Maximum number of GPIOs required by the platform. This allows control how
539 much memory is allocated for PL061 GPIO controllers. The default value is
540
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100541 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100542
543If the platform port uses the partition driver, the following constant may
544optionally be defined:
545
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100546- **PLAT_PARTITION_MAX_ENTRIES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100547 Maximum number of partition entries required by the platform. This allows
548 control how much memory is allocated for partition entries. The default
549 value is 128.
Paul Beesleyf8640672019-04-12 14:19:42 +0100550 For example, define the build flag in ``platform.mk``:
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100551 PLAT_PARTITION_MAX_ENTRIES := 12
552 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100553
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800554- **PLAT_PARTITION_BLOCK_SIZE**
555 The size of partition block. It could be either 512 bytes or 4096 bytes.
556 The default value is 512.
Paul Beesleyf2ec7142019-10-04 16:17:46 +0000557 For example, define the build flag in ``platform.mk``:
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800558 PLAT_PARTITION_BLOCK_SIZE := 4096
559 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE))
560
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100561The following constant is optional. It should be defined to override the default
562behaviour of the ``assert()`` function (for example, to save memory).
563
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100564- **PLAT_LOG_LEVEL_ASSERT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100565 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``,
566 ``assert()`` prints the name of the file, the line number and the asserted
567 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file
568 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it
569 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't
570 defined, it defaults to ``LOG_LEVEL``.
571
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +0100572If the platform port uses the DRTM feature, the following constants must be
573defined:
574
575- **#define : PLAT_DRTM_EVENT_LOG_MAX_SIZE**
576
577 Maximum Event Log size used by the platform. Platform can decide the maximum
578 size of the Event Log buffer, depending upon the highest hash algorithm
579 chosen and the number of components selected to measure during the DRTM
580 execution flow.
581
582- **#define : PLAT_DRTM_MMAP_ENTRIES**
583
584 Number of the MMAP entries used by the DRTM implementation to calculate the
585 size of address map region of the platform.
586
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100587File : plat_macros.S [mandatory]
588~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100589
590Each platform must ensure a file of this name is in the system include path with
Dan Handley610e7e12018-03-01 18:44:00 +0000591the following macro defined. In the Arm development platforms, this file is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100592found in ``plat/arm/board/<plat_name>/include/plat_macros.S``.
593
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100594- **Macro : plat_crash_print_regs**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100595
596 This macro allows the crash reporting routine to print relevant platform
597 registers in case of an unhandled exception in BL31. This aids in debugging
598 and this macro can be defined to be empty in case register reporting is not
599 desired.
600
601 For instance, GIC or interconnect registers may be helpful for
602 troubleshooting.
603
604Handling Reset
605--------------
606
607BL1 by default implements the reset vector where execution starts from a cold
608or warm boot. BL31 can be optionally set as a reset vector using the
609``RESET_TO_BL31`` make variable.
610
611For each CPU, the reset vector code is responsible for the following tasks:
612
613#. Distinguishing between a cold boot and a warm boot.
614
615#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
616 the CPU is placed in a platform-specific state until the primary CPU
617 performs the necessary steps to remove it from this state.
618
619#. In the case of a warm boot, ensuring that the CPU jumps to a platform-
620 specific address in the BL31 image in the same processor mode as it was
621 when released from reset.
622
623The following functions need to be implemented by the platform port to enable
624reset vector code to perform the above tasks.
625
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100626Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0]
627~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100628
629::
630
631 Argument : void
632 Return : uintptr_t
633
634This function is called with the MMU and caches disabled
635(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for
636distinguishing between a warm and cold reset for the current CPU using
637platform-specific means. If it's a warm reset, then it returns the warm
638reset entrypoint point provided to ``plat_setup_psci_ops()`` during
639BL31 initialization. If it's a cold reset then this function must return zero.
640
641This function does not follow the Procedure Call Standard used by the
Dan Handley610e7e12018-03-01 18:44:00 +0000642Application Binary Interface for the Arm 64-bit architecture. The caller should
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100643not assume that callee saved registers are preserved across a call to this
644function.
645
646This function fulfills requirement 1 and 3 listed above.
647
648Note that for platforms that support programming the reset address, it is
649expected that a CPU will start executing code directly at the right address,
650both on a cold and warm reset. In this case, there is no need to identify the
651type of reset nor to query the warm reset entrypoint. Therefore, implementing
652this function is not required on such platforms.
653
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100654Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
655~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100656
657::
658
659 Argument : void
660
661This function is called with the MMU and data caches disabled. It is responsible
662for placing the executing secondary CPU in a platform-specific state until the
663primary CPU performs the necessary actions to bring it out of that state and
664allow entry into the OS. This function must not return.
665
Dan Handley610e7e12018-03-01 18:44:00 +0000666In the Arm FVP port, when using the normal boot flow, each secondary CPU powers
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100667itself off. The primary CPU is responsible for powering up the secondary CPUs
668when normal world software requires them. When booting an EL3 payload instead,
669they stay powered on and are put in a holding pen until their mailbox gets
670populated.
671
672This function fulfills requirement 2 above.
673
674Note that for platforms that can't release secondary CPUs out of reset, only the
675primary CPU will execute the cold boot code. Therefore, implementing this
676function is not required on such platforms.
677
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100678Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
679~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100680
681::
682
683 Argument : void
684 Return : unsigned int
685
686This function identifies whether the current CPU is the primary CPU or a
687secondary CPU. A return value of zero indicates that the CPU is not the
688primary CPU, while a non-zero return value indicates that the CPU is the
689primary CPU.
690
691Note that for platforms that can't release secondary CPUs out of reset, only the
692primary CPU will execute the cold boot code. Therefore, there is no need to
693distinguish between primary and secondary CPUs and implementing this function is
694not required.
695
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100696Function : platform_mem_init() [mandatory]
697~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100698
699::
700
701 Argument : void
702 Return : void
703
704This function is called before any access to data is made by the firmware, in
705order to carry out any essential memory initialization.
706
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100707Function: plat_get_rotpk_info()
708~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100709
710::
711
712 Argument : void *, void **, unsigned int *, unsigned int *
713 Return : int
714
715This function is mandatory when Trusted Board Boot is enabled. It returns a
716pointer to the ROTPK stored in the platform (or a hash of it) and its length.
717The ROTPK must be encoded in DER format according to the following ASN.1
718structure:
719
720::
721
722 AlgorithmIdentifier ::= SEQUENCE {
723 algorithm OBJECT IDENTIFIER,
724 parameters ANY DEFINED BY algorithm OPTIONAL
725 }
726
727 SubjectPublicKeyInfo ::= SEQUENCE {
728 algorithm AlgorithmIdentifier,
729 subjectPublicKey BIT STRING
730 }
731
732In case the function returns a hash of the key:
733
734::
735
736 DigestInfo ::= SEQUENCE {
737 digestAlgorithm AlgorithmIdentifier,
738 digest OCTET STRING
739 }
740
741The function returns 0 on success. Any other value is treated as error by the
742Trusted Board Boot. The function also reports extra information related
743to the ROTPK in the flags parameter:
744
745::
746
747 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a
748 hash.
749 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK
750 verification while the platform ROTPK is not deployed.
751 When this flag is set, the function does not need to
752 return a platform ROTPK, and the authentication
753 framework uses the ROTPK in the certificate without
754 verifying it against the platform value. This flag
755 must not be used in a deployed production environment.
756
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100757Function: plat_get_nv_ctr()
758~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100759
760::
761
762 Argument : void *, unsigned int *
763 Return : int
764
765This function is mandatory when Trusted Board Boot is enabled. It returns the
766non-volatile counter value stored in the platform in the second argument. The
767cookie in the first argument may be used to select the counter in case the
768platform provides more than one (for example, on platforms that use the default
769TBBR CoT, the cookie will correspond to the OID values defined in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100770TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100771
772The function returns 0 on success. Any other value means the counter value could
773not be retrieved from the platform.
774
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100775Function: plat_set_nv_ctr()
776~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100777
778::
779
780 Argument : void *, unsigned int
781 Return : int
782
783This function is mandatory when Trusted Board Boot is enabled. It sets a new
784counter value in the platform. The cookie in the first argument may be used to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100785select the counter (as explained in plat_get_nv_ctr()). The second argument is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100786the updated counter value to be written to the NV counter.
787
788The function returns 0 on success. Any other value means the counter value could
789not be updated.
790
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100791Function: plat_set_nv_ctr2()
792~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100793
794::
795
796 Argument : void *, const auth_img_desc_t *, unsigned int
797 Return : int
798
799This function is optional when Trusted Board Boot is enabled. If this
800interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The
801first argument passed is a cookie and is typically used to
802differentiate between a Non Trusted NV Counter and a Trusted NV
803Counter. The second argument is a pointer to an authentication image
804descriptor and may be used to decide if the counter is allowed to be
805updated or not. The third argument is the updated counter value to
806be written to the NV counter.
807
808The function returns 0 on success. Any other value means the counter value
809either could not be updated or the authentication image descriptor indicates
810that it is not allowed to be updated.
811
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +0100812Dynamic Root of Trust for Measurement support (in BL31)
813-------------------------------------------------------
814
815The functions mentioned in this section are mandatory, when platform enables
816DRTM_SUPPORT build flag.
817
818Function : plat_get_addr_mmap()
819~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
820
821::
822
823 Argument : void
824 Return : const mmap_region_t *
825
826This function is used to return the address of the platform *address-map* table,
827which describes the regions of normal memory, memory mapped I/O
828and non-volatile memory.
829
830Function : plat_has_non_host_platforms()
831~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
832
833::
834
835 Argument : void
836 Return : bool
837
838This function returns *true* if the platform has any trusted devices capable of
839DMA, otherwise returns *false*.
840
841Function : plat_has_unmanaged_dma_peripherals()
842~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
843
844::
845
846 Argument : void
847 Return : bool
848
849This function returns *true* if platform uses peripherals whose DMA is not
850managed by an SMMU, otherwise returns *false*.
851
852Note -
853If the platform has peripherals that are not managed by the SMMU, then the
854platform should investigate such peripherals to determine whether they can
855be trusted, and such peripherals should be moved under "Non-host platforms"
856if they can be trusted.
857
858Function : plat_get_total_num_smmus()
859~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
860
861::
862
863 Argument : void
864 Return : unsigned int
865
866This function returns the total number of SMMUs in the platform.
867
868Function : plat_enumerate_smmus()
869~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
870::
871
872
873 Argument : void
874 Return : const uintptr_t *, size_t
875
876This function returns an array of SMMU addresses and the actual number of SMMUs
877reported by the platform.
878
879Function : plat_drtm_get_dma_prot_features()
880~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
881
882::
883
884 Argument : void
885 Return : const plat_drtm_dma_prot_features_t*
886
887This function returns the address of plat_drtm_dma_prot_features_t structure
888containing the maximum number of protected regions and bitmap with the types
889of DMA protection supported by the platform.
890For more details see section 3.3 Table 6 of `DRTM`_ specification.
891
892Function : plat_drtm_dma_prot_get_max_table_bytes()
893~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
894
895::
896
897 Argument : void
898 Return : uint64_t
899
900This function returns the maximum size of DMA protected regions table in
901bytes.
902
903Function : plat_drtm_get_tpm_features()
904~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
905
906::
907
908 Argument : void
909 Return : const plat_drtm_tpm_features_t*
910
911This function returns the address of *plat_drtm_tpm_features_t* structure
912containing PCR usage schema, TPM-based hash, and firmware hash algorithm
913supported by the platform.
914
915Function : plat_drtm_get_min_size_normal_world_dce()
916~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
917
918::
919
920 Argument : void
921 Return : uint64_t
922
923This function returns the size normal-world DCE of the platform.
924
925Function : plat_drtm_get_imp_def_dlme_region_size()
926~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
927
928::
929
930 Argument : void
931 Return : uint64_t
932
933This function returns the size of implementation defined DLME region
934of the platform.
935
936Function : plat_drtm_get_tcb_hash_table_size()
937~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
938
939::
940
941 Argument : void
942 Return : uint64_t
943
944This function returns the size of TCB hash table of the platform.
945
946Function : plat_drtm_get_tcb_hash_features()
947~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
948
949::
950
951 Argument : void
952 Return : uint64_t
953
954This function returns the Maximum number of TCB hashes recorded by the
955platform.
956For more details see section 3.3 Table 6 of `DRTM`_ specification.
957
958Function : plat_drtm_validate_ns_region()
959~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
960
961::
962
963 Argument : uintptr_t, uintptr_t
964 Return : int
965
966This function validates that given region is within the Non-Secure region
967of DRAM. This function takes a region start address and size an input
968arguments, and returns 0 on success and -1 on failure.
969
970Function : plat_set_drtm_error()
971~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
972
973::
974
975 Argument : uint64_t
976 Return : int
977
978This function writes a 64 bit error code received as input into
979non-volatile storage and returns 0 on success and -1 on failure.
980
981Function : plat_get_drtm_error()
982~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
983
984::
985
986 Argument : uint64_t*
987 Return : int
988
989This function reads a 64 bit error code from the non-volatile storage
990into the received address, and returns 0 on success and -1 on failure.
991
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100992Common mandatory function modifications
993---------------------------------------
994
995The following functions are mandatory functions which need to be implemented
996by the platform port.
997
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100998Function : plat_my_core_pos()
999~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001000
1001::
1002
1003 Argument : void
1004 Return : unsigned int
1005
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001006This function returns the index of the calling CPU which is used as a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001007CPU-specific linear index into blocks of memory (for example while allocating
1008per-CPU stacks). This function will be invoked very early in the
1009initialization sequence which mandates that this function should be
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001010implemented in assembly and should not rely on the availability of a C
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001011runtime environment. This function can clobber x0 - x8 and must preserve
1012x9 - x29.
1013
1014This function plays a crucial role in the power domain topology framework in
Paul Beesleyf8640672019-04-12 14:19:42 +01001015PSCI and details of this can be found in
1016:ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001017
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001018Function : plat_core_pos_by_mpidr()
1019~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001020
1021::
1022
1023 Argument : u_register_t
1024 Return : int
1025
1026This function validates the ``MPIDR`` of a CPU and converts it to an index,
1027which can be used as a CPU-specific linear index into blocks of memory. In
1028case the ``MPIDR`` is invalid, this function returns -1. This function will only
1029be invoked by BL31 after the power domain topology is initialized and can
Dan Handley610e7e12018-03-01 18:44:00 +00001030utilize the C runtime environment. For further details about how TF-A
1031represents the power domain topology and how this relates to the linear CPU
Paul Beesleyf8640672019-04-12 14:19:42 +01001032index, please refer :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001033
Ambroise Vincentd207f562019-04-10 12:50:27 +01001034Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1]
1035~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1036
1037::
1038
1039 Arguments : void **heap_addr, size_t *heap_size
1040 Return : int
1041
1042This function is invoked during Mbed TLS library initialisation to get a heap,
1043by means of a starting address and a size. This heap will then be used
1044internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS
1045must be able to provide a heap to it.
1046
1047A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in
1048which a heap is statically reserved during compile time inside every image
1049(i.e. every BL stage) that utilises Mbed TLS. In this default implementation,
1050the function simply returns the address and size of this "pre-allocated" heap.
1051For a platform to use this default implementation, only a call to the helper
1052from inside plat_get_mbedtls_heap() body is enough and nothing else is needed.
1053
1054However, by writting their own implementation, platforms have the potential to
1055optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is
1056shared between BL1 and BL2 stages and, thus, the necessary space is not reserved
1057twice.
1058
1059On success the function should return 0 and a negative error code otherwise.
1060
Sumit Gargc0c369c2019-11-15 18:47:53 +05301061Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1]
1062~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1063
1064::
1065
1066 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key,
1067 size_t *key_len, unsigned int *flags, const uint8_t *img_id,
1068 size_t img_id_len
1069 Return : int
1070
1071This function provides a symmetric key (either SSK or BSSK depending on
1072fw_enc_status) which is invoked during runtime decryption of encrypted
1073firmware images. `plat/common/plat_bl_common.c` provides a dummy weak
1074implementation for testing purposes which must be overridden by the platform
1075trying to implement a real world firmware encryption use-case.
1076
1077It also allows the platform to pass symmetric key identifier rather than
1078actual symmetric key which is useful in cases where the crypto backend provides
1079secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER``
1080flag must be set in ``flags``.
1081
1082In addition to above a platform may also choose to provide an image specific
1083symmetric key/identifier using img_id.
1084
1085On success the function should return 0 and a negative error code otherwise.
1086
Manish Pandey34a305e2021-10-21 21:53:49 +01001087Note that this API depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +05301088
Manish V Badarkheda87af12021-06-20 21:14:46 +01001089Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1]
1090~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1091
1092::
1093
Sughosh Ganuf40154f2021-11-17 17:08:10 +05301094 Argument : const struct fwu_metadata *metadata
Manish V Badarkheda87af12021-06-20 21:14:46 +01001095 Return : void
1096
1097This function is mandatory when PSA_FWU_SUPPORT is enabled.
1098It provides a means to retrieve image specification (offset in
1099non-volatile storage and length) of active/updated images using the passed
1100FWU metadata, and update I/O policies of active/updated images using retrieved
1101image specification information.
1102Further I/O layer operations such as I/O open, I/O read, etc. on these
1103images rely on this function call.
1104
1105In Arm platforms, this function is used to set an I/O policy of the FIP image,
1106container of all active/updated secure and non-secure images.
1107
1108Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1]
1109~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1110
1111::
1112
1113 Argument : unsigned int image_id, uintptr_t *dev_handle,
1114 uintptr_t *image_spec
1115 Return : int
1116
1117This function is mandatory when PSA_FWU_SUPPORT is enabled. It is
1118responsible for setting up the platform I/O policy of the requested metadata
1119image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will
1120be used to load this image from the platform's non-volatile storage.
1121
1122FWU metadata can not be always stored as a raw image in non-volatile storage
1123to define its image specification (offset in non-volatile storage and length)
1124statically in I/O policy.
1125For example, the FWU metadata image is stored as a partition inside the GUID
1126partition table image. Its specification is defined in the partition table
1127that needs to be parsed dynamically.
1128This function provides a means to retrieve such dynamic information to set
1129the I/O policy of the FWU metadata image.
1130Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata
1131image relies on this function call.
1132
1133It returns '0' on success, otherwise a negative error value on error.
1134Alongside, returns device handle and image specification from the I/O policy
1135of the requested FWU metadata image.
1136
Sughosh Ganu4e336a62021-12-01 15:53:32 +05301137Function : plat_fwu_get_boot_idx() [when PSA_FWU_SUPPORT == 1]
1138~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1139
1140::
1141
1142 Argument : void
1143 Return : uint32_t
1144
1145This function is mandatory when PSA_FWU_SUPPORT is enabled. It provides the
1146means to retrieve the boot index value from the platform. The boot index is the
1147bank from which the platform has booted the firmware images.
1148
1149By default, the platform will read the metadata structure and try to boot from
1150the active bank. If the platform fails to boot from the active bank due to
1151reasons like an Authentication failure, or on crossing a set number of watchdog
1152resets while booting from the active bank, the platform can then switch to boot
1153from a different bank. This function then returns the bank that the platform
1154should boot its images from.
1155
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001156Common optional modifications
1157-----------------------------
1158
1159The following are helper functions implemented by the firmware that perform
1160common platform-specific tasks. A platform may choose to override these
1161definitions.
1162
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001163Function : plat_set_my_stack()
1164~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001165
1166::
1167
1168 Argument : void
1169 Return : void
1170
1171This function sets the current stack pointer to the normal memory stack that
1172has been allocated for the current CPU. For BL images that only require a
1173stack for the primary CPU, the UP version of the function is used. The size
1174of the stack allocated to each CPU is specified by the platform defined
1175constant ``PLATFORM_STACK_SIZE``.
1176
1177Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +01001178provided in ``plat/common/aarch64/platform_up_stack.S`` and
1179``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001180
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001181Function : plat_get_my_stack()
1182~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001183
1184::
1185
1186 Argument : void
1187 Return : uintptr_t
1188
1189This function returns the base address of the normal memory stack that
1190has been allocated for the current CPU. For BL images that only require a
1191stack for the primary CPU, the UP version of the function is used. The size
1192of the stack allocated to each CPU is specified by the platform defined
1193constant ``PLATFORM_STACK_SIZE``.
1194
1195Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +01001196provided in ``plat/common/aarch64/platform_up_stack.S`` and
1197``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001198
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001199Function : plat_report_exception()
1200~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001201
1202::
1203
1204 Argument : unsigned int
1205 Return : void
1206
1207A platform may need to report various information about its status when an
1208exception is taken, for example the current exception level, the CPU security
1209state (secure/non-secure), the exception type, and so on. This function is
1210called in the following circumstances:
1211
1212- In BL1, whenever an exception is taken.
1213- In BL2, whenever an exception is taken.
1214
1215The default implementation doesn't do anything, to avoid making assumptions
1216about the way the platform displays its status information.
1217
1218For AArch64, this function receives the exception type as its argument.
1219Possible values for exceptions types are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +01001220``include/common/bl_common.h`` header file. Note that these constants are not
Dan Handley610e7e12018-03-01 18:44:00 +00001221related to any architectural exception code; they are just a TF-A convention.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001222
1223For AArch32, this function receives the exception mode as its argument.
1224Possible values for exception modes are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +01001225``include/lib/aarch32/arch.h`` header file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001226
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001227Function : plat_reset_handler()
1228~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001229
1230::
1231
1232 Argument : void
1233 Return : void
1234
1235A platform may need to do additional initialization after reset. This function
Paul Beesleyf2ec7142019-10-04 16:17:46 +00001236allows the platform to do the platform specific initializations. Platform
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001237specific errata workarounds could also be implemented here. The API should
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001238preserve the values of callee saved registers x19 to x29.
1239
1240The default implementation doesn't do anything. If a platform needs to override
Paul Beesleyf8640672019-04-12 14:19:42 +01001241the default implementation, refer to the :ref:`Firmware Design` for general
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001242guidelines.
1243
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001244Function : plat_disable_acp()
1245~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001246
1247::
1248
1249 Argument : void
1250 Return : void
1251
John Tsichritzis6dda9762018-07-23 09:18:04 +01001252This API allows a platform to disable the Accelerator Coherency Port (if
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001253present) during a cluster power down sequence. The default weak implementation
John Tsichritzis6dda9762018-07-23 09:18:04 +01001254doesn't do anything. Since this API is called during the power down sequence,
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001255it has restrictions for stack usage and it can use the registers x0 - x17 as
1256scratch registers. It should preserve the value in x18 register as it is used
1257by the caller to store the return address.
1258
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001259Function : plat_error_handler()
1260~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001261
1262::
1263
1264 Argument : int
1265 Return : void
1266
1267This API is called when the generic code encounters an error situation from
1268which it cannot continue. It allows the platform to perform error reporting or
1269recovery actions (for example, reset the system). This function must not return.
1270
1271The parameter indicates the type of error using standard codes from ``errno.h``.
1272Possible errors reported by the generic code are:
1273
1274- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted
1275 Board Boot is enabled)
1276- ``-ENOENT``: the requested image or certificate could not be found or an IO
1277 error was detected
Dan Handley610e7e12018-03-01 18:44:00 +00001278- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this
1279 error is usually an indication of an incorrect array size
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001280
1281The default implementation simply spins.
1282
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001283Function : plat_panic_handler()
1284~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001285
1286::
1287
1288 Argument : void
1289 Return : void
1290
1291This API is called when the generic code encounters an unexpected error
1292situation from which it cannot recover. This function must not return,
1293and must be implemented in assembly because it may be called before the C
1294environment is initialized.
1295
Paul Beesleyba3ed402019-03-13 16:20:44 +00001296.. note::
1297 The address from where it was called is stored in x30 (Link Register).
1298 The default implementation simply spins.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001299
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +01001300Function : plat_system_reset()
1301~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1302
1303::
1304
1305 Argument : void
1306 Return : void
1307
1308This function is used by the platform to resets the system. It can be used
1309in any specific use-case where system needs to be resetted. For example,
1310in case of DRTM implementation this function reset the system after
1311writing the DRTM error code in the non-volatile storage. This function
1312never returns. Failure in reset results in panic.
1313
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001314Function : plat_get_bl_image_load_info()
1315~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001316
1317::
1318
1319 Argument : void
1320 Return : bl_load_info_t *
1321
1322This function returns pointer to the list of images that the platform has
Soby Mathew97b1bff2018-09-27 16:46:41 +01001323populated to load. This function is invoked in BL2 to load the
1324BL3xx images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001325
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001326Function : plat_get_next_bl_params()
1327~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001328
1329::
1330
1331 Argument : void
1332 Return : bl_params_t *
1333
1334This function returns a pointer to the shared memory that the platform has
Dan Handley610e7e12018-03-01 18:44:00 +00001335kept aside to pass TF-A related information that next BL image needs. This
Soby Mathew97b1bff2018-09-27 16:46:41 +01001336function is invoked in BL2 to pass this information to the next BL
1337image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001338
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001339Function : plat_get_stack_protector_canary()
1340~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001341
1342::
1343
1344 Argument : void
1345 Return : u_register_t
1346
1347This function returns a random value that is used to initialize the canary used
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001348when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001349value will weaken the protection as the attacker could easily write the right
1350value as part of the attack most of the time. Therefore, it should return a
1351true random number.
1352
Paul Beesleyba3ed402019-03-13 16:20:44 +00001353.. warning::
1354 For the protection to be effective, the global data need to be placed at
1355 a lower address than the stack bases. Failure to do so would allow an
1356 attacker to overwrite the canary as part of the stack buffer overflow attack.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001357
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001358Function : plat_flush_next_bl_params()
1359~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001360
1361::
1362
1363 Argument : void
1364 Return : void
1365
1366This function flushes to main memory all the image params that are passed to
Soby Mathew97b1bff2018-09-27 16:46:41 +01001367next image. This function is invoked in BL2 to flush this information
1368to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001369
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001370Function : plat_log_get_prefix()
1371~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewaaf15f52017-09-04 11:49:29 +01001372
1373::
1374
1375 Argument : unsigned int
1376 Return : const char *
1377
1378This function defines the prefix string corresponding to the `log_level` to be
Dan Handley610e7e12018-03-01 18:44:00 +00001379prepended to all the log output from TF-A. The `log_level` (argument) will
1380correspond to one of the standard log levels defined in debug.h. The platform
1381can override the common implementation to define a different prefix string for
John Tsichritzis30f89642018-06-07 16:31:34 +01001382the log output. The implementation should be robust to future changes that
Dan Handley610e7e12018-03-01 18:44:00 +00001383increase the number of log levels.
Soby Mathewaaf15f52017-09-04 11:49:29 +01001384
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001385Function : plat_get_soc_version()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001386~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001387
1388::
1389
1390 Argument : void
1391 Return : int32_t
1392
1393This function returns soc version which mainly consist of below fields
1394
1395::
1396
1397 soc_version[30:24] = JEP-106 continuation code for the SiP
1398 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001399 soc_version[15:0] = Implementation defined SoC ID
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001400
1401Function : plat_get_soc_revision()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001402~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001403
1404::
1405
1406 Argument : void
1407 Return : int32_t
1408
1409This function returns soc revision in below format
1410
1411::
1412
1413 soc_revision[0:30] = SOC revision of specific SOC
1414
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001415Function : plat_is_smccc_feature_available()
1416~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1417
1418::
1419
1420 Argument : u_register_t
1421 Return : int32_t
1422
1423This function returns SMC_ARCH_CALL_SUCCESS if the platform supports
1424the SMCCC function specified in the argument; otherwise returns
1425SMC_ARCH_CALL_NOT_SUPPORTED.
1426
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001427Function : plat_mboot_measure_image()
1428~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1429
1430::
1431
1432 Argument : unsigned int, image_info_t *
Manish V Badarkhe931c6ef2021-10-21 09:06:18 +01001433 Return : int
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001434
1435When the MEASURED_BOOT flag is enabled:
1436
1437- This function measures the given image and records its measurement using
1438 the measured boot backend driver.
1439- On the Arm FVP port, this function measures the given image using its
1440 passed id and information and then records that measurement in the
1441 Event Log buffer.
Manish V Badarkhe931c6ef2021-10-21 09:06:18 +01001442- This function must return 0 on success, a signed integer error code
1443 otherwise.
1444
1445When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1446
1447Function : plat_mboot_measure_critical_data()
1448~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1449
1450::
1451
1452 Argument : unsigned int, const void *, size_t
1453 Return : int
1454
1455When the MEASURED_BOOT flag is enabled:
1456
1457- This function measures the given critical data structure and records its
1458 measurement using the measured boot backend driver.
1459- This function must return 0 on success, a signed integer error code
1460 otherwise.
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001461
1462When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1463
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001464Modifications specific to a Boot Loader stage
1465---------------------------------------------
1466
1467Boot Loader Stage 1 (BL1)
1468-------------------------
1469
1470BL1 implements the reset vector where execution starts from after a cold or
1471warm boot. For each CPU, BL1 is responsible for the following tasks:
1472
1473#. Handling the reset as described in section 2.2
1474
1475#. In the case of a cold boot and the CPU being the primary CPU, ensuring that
1476 only this CPU executes the remaining BL1 code, including loading and passing
1477 control to the BL2 stage.
1478
1479#. Identifying and starting the Firmware Update process (if required).
1480
1481#. Loading the BL2 image from non-volatile storage into secure memory at the
1482 address specified by the platform defined constant ``BL2_BASE``.
1483
1484#. Populating a ``meminfo`` structure with the following information in memory,
1485 accessible by BL2 immediately upon entry.
1486
1487 ::
1488
1489 meminfo.total_base = Base address of secure RAM visible to BL2
1490 meminfo.total_size = Size of secure RAM visible to BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001491
Soby Mathew97b1bff2018-09-27 16:46:41 +01001492 By default, BL1 places this ``meminfo`` structure at the end of secure
1493 memory visible to BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001494
Soby Mathewb1bf0442018-02-16 14:52:52 +00001495 It is possible for the platform to decide where it wants to place the
1496 ``meminfo`` structure for BL2 or restrict the amount of memory visible to
1497 BL2 by overriding the weak default implementation of
1498 ``bl1_plat_handle_post_image_load`` API.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001499
1500The following functions need to be implemented by the platform port to enable
1501BL1 to perform the above tasks.
1502
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001503Function : bl1_early_platform_setup() [mandatory]
1504~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001505
1506::
1507
1508 Argument : void
1509 Return : void
1510
1511This function executes with the MMU and data caches disabled. It is only called
1512by the primary CPU.
1513
Dan Handley610e7e12018-03-01 18:44:00 +00001514On Arm standard platforms, this function:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001515
1516- Enables a secure instance of SP805 to act as the Trusted Watchdog.
1517
1518- Initializes a UART (PL011 console), which enables access to the ``printf``
1519 family of functions in BL1.
1520
1521- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to
1522 the CCI slave interface corresponding to the cluster that includes the
1523 primary CPU.
1524
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001525Function : bl1_plat_arch_setup() [mandatory]
1526~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001527
1528::
1529
1530 Argument : void
1531 Return : void
1532
1533This function performs any platform-specific and architectural setup that the
1534platform requires. Platform-specific setup might include configuration of
1535memory controllers and the interconnect.
1536
Dan Handley610e7e12018-03-01 18:44:00 +00001537In Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001538
1539This function helps fulfill requirement 2 above.
1540
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001541Function : bl1_platform_setup() [mandatory]
1542~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001543
1544::
1545
1546 Argument : void
1547 Return : void
1548
1549This function executes with the MMU and data caches enabled. It is responsible
1550for performing any remaining platform-specific setup that can occur after the
1551MMU and data cache have been enabled.
1552
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001553if support for multiple boot sources is required, it initializes the boot
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001554sequence used by plat_try_next_boot_source().
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001555
Dan Handley610e7e12018-03-01 18:44:00 +00001556In Arm standard platforms, this function initializes the storage abstraction
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001557layer used to load the next bootloader image.
1558
1559This function helps fulfill requirement 4 above.
1560
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001561Function : bl1_plat_sec_mem_layout() [mandatory]
1562~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001563
1564::
1565
1566 Argument : void
1567 Return : meminfo *
1568
1569This function should only be called on the cold boot path. It executes with the
1570MMU and data caches enabled. The pointer returned by this function must point to
1571a ``meminfo`` structure containing the extents and availability of secure RAM for
1572the BL1 stage.
1573
1574::
1575
1576 meminfo.total_base = Base address of secure RAM visible to BL1
1577 meminfo.total_size = Size of secure RAM visible to BL1
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001578
1579This information is used by BL1 to load the BL2 image in secure RAM. BL1 also
1580populates a similar structure to tell BL2 the extents of memory available for
1581its own use.
1582
1583This function helps fulfill requirements 4 and 5 above.
1584
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001585Function : bl1_plat_prepare_exit() [optional]
1586~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001587
1588::
1589
1590 Argument : entry_point_info_t *
1591 Return : void
1592
1593This function is called prior to exiting BL1 in response to the
1594``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform
1595platform specific clean up or bookkeeping operations before transferring
1596control to the next image. It receives the address of the ``entry_point_info_t``
1597structure passed from BL2. This function runs with MMU disabled.
1598
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001599Function : bl1_plat_set_ep_info() [optional]
1600~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001601
1602::
1603
1604 Argument : unsigned int image_id, entry_point_info_t *ep_info
1605 Return : void
1606
1607This function allows platforms to override ``ep_info`` for the given ``image_id``.
1608
1609The default implementation just returns.
1610
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001611Function : bl1_plat_get_next_image_id() [optional]
1612~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001613
1614::
1615
1616 Argument : void
1617 Return : unsigned int
1618
1619This and the following function must be overridden to enable the FWU feature.
1620
1621BL1 calls this function after platform setup to identify the next image to be
1622loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds
1623with the normal boot sequence, which loads and executes BL2. If the platform
1624returns a different image id, BL1 assumes that Firmware Update is required.
1625
Dan Handley610e7e12018-03-01 18:44:00 +00001626The default implementation always returns ``BL2_IMAGE_ID``. The Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001627platforms override this function to detect if firmware update is required, and
1628if so, return the first image in the firmware update process.
1629
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001630Function : bl1_plat_get_image_desc() [optional]
1631~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001632
1633::
1634
1635 Argument : unsigned int image_id
1636 Return : image_desc_t *
1637
1638BL1 calls this function to get the image descriptor information ``image_desc_t``
1639for the provided ``image_id`` from the platform.
1640
Dan Handley610e7e12018-03-01 18:44:00 +00001641The default implementation always returns a common BL2 image descriptor. Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001642standard platforms return an image descriptor corresponding to BL2 or one of
1643the firmware update images defined in the Trusted Board Boot Requirements
1644specification.
1645
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001646Function : bl1_plat_handle_pre_image_load() [optional]
1647~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001648
1649::
1650
Soby Mathew2f38ce32018-02-08 17:45:12 +00001651 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001652 Return : int
1653
1654This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001655corresponding to ``image_id``. This function is invoked in BL1, both in cold
1656boot and FWU code path, before loading the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001657
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001658Function : bl1_plat_handle_post_image_load() [optional]
1659~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001660
1661::
1662
Soby Mathew2f38ce32018-02-08 17:45:12 +00001663 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001664 Return : int
1665
1666This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001667corresponding to ``image_id``. This function is invoked in BL1, both in cold
1668boot and FWU code path, after loading and authenticating the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001669
Soby Mathewb1bf0442018-02-16 14:52:52 +00001670The default weak implementation of this function calculates the amount of
1671Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t``
1672structure at the beginning of this free memory and populates it. The address
1673of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint
1674information to BL2.
1675
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001676Function : bl1_plat_fwu_done() [optional]
1677~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001678
1679::
1680
1681 Argument : unsigned int image_id, uintptr_t image_src,
1682 unsigned int image_size
1683 Return : void
1684
1685BL1 calls this function when the FWU process is complete. It must not return.
1686The platform may override this function to take platform specific action, for
1687example to initiate the normal boot flow.
1688
1689The default implementation spins forever.
1690
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001691Function : bl1_plat_mem_check() [mandatory]
1692~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001693
1694::
1695
1696 Argument : uintptr_t mem_base, unsigned int mem_size,
1697 unsigned int flags
1698 Return : int
1699
1700BL1 calls this function while handling FWU related SMCs, more specifically when
1701copying or authenticating an image. Its responsibility is to ensure that the
1702region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and
1703that this memory corresponds to either a secure or non-secure memory region as
1704indicated by the security state of the ``flags`` argument.
1705
1706This function can safely assume that the value resulting from the addition of
1707``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not
1708overflow.
1709
1710This function must return 0 on success, a non-null error code otherwise.
1711
1712The default implementation of this function asserts therefore platforms must
1713override it when using the FWU feature.
1714
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001715Function : bl1_plat_mboot_init() [optional]
1716~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1717
1718::
1719
1720 Argument : void
1721 Return : void
1722
1723When the MEASURED_BOOT flag is enabled:
1724
1725- This function is used to initialize the backend driver(s) of measured boot.
1726- On the Arm FVP port, this function is used to initialize the Event Log
1727 backend driver, and also to write header information in the Event Log buffer.
1728
1729When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1730
1731Function : bl1_plat_mboot_finish() [optional]
1732~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1733
1734::
1735
1736 Argument : void
1737 Return : void
1738
1739When the MEASURED_BOOT flag is enabled:
1740
1741- This function is used to finalize the measured boot backend driver(s),
1742 and also, set the information for the next bootloader component to
1743 extend the measurement if needed.
1744- On the Arm FVP port, this function is used to pass the base address of
1745 the Event Log buffer and its size to BL2 via tb_fw_config to extend the
1746 Event Log buffer with the measurement of various images loaded by BL2.
1747 It results in panic on error.
1748
1749When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1750
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001751Boot Loader Stage 2 (BL2)
1752-------------------------
1753
1754The BL2 stage is executed only by the primary CPU, which is determined in BL1
1755using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at
Soby Mathew97b1bff2018-09-27 16:46:41 +01001756``BL2_BASE``. BL2 executes in Secure EL1 and and invokes
1757``plat_get_bl_image_load_info()`` to retrieve the list of images to load from
1758non-volatile storage to secure/non-secure RAM. After all the images are loaded
1759then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable
1760images to be passed to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001761
1762The following functions must be implemented by the platform port to enable BL2
1763to perform the above tasks.
1764
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001765Function : bl2_early_platform_setup2() [mandatory]
1766~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001767
1768::
1769
Soby Mathew97b1bff2018-09-27 16:46:41 +01001770 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001771 Return : void
1772
1773This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001774by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments
1775are platform specific.
1776
1777On Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001778
Manish V Badarkhe81414512020-06-24 15:58:38 +01001779 arg0 - Points to load address of FW_CONFIG
Soby Mathew97b1bff2018-09-27 16:46:41 +01001780
1781 arg1 - ``meminfo`` structure populated by BL1. The platform copies
1782 the contents of ``meminfo`` as it may be subsequently overwritten by BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001783
Dan Handley610e7e12018-03-01 18:44:00 +00001784On Arm standard platforms, this function also:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001785
1786- Initializes a UART (PL011 console), which enables access to the ``printf``
1787 family of functions in BL2.
1788
1789- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001790 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1791 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001792
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001793Function : bl2_plat_arch_setup() [mandatory]
1794~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001795
1796::
1797
1798 Argument : void
1799 Return : void
1800
1801This function executes with the MMU and data caches disabled. It is only called
1802by the primary CPU.
1803
1804The purpose of this function is to perform any architectural initialization
1805that varies across platforms.
1806
Dan Handley610e7e12018-03-01 18:44:00 +00001807On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001808
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001809Function : bl2_platform_setup() [mandatory]
1810~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001811
1812::
1813
1814 Argument : void
1815 Return : void
1816
1817This function may execute with the MMU and data caches enabled if the platform
1818port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only
1819called by the primary CPU.
1820
1821The purpose of this function is to perform any platform initialization
1822specific to BL2.
1823
Dan Handley610e7e12018-03-01 18:44:00 +00001824In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001825configuration of the TrustZone controller to allow non-secure masters access
1826to most of DRAM. Part of DRAM is reserved for secure world use.
1827
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001828Function : bl2_plat_handle_pre_image_load() [optional]
1829~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001830
1831::
1832
1833 Argument : unsigned int
1834 Return : int
1835
1836This function can be used by the platforms to update/use image information
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001837for given ``image_id``. This function is currently invoked in BL2 before
Soby Mathew97b1bff2018-09-27 16:46:41 +01001838loading each image.
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001839
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001840Function : bl2_plat_handle_post_image_load() [optional]
1841~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001842
1843::
1844
1845 Argument : unsigned int
1846 Return : int
1847
1848This function can be used by the platforms to update/use image information
1849for given ``image_id``. This function is currently invoked in BL2 after
Soby Mathew97b1bff2018-09-27 16:46:41 +01001850loading each image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001851
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001852Function : bl2_plat_preload_setup [optional]
1853~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001854
1855::
John Tsichritzisee10e792018-06-06 09:38:10 +01001856
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001857 Argument : void
1858 Return : void
1859
1860This optional function performs any BL2 platform initialization
1861required before image loading, that is not done later in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001862bl2_platform_setup(). Specifically, if support for multiple
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001863boot sources is required, it initializes the boot sequence used by
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001864plat_try_next_boot_source().
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001865
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001866Function : plat_try_next_boot_source() [optional]
1867~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001868
1869::
John Tsichritzisee10e792018-06-06 09:38:10 +01001870
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001871 Argument : void
1872 Return : int
1873
1874This optional function passes to the next boot source in the redundancy
1875sequence.
1876
1877This function moves the current boot redundancy source to the next
1878element in the boot sequence. If there are no more boot sources then it
1879must return 0, otherwise it must return 1. The default implementation
1880of this always returns 0.
1881
Sandrine Bailleuxeb5fadc2022-07-13 10:07:54 +02001882Function : bl2_plat_mboot_init() [optional]
1883~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1884
1885::
1886
1887 Argument : void
1888 Return : void
1889
1890When the MEASURED_BOOT flag is enabled:
1891
1892- This function is used to initialize the backend driver(s) of measured boot.
1893- On the Arm FVP port, this function is used to initialize the Event Log
1894 backend driver with the Event Log buffer information (base address and
1895 size) received from BL1. It results in panic on error.
1896
1897When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1898
1899Function : bl2_plat_mboot_finish() [optional]
1900~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1901
1902::
1903
1904 Argument : void
1905 Return : void
1906
1907When the MEASURED_BOOT flag is enabled:
1908
1909- This function is used to finalize the measured boot backend driver(s),
1910 and also, set the information for the next bootloader component to extend
1911 the measurement if needed.
1912- On the Arm FVP port, this function is used to pass the Event Log buffer
1913 information (base address and size) to non-secure(BL33) and trusted OS(BL32)
1914 via nt_fw and tos_fw config respectively. It results in panic on error.
1915
1916When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1917
Roberto Vargasb1584272017-11-20 13:36:10 +00001918Boot Loader Stage 2 (BL2) at EL3
1919--------------------------------
1920
Dan Handley610e7e12018-03-01 18:44:00 +00001921When the platform has a non-TF-A Boot ROM it is desirable to jump
1922directly to BL2 instead of TF-A BL1. In this case BL2 is expected to
Paul Beesleyf8640672019-04-12 14:19:42 +01001923execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design`
1924document for more information.
Roberto Vargasb1584272017-11-20 13:36:10 +00001925
1926All mandatory functions of BL2 must be implemented, except the functions
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001927bl2_early_platform_setup and bl2_el3_plat_arch_setup, because
1928their work is done now by bl2_el3_early_platform_setup and
1929bl2_el3_plat_arch_setup. These functions should generally implement
1930the bl1_plat_xxx() and bl2_plat_xxx() functionality combined.
Roberto Vargasb1584272017-11-20 13:36:10 +00001931
1932
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001933Function : bl2_el3_early_platform_setup() [mandatory]
1934~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001935
1936::
John Tsichritzisee10e792018-06-06 09:38:10 +01001937
Roberto Vargasb1584272017-11-20 13:36:10 +00001938 Argument : u_register_t, u_register_t, u_register_t, u_register_t
1939 Return : void
1940
1941This function executes with the MMU and data caches disabled. It is only called
1942by the primary CPU. This function receives four parameters which can be used
1943by the platform to pass any needed information from the Boot ROM to BL2.
1944
Dan Handley610e7e12018-03-01 18:44:00 +00001945On Arm standard platforms, this function does the following:
Roberto Vargasb1584272017-11-20 13:36:10 +00001946
1947- Initializes a UART (PL011 console), which enables access to the ``printf``
1948 family of functions in BL2.
1949
1950- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001951 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1952 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Roberto Vargasb1584272017-11-20 13:36:10 +00001953
1954- Initializes the private variables that define the memory layout used.
1955
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001956Function : bl2_el3_plat_arch_setup() [mandatory]
1957~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001958
1959::
John Tsichritzisee10e792018-06-06 09:38:10 +01001960
Roberto Vargasb1584272017-11-20 13:36:10 +00001961 Argument : void
1962 Return : void
1963
1964This function executes with the MMU and data caches disabled. It is only called
1965by the primary CPU.
1966
1967The purpose of this function is to perform any architectural initialization
1968that varies across platforms.
1969
Dan Handley610e7e12018-03-01 18:44:00 +00001970On Arm standard platforms, this function enables the MMU.
Roberto Vargasb1584272017-11-20 13:36:10 +00001971
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001972Function : bl2_el3_plat_prepare_exit() [optional]
1973~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001974
1975::
John Tsichritzisee10e792018-06-06 09:38:10 +01001976
Roberto Vargasb1584272017-11-20 13:36:10 +00001977 Argument : void
1978 Return : void
1979
1980This function is called prior to exiting BL2 and run the next image.
1981It should be used to perform platform specific clean up or bookkeeping
1982operations before transferring control to the next image. This function
1983runs with MMU disabled.
1984
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001985FWU Boot Loader Stage 2 (BL2U)
1986------------------------------
1987
1988The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU
1989process and is executed only by the primary CPU. BL1 passes control to BL2U at
1990``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for:
1991
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001992#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure
1993 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1.
1994 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U
1995 should be copied from. Subsequent handling of the SCP_BL2U image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001996 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function.
1997 If ``SCP_BL2U_BASE`` is not defined then this step is not performed.
1998
1999#. Any platform specific setup required to perform the FWU process. For
Dan Handley610e7e12018-03-01 18:44:00 +00002000 example, Arm standard platforms initialize the TZC controller so that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002001 normal world can access DDR memory.
2002
2003The following functions must be implemented by the platform port to enable
2004BL2U to perform the tasks mentioned above.
2005
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002006Function : bl2u_early_platform_setup() [mandatory]
2007~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002008
2009::
2010
2011 Argument : meminfo *mem_info, void *plat_info
2012 Return : void
2013
2014This function executes with the MMU and data caches disabled. It is only
2015called by the primary CPU. The arguments to this function is the address
2016of the ``meminfo`` structure and platform specific info provided by BL1.
2017
2018The platform may copy the contents of the ``mem_info`` and ``plat_info`` into
2019private storage as the original memory may be subsequently overwritten by BL2U.
2020
Dan Handley610e7e12018-03-01 18:44:00 +00002021On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002022to extract SCP_BL2U image information, which is then copied into a private
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002023variable.
2024
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002025Function : bl2u_plat_arch_setup() [mandatory]
2026~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002027
2028::
2029
2030 Argument : void
2031 Return : void
2032
2033This function executes with the MMU and data caches disabled. It is only
2034called by the primary CPU.
2035
2036The purpose of this function is to perform any architectural initialization
2037that varies across platforms, for example enabling the MMU (since the memory
2038map differs across platforms).
2039
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002040Function : bl2u_platform_setup() [mandatory]
2041~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002042
2043::
2044
2045 Argument : void
2046 Return : void
2047
2048This function may execute with the MMU and data caches enabled if the platform
2049port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only
2050called by the primary CPU.
2051
2052The purpose of this function is to perform any platform initialization
2053specific to BL2U.
2054
Dan Handley610e7e12018-03-01 18:44:00 +00002055In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002056configuration of the TrustZone controller to allow non-secure masters access
2057to most of DRAM. Part of DRAM is reserved for secure world use.
2058
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002059Function : bl2u_plat_handle_scp_bl2u() [optional]
2060~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002061
2062::
2063
2064 Argument : void
2065 Return : int
2066
2067This function is used to perform any platform-specific actions required to
2068handle the SCP firmware. Typically it transfers the image into SCP memory using
2069a platform-specific protocol and waits until SCP executes it and signals to the
2070Application Processor (AP) for BL2U execution to continue.
2071
2072This function returns 0 on success, a negative error code otherwise.
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002073This function is included if SCP_BL2U_BASE is defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002074
2075Boot Loader Stage 3-1 (BL31)
2076----------------------------
2077
2078During cold boot, the BL31 stage is executed only by the primary CPU. This is
2079determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes
2080control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all
2081CPUs. BL31 executes at EL3 and is responsible for:
2082
2083#. Re-initializing all architectural and platform state. Although BL1 performs
2084 some of this initialization, BL31 remains resident in EL3 and must ensure
2085 that EL3 architectural and platform state is completely initialized. It
2086 should make no assumptions about the system state when it receives control.
2087
2088#. Passing control to a normal world BL image, pre-loaded at a platform-
Soby Mathew97b1bff2018-09-27 16:46:41 +01002089 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list
2090 populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002091
2092#. Providing runtime firmware services. Currently, BL31 only implements a
2093 subset of the Power State Coordination Interface (PSCI) API as a runtime
2094 service. See Section 3.3 below for details of porting the PSCI
2095 implementation.
2096
2097#. Optionally passing control to the BL32 image, pre-loaded at a platform-
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002098 specific address by BL2. BL31 exports a set of APIs that allow runtime
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002099 services to specify the security state in which the next image should be
Soby Mathew97b1bff2018-09-27 16:46:41 +01002100 executed and run the corresponding image. On ARM platforms, BL31 uses the
2101 ``bl_params`` list populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002102
2103If BL31 is a reset vector, It also needs to handle the reset as specified in
2104section 2.2 before the tasks described above.
2105
2106The following functions must be implemented by the platform port to enable BL31
2107to perform the above tasks.
2108
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002109Function : bl31_early_platform_setup2() [mandatory]
2110~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002111
2112::
2113
Soby Mathew97b1bff2018-09-27 16:46:41 +01002114 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002115 Return : void
2116
2117This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01002118by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are
2119platform specific.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002120
Soby Mathew97b1bff2018-09-27 16:46:41 +01002121In Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002122
Soby Mathew97b1bff2018-09-27 16:46:41 +01002123 arg0 - The pointer to the head of `bl_params_t` list
2124 which is list of executable images following BL31,
2125
2126 arg1 - Points to load address of SOC_FW_CONFIG if present
Mikael Olsson0232da22021-02-12 17:30:16 +01002127 except in case of Arm FVP and Juno platform.
Manish V Badarkhe81414512020-06-24 15:58:38 +01002128
Mikael Olsson0232da22021-02-12 17:30:16 +01002129 In case of Arm FVP and Juno platform, points to load address
Manish V Badarkhe81414512020-06-24 15:58:38 +01002130 of FW_CONFIG.
Soby Mathew97b1bff2018-09-27 16:46:41 +01002131
2132 arg2 - Points to load address of HW_CONFIG if present
2133
2134 arg3 - A special value to verify platform parameters from BL2 to BL31. Not
2135 used in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002136
Soby Mathew97b1bff2018-09-27 16:46:41 +01002137The function runs through the `bl_param_t` list and extracts the entry point
2138information for BL32 and BL33. It also performs the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002139
2140- Initialize a UART (PL011 console), which enables access to the ``printf``
2141 family of functions in BL31.
2142
2143- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the
2144 CCI slave interface corresponding to the cluster that includes the primary
2145 CPU.
2146
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002147Function : bl31_plat_arch_setup() [mandatory]
2148~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002149
2150::
2151
2152 Argument : void
2153 Return : void
2154
2155This function executes with the MMU and data caches disabled. It is only called
2156by the primary CPU.
2157
2158The purpose of this function is to perform any architectural initialization
2159that varies across platforms.
2160
Dan Handley610e7e12018-03-01 18:44:00 +00002161On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002162
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002163Function : bl31_platform_setup() [mandatory]
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002164~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2165
2166::
2167
2168 Argument : void
2169 Return : void
2170
2171This function may execute with the MMU and data caches enabled if the platform
2172port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only
2173called by the primary CPU.
2174
2175The purpose of this function is to complete platform initialization so that both
2176BL31 runtime services and normal world software can function correctly.
2177
Dan Handley610e7e12018-03-01 18:44:00 +00002178On Arm standard platforms, this function does the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002179
2180- Initialize the generic interrupt controller.
2181
2182 Depending on the GIC driver selected by the platform, the appropriate GICv2
2183 or GICv3 initialization will be done, which mainly consists of:
2184
2185 - Enable secure interrupts in the GIC CPU interface.
2186 - Disable the legacy interrupt bypass mechanism.
2187 - Configure the priority mask register to allow interrupts of all priorities
2188 to be signaled to the CPU interface.
2189 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure.
2190 - Target all secure SPIs to CPU0.
2191 - Enable these secure interrupts in the GIC distributor.
2192 - Configure all other interrupts as non-secure.
2193 - Enable signaling of secure interrupts in the GIC distributor.
2194
2195- Enable system-level implementation of the generic timer counter through the
2196 memory mapped interface.
2197
2198- Grant access to the system counter timer module
2199
2200- Initialize the power controller device.
2201
2202 In particular, initialise the locks that prevent concurrent accesses to the
2203 power controller device.
2204
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002205Function : bl31_plat_runtime_setup() [optional]
2206~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002207
2208::
2209
2210 Argument : void
2211 Return : void
2212
2213The purpose of this function is allow the platform to perform any BL31 runtime
2214setup just prior to BL31 exit during cold boot. The default weak
Julius Werneraae9bb12017-09-18 16:49:48 -07002215implementation of this function will invoke ``console_switch_state()`` to switch
2216console output to consoles marked for use in the ``runtime`` state.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002217
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002218Function : bl31_plat_get_next_image_ep_info() [mandatory]
2219~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002220
2221::
2222
Sandrine Bailleux842117d2018-05-14 14:25:47 +02002223 Argument : uint32_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002224 Return : entry_point_info *
2225
2226This function may execute with the MMU and data caches enabled if the platform
2227port does the necessary initializations in ``bl31_plat_arch_setup()``.
2228
2229This function is called by ``bl31_main()`` to retrieve information provided by
2230BL2 for the next image in the security state specified by the argument. BL31
2231uses this information to pass control to that image in the specified security
2232state. This function must return a pointer to the ``entry_point_info`` structure
2233(that was copied during ``bl31_early_platform_setup()``) if the image exists. It
2234should return NULL otherwise.
2235
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002236Function : plat_rmmd_get_cca_attest_token() [mandatory when ENABLE_RME == 1]
Soby Mathew294e1cf2022-03-22 16:19:39 +00002237~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2238
2239::
2240
2241 Argument : uintptr_t, size_t *, uintptr_t, size_t
2242 Return : int
2243
2244This function returns the Platform attestation token.
2245
2246The parameters of the function are:
2247
2248 arg0 - A pointer to the buffer where the Platform token should be copied by
2249 this function. The buffer must be big enough to hold the Platform
2250 token.
2251
2252 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
2253 function returns the platform token length in this parameter.
2254
2255 arg2 - A pointer to the buffer where the challenge object is stored.
2256
2257 arg3 - The length of the challenge object in bytes. Possible values are 32,
2258 48 and 64.
2259
2260The function returns 0 on success, -EINVAL on failure.
2261
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002262Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1]
2263~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewf05d93a2022-03-22 16:21:19 +00002264
2265::
2266
2267 Argument : uintptr_t, size_t *, unsigned int
2268 Return : int
2269
2270This function returns the delegated realm attestation key which will be used to
2271sign Realm attestation token. The API currently only supports P-384 ECC curve
2272key.
2273
2274The parameters of the function are:
2275
2276 arg0 - A pointer to the buffer where the attestation key should be copied
2277 by this function. The buffer must be big enough to hold the
2278 attestation key.
2279
2280 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
2281 function returns the attestation key length in this parameter.
2282
2283 arg2 - The type of the elliptic curve to which the requested attestation key
2284 belongs.
2285
2286The function returns 0 on success, -EINVAL on failure.
2287
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002288Function : plat_rmmd_get_el3_rmm_shared_mem() [when ENABLE_RME == 1]
2289~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2290
2291::
2292
2293 Argument : uintptr_t *
2294 Return : size_t
2295
2296This function returns the size of the shared area between EL3 and RMM (or 0 on
2297failure). A pointer to the shared area (or a NULL pointer on failure) is stored
2298in the pointer passed as argument.
2299
Javier Almansa Sobrino4165e842022-04-25 17:18:15 +01002300Function : plat_rmmd_load_manifest() [when ENABLE_RME == 1]
2301~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2302
2303::
2304
2305 Arguments : rmm_manifest_t *manifest
2306 Return : int
2307
2308When ENABLE_RME is enabled, this function populates a boot manifest for the
2309RMM image and stores it in the area specified by manifest.
2310
2311When ENABLE_RME is disabled, this function is not used.
2312
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01002313Function : bl31_plat_enable_mmu [optional]
2314~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2315
2316::
2317
2318 Argument : uint32_t
2319 Return : void
2320
2321This function enables the MMU. The boot code calls this function with MMU and
2322caches disabled. This function should program necessary registers to enable
2323translation, and upon return, the MMU on the calling PE must be enabled.
2324
2325The function must honor flags passed in the first argument. These flags are
2326defined by the translation library, and can be found in the file
2327``include/lib/xlat_tables/xlat_mmu_helpers.h``.
2328
2329On DynamIQ systems, this function must not use stack while enabling MMU, which
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002330is how the function in xlat table library version 2 is implemented.
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01002331
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002332Function : plat_init_apkey [optional]
2333~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002334
2335::
2336
2337 Argument : void
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002338 Return : uint128_t
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002339
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002340This function returns the 128-bit value which can be used to program ARMv8.3
2341pointer authentication keys.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002342
2343The value should be obtained from a reliable source of randomness.
2344
2345This function is only needed if ARMv8.3 pointer authentication is used in the
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002346Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002347
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002348Function : plat_get_syscnt_freq2() [mandatory]
2349~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002350
2351::
2352
2353 Argument : void
2354 Return : unsigned int
2355
2356This function is used by the architecture setup code to retrieve the counter
2357frequency for the CPU's generic timer. This value will be programmed into the
Dan Handley610e7e12018-03-01 18:44:00 +00002358``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002359of the system counter, which is retrieved from the first entry in the frequency
2360modes table.
2361
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002362#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]
2363~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002364
2365When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in
2366bytes) aligned to the cache line boundary that should be allocated per-cpu to
2367accommodate all the bakery locks.
2368
2369If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker
2370calculates the size of the ``bakery_lock`` input section, aligns it to the
2371nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT``
2372and stores the result in a linker symbol. This constant prevents a platform
2373from relying on the linker and provide a more efficient mechanism for
2374accessing per-cpu bakery lock information.
2375
2376If this constant is defined and its value is not equal to the value
2377calculated by the linker then a link time assertion is raised. A compile time
2378assertion is raised if the value of the constant is not aligned to the cache
2379line boundary.
2380
Paul Beesleyf8640672019-04-12 14:19:42 +01002381.. _porting_guide_sdei_requirements:
2382
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002383SDEI porting requirements
2384~~~~~~~~~~~~~~~~~~~~~~~~~
2385
Paul Beesley606d8072019-03-13 13:58:02 +00002386The |SDEI| dispatcher requires the platform to provide the following macros
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002387and functions, of which some are optional, and some others mandatory.
2388
2389Macros
2390......
2391
2392Macro: PLAT_SDEI_NORMAL_PRI [mandatory]
2393^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2394
2395This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00002396Normal |SDEI| events on the platform. This must have a higher value
2397(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002398
2399Macro: PLAT_SDEI_CRITICAL_PRI [mandatory]
2400^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2401
2402This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00002403Critical |SDEI| events on the platform. This must have a lower value
2404(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002405
Paul Beesley606d8072019-03-13 13:58:02 +00002406**Note**: |SDEI| exception priorities must be the lowest among Secure
2407priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must
2408be higher than Normal |SDEI| priority.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002409
2410Functions
2411.........
2412
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002413Function: int plat_sdei_validate_entry_point() [optional]
2414^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002415
2416::
2417
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002418 Argument: uintptr_t ep, unsigned int client_mode
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002419 Return: int
2420
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002421This function validates the entry point address of the event handler provided by
2422the client for both event registration and *Complete and Resume* |SDEI| calls.
2423The function ensures that the address is valid in the client translation regime.
2424
2425The second argument is the exception level that the client is executing in. It
2426can be Non-Secure EL1 or Non-Secure EL2.
2427
2428The function must return ``0`` for successful validation, or ``-1`` upon failure.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002429
Dan Handley610e7e12018-03-01 18:44:00 +00002430The default implementation always returns ``0``. On Arm platforms, this function
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002431translates the entry point address within the client translation regime and
2432further ensures that the resulting physical address is located in Non-secure
2433DRAM.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002434
2435Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional]
2436^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2437
2438::
2439
2440 Argument: uint64_t
2441 Argument: unsigned int
2442 Return: void
2443
Paul Beesley606d8072019-03-13 13:58:02 +00002444|SDEI| specification requires that a PE comes out of reset with the events
2445masked. The client therefore is expected to call ``PE_UNMASK`` to unmask
2446|SDEI| events on the PE. No |SDEI| events can be dispatched until such
2447time.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002448
Paul Beesley606d8072019-03-13 13:58:02 +00002449Should a PE receive an interrupt that was bound to an |SDEI| event while the
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002450events are masked on the PE, the dispatcher implementation invokes the function
2451``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the
2452interrupt and the interrupt ID are passed as parameters.
2453
2454The default implementation only prints out a warning message.
2455
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -05002456.. _porting_guide_trng_requirements:
2457
2458TRNG porting requirements
2459~~~~~~~~~~~~~~~~~~~~~~~~~
2460
2461The |TRNG| backend requires the platform to provide the following values
2462and mandatory functions.
2463
2464Values
2465......
2466
2467value: uuid_t plat_trng_uuid [mandatory]
2468^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2469
2470This value must be defined to the UUID of the TRNG backend that is specific to
2471the hardware after ``plat_trng_setup`` function is called. This value must
2472conform to the SMCCC calling convention; The most significant 32 bits of the
2473UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in
2474w0 indicates failure to get a TRNG source.
2475
2476Functions
2477.........
2478
2479Function: void plat_entropy_setup(void) [mandatory]
2480^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2481
2482::
2483
2484 Argument: none
2485 Return: none
2486
2487This function is expected to do platform-specific initialization of any TRNG
2488hardware. This may include generating a UUID from a hardware-specific seed.
2489
2490Function: bool plat_get_entropy(uint64_t \*out) [mandatory]
2491^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2492
2493::
2494
2495 Argument: uint64_t *
2496 Return: bool
2497 Out : when the return value is true, the entropy has been written into the
2498 storage pointed to
2499
2500This function writes entropy into storage provided by the caller. If no entropy
2501is available, it must return false and the storage must not be written.
2502
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002503Power State Coordination Interface (in BL31)
2504--------------------------------------------
2505
Dan Handley610e7e12018-03-01 18:44:00 +00002506The TF-A implementation of the PSCI API is based around the concept of a
2507*power domain*. A *power domain* is a CPU or a logical group of CPUs which
2508share some state on which power management operations can be performed as
2509specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is
2510a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The
2511*power domains* are arranged in a hierarchical tree structure and each
2512*power domain* can be identified in a system by the cpu index of any CPU that
2513is part of that domain and a *power domain level*. A processing element (for
2514example, a CPU) is at level 0. If the *power domain* node above a CPU is a
2515logical grouping of CPUs that share some state, then level 1 is that group of
2516CPUs (for example, a cluster), and level 2 is a group of clusters (for
2517example, the system). More details on the power domain topology and its
Paul Beesleyf8640672019-04-12 14:19:42 +01002518organization can be found in :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002519
2520BL31's platform initialization code exports a pointer to the platform-specific
2521power management operations required for the PSCI implementation to function
2522correctly. This information is populated in the ``plat_psci_ops`` structure. The
2523PSCI implementation calls members of the ``plat_psci_ops`` structure for performing
2524power management operations on the power domains. For example, the target
2525CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()``
2526handler (if present) is called for the CPU power domain.
2527
2528The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to
2529describe composite power states specific to a platform. The PSCI implementation
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00002530defines a generic representation of the power-state parameter, which is an
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002531array of local power states where each index corresponds to a power domain
2532level. Each entry contains the local power state the power domain at that power
2533level could enter. It depends on the ``validate_power_state()`` handler to
2534convert the power-state parameter (possibly encoding a composite power state)
2535passed in a PSCI ``CPU_SUSPEND`` call to this representation.
2536
2537The following functions form part of platform port of PSCI functionality.
2538
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002539Function : plat_psci_stat_accounting_start() [optional]
2540~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002541
2542::
2543
2544 Argument : const psci_power_state_t *
2545 Return : void
2546
2547This is an optional hook that platforms can implement for residency statistics
2548accounting before entering a low power state. The ``pwr_domain_state`` field of
2549``state_info`` (first argument) can be inspected if stat accounting is done
2550differently at CPU level versus higher levels. As an example, if the element at
2551index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2552state, special hardware logic may be programmed in order to keep track of the
2553residency statistics. For higher levels (array indices > 0), the residency
2554statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2555default implementation will use PMF to capture timestamps.
2556
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002557Function : plat_psci_stat_accounting_stop() [optional]
2558~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002559
2560::
2561
2562 Argument : const psci_power_state_t *
2563 Return : void
2564
2565This is an optional hook that platforms can implement for residency statistics
2566accounting after exiting from a low power state. The ``pwr_domain_state`` field
2567of ``state_info`` (first argument) can be inspected if stat accounting is done
2568differently at CPU level versus higher levels. As an example, if the element at
2569index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2570state, special hardware logic may be programmed in order to keep track of the
2571residency statistics. For higher levels (array indices > 0), the residency
2572statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2573default implementation will use PMF to capture timestamps.
2574
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002575Function : plat_psci_stat_get_residency() [optional]
2576~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002577
2578::
2579
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -06002580 Argument : unsigned int, const psci_power_state_t *, unsigned int
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002581 Return : u_register_t
2582
2583This is an optional interface that is is invoked after resuming from a low power
2584state and provides the time spent resident in that low power state by the power
2585domain at a particular power domain level. When a CPU wakes up from suspend,
2586all its parent power domain levels are also woken up. The generic PSCI code
2587invokes this function for each parent power domain that is resumed and it
2588identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second
2589argument) describes the low power state that the power domain has resumed from.
2590The current CPU is the first CPU in the power domain to resume from the low
2591power state and the ``last_cpu_idx`` (third parameter) is the index of the last
2592CPU in the power domain to suspend and may be needed to calculate the residency
2593for that power domain.
2594
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002595Function : plat_get_target_pwr_state() [optional]
2596~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002597
2598::
2599
2600 Argument : unsigned int, const plat_local_state_t *, unsigned int
2601 Return : plat_local_state_t
2602
2603The PSCI generic code uses this function to let the platform participate in
2604state coordination during a power management operation. The function is passed
2605a pointer to an array of platform specific local power state ``states`` (second
2606argument) which contains the requested power state for each CPU at a particular
2607power domain level ``lvl`` (first argument) within the power domain. The function
2608is expected to traverse this array of upto ``ncpus`` (third argument) and return
2609a coordinated target power state by the comparing all the requested power
2610states. The target power state should not be deeper than any of the requested
2611power states.
2612
2613A weak definition of this API is provided by default wherein it assumes
2614that the platform assigns a local state value in order of increasing depth
2615of the power state i.e. for two power states X & Y, if X < Y
2616then X represents a shallower power state than Y. As a result, the
2617coordinated target local power state for a power domain will be the minimum
2618of the requested local power state values.
2619
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002620Function : plat_get_power_domain_tree_desc() [mandatory]
2621~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002622
2623::
2624
2625 Argument : void
2626 Return : const unsigned char *
2627
2628This function returns a pointer to the byte array containing the power domain
2629topology tree description. The format and method to construct this array are
Paul Beesleyf8640672019-04-12 14:19:42 +01002630described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI
2631initialization code requires this array to be described by the platform, either
2632statically or dynamically, to initialize the power domain topology tree. In case
2633the array is populated dynamically, then plat_core_pos_by_mpidr() and
2634plat_my_core_pos() should also be implemented suitably so that the topology tree
2635description matches the CPU indices returned by these APIs. These APIs together
2636form the platform interface for the PSCI topology framework.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002637
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002638Function : plat_setup_psci_ops() [mandatory]
2639~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002640
2641::
2642
2643 Argument : uintptr_t, const plat_psci_ops **
2644 Return : int
2645
2646This function may execute with the MMU and data caches enabled if the platform
2647port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
2648called by the primary CPU.
2649
2650This function is called by PSCI initialization code. Its purpose is to let
2651the platform layer know about the warm boot entrypoint through the
2652``sec_entrypoint`` (first argument) and to export handler routines for
2653platform-specific psci power management actions by populating the passed
2654pointer with a pointer to BL31's private ``plat_psci_ops`` structure.
2655
2656A description of each member of this structure is given below. Please refer to
Dan Handley610e7e12018-03-01 18:44:00 +00002657the Arm FVP specific implementation of these handlers in
Paul Beesleyf8640672019-04-12 14:19:42 +01002658``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002659platform wants to support, the associated operation or operations in this
2660structure must be provided and implemented (Refer section 4 of
Paul Beesleyf8640672019-04-12 14:19:42 +01002661:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI
Dan Handley610e7e12018-03-01 18:44:00 +00002662function in a platform port, the operation should be removed from this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002663structure instead of providing an empty implementation.
2664
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002665plat_psci_ops.cpu_standby()
2666...........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002667
2668Perform the platform-specific actions to enter the standby state for a cpu
2669indicated by the passed argument. This provides a fast path for CPU standby
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002670wherein overheads of PSCI state management and lock acquisition is avoided.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002671For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation,
2672the suspend state type specified in the ``power-state`` parameter should be
2673STANDBY and the target power domain level specified should be the CPU. The
2674handler should put the CPU into a low power retention state (usually by
2675issuing a wfi instruction) and ensure that it can be woken up from that
2676state by a normal interrupt. The generic code expects the handler to succeed.
2677
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002678plat_psci_ops.pwr_domain_on()
2679.............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002680
2681Perform the platform specific actions to power on a CPU, specified
2682by the ``MPIDR`` (first argument). The generic code expects the platform to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002683return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002684
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002685plat_psci_ops.pwr_domain_off()
2686..............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002687
2688Perform the platform specific actions to prepare to power off the calling CPU
2689and its higher parent power domain levels as indicated by the ``target_state``
2690(first argument). It is called by the PSCI ``CPU_OFF`` API implementation.
2691
2692The ``target_state`` encodes the platform coordinated target local power states
2693for the CPU power domain and its parent power domain levels. The handler
2694needs to perform power management operation corresponding to the local state
2695at each power level.
2696
2697For this handler, the local power state for the CPU power domain will be a
2698power down state where as it could be either power down, retention or run state
2699for the higher power domain levels depending on the result of state
2700coordination. The generic code expects the handler to succeed.
2701
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002702plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]
2703...........................................................
Varun Wadekarae87f4b2017-07-10 16:02:05 -07002704
2705This optional function may be used as a performance optimization to replace
2706or complement pwr_domain_suspend() on some platforms. Its calling semantics
2707are identical to pwr_domain_suspend(), except the PSCI implementation only
2708calls this function when suspending to a power down state, and it guarantees
2709that data caches are enabled.
2710
2711When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches
2712before calling pwr_domain_suspend(). If the target_state corresponds to a
2713power down state and it is safe to perform some or all of the platform
2714specific actions in that function with data caches enabled, it may be more
2715efficient to move those actions to this function. When HW_ASSISTED_COHERENCY
2716= 1, data caches remain enabled throughout, and so there is no advantage to
2717moving platform specific actions to this function.
2718
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002719plat_psci_ops.pwr_domain_suspend()
2720..................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002721
2722Perform the platform specific actions to prepare to suspend the calling
2723CPU and its higher parent power domain levels as indicated by the
2724``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND``
2725API implementation.
2726
2727The ``target_state`` has a similar meaning as described in
2728the ``pwr_domain_off()`` operation. It encodes the platform coordinated
2729target local power states for the CPU power domain and its parent
2730power domain levels. The handler needs to perform power management operation
2731corresponding to the local state at each power level. The generic code
2732expects the handler to succeed.
2733
Douglas Raillarda84996b2017-08-02 16:57:32 +01002734The difference between turning a power domain off versus suspending it is that
2735in the former case, the power domain is expected to re-initialize its state
2736when it is next powered on (see ``pwr_domain_on_finish()``). In the latter
2737case, the power domain is expected to save enough state so that it can resume
2738execution by restoring this state when its powered on (see
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002739``pwr_domain_suspend_finish()``).
2740
Douglas Raillarda84996b2017-08-02 16:57:32 +01002741When suspending a core, the platform can also choose to power off the GICv3
2742Redistributor and ITS through an implementation-defined sequence. To achieve
2743this safely, the ITS context must be saved first. The architectural part is
2744implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed
2745sequence is implementation defined and it is therefore the responsibility of
2746the platform code to implement the necessary sequence. Then the GIC
2747Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper.
2748Powering off the Redistributor requires the implementation to support it and it
2749is the responsibility of the platform code to execute the right implementation
2750defined sequence.
2751
2752When a system suspend is requested, the platform can also make use of the
2753``gicv3_distif_save()`` helper to save the context of the GIC Distributor after
2754it has saved the context of the Redistributors and ITS of all the cores in the
2755system. The context of the Distributor can be large and may require it to be
2756allocated in a special area if it cannot fit in the platform's global static
2757data, for example in DRAM. The Distributor can then be powered down using an
2758implementation-defined sequence.
2759
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002760plat_psci_ops.pwr_domain_pwr_down_wfi()
2761.......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002762
2763This is an optional function and, if implemented, is expected to perform
2764platform specific actions including the ``wfi`` invocation which allows the
2765CPU to powerdown. Since this function is invoked outside the PSCI locks,
2766the actions performed in this hook must be local to the CPU or the platform
2767must ensure that races between multiple CPUs cannot occur.
2768
2769The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()``
2770operation and it encodes the platform coordinated target local power states for
2771the CPU power domain and its parent power domain levels. This function must
2772not return back to the caller.
2773
2774If this function is not implemented by the platform, PSCI generic
2775implementation invokes ``psci_power_down_wfi()`` for power down.
2776
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002777plat_psci_ops.pwr_domain_on_finish()
2778....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002779
2780This function is called by the PSCI implementation after the calling CPU is
2781powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
2782It performs the platform-specific setup required to initialize enough state for
2783this CPU to enter the normal world and also provide secure runtime firmware
2784services.
2785
2786The ``target_state`` (first argument) is the prior state of the power domains
2787immediately before the CPU was turned on. It indicates which power domains
2788above the CPU might require initialization due to having previously been in
2789low power states. The generic code expects the handler to succeed.
2790
Madhukar Pappireddy33bd5142019-08-12 18:31:33 -05002791plat_psci_ops.pwr_domain_on_finish_late() [optional]
2792...........................................................
2793
2794This optional function is called by the PSCI implementation after the calling
2795CPU is fully powered on with respective data caches enabled. The calling CPU and
2796the associated cluster are guaranteed to be participating in coherency. This
2797function gives the flexibility to perform any platform-specific actions safely,
2798such as initialization or modification of shared data structures, without the
2799overhead of explicit cache maintainace operations.
2800
2801The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()``
2802operation. The generic code expects the handler to succeed.
2803
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002804plat_psci_ops.pwr_domain_suspend_finish()
2805.........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002806
2807This function is called by the PSCI implementation after the calling CPU is
2808powered on and released from reset in response to an asynchronous wakeup
2809event, for example a timer interrupt that was programmed by the CPU during the
2810``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
2811setup required to restore the saved state for this CPU to resume execution
2812in the normal world and also provide secure runtime firmware services.
2813
2814The ``target_state`` (first argument) has a similar meaning as described in
2815the ``pwr_domain_on_finish()`` operation. The generic code expects the platform
2816to succeed.
2817
Douglas Raillarda84996b2017-08-02 16:57:32 +01002818If the Distributor, Redistributors or ITS have been powered off as part of a
2819suspend, their context must be restored in this function in the reverse order
2820to how they were saved during suspend sequence.
2821
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002822plat_psci_ops.system_off()
2823..........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002824
2825This function is called by PSCI implementation in response to a ``SYSTEM_OFF``
2826call. It performs the platform-specific system poweroff sequence after
2827notifying the Secure Payload Dispatcher.
2828
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002829plat_psci_ops.system_reset()
2830............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002831
2832This function is called by PSCI implementation in response to a ``SYSTEM_RESET``
2833call. It performs the platform-specific system reset sequence after
2834notifying the Secure Payload Dispatcher.
2835
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002836plat_psci_ops.validate_power_state()
2837....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002838
2839This function is called by the PSCI implementation during the ``CPU_SUSPEND``
2840call to validate the ``power_state`` parameter of the PSCI API and if valid,
2841populate it in ``req_state`` (second argument) array as power domain level
2842specific local states. If the ``power_state`` is invalid, the platform must
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002843return PSCI_E_INVALID_PARAMS as error, which is propagated back to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002844normal world PSCI client.
2845
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002846plat_psci_ops.validate_ns_entrypoint()
2847......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002848
2849This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
2850``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point``
2851parameter passed by the normal world. If the ``entry_point`` is invalid,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002852the platform must return PSCI_E_INVALID_ADDRESS as error, which is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002853propagated back to the normal world PSCI client.
2854
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002855plat_psci_ops.get_sys_suspend_power_state()
2856...........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002857
2858This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
2859call to get the ``req_state`` parameter from platform which encodes the power
2860domain level specific local states to suspend to system affinity level. The
2861``req_state`` will be utilized to do the PSCI state coordination and
2862``pwr_domain_suspend()`` will be invoked with the coordinated target state to
2863enter system suspend.
2864
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002865plat_psci_ops.get_pwr_lvl_state_idx()
2866.....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002867
2868This is an optional function and, if implemented, is invoked by the PSCI
2869implementation to convert the ``local_state`` (first argument) at a specified
2870``pwr_lvl`` (second argument) to an index between 0 and
2871``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform
2872supports more than two local power states at each power domain level, that is
2873``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these
2874local power states.
2875
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002876plat_psci_ops.translate_power_state_by_mpidr()
2877..............................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002878
2879This is an optional function and, if implemented, verifies the ``power_state``
2880(second argument) parameter of the PSCI API corresponding to a target power
2881domain. The target power domain is identified by using both ``MPIDR`` (first
2882argument) and the power domain level encoded in ``power_state``. The power domain
2883level specific local states are to be extracted from ``power_state`` and be
2884populated in the ``output_state`` (third argument) array. The functionality
2885is similar to the ``validate_power_state`` function described above and is
2886envisaged to be used in case the validity of ``power_state`` depend on the
2887targeted power domain. If the ``power_state`` is invalid for the targeted power
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002888domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002889function is not implemented, then the generic implementation relies on
2890``validate_power_state`` function to translate the ``power_state``.
2891
2892This function can also be used in case the platform wants to support local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002893power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002894APIs as described in Section 5.18 of `PSCI`_.
2895
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002896plat_psci_ops.get_node_hw_state()
2897.................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002898
2899This is an optional function. If implemented this function is intended to return
2900the power state of a node (identified by the first parameter, the ``MPIDR``) in
2901the power domain topology (identified by the second parameter, ``power_level``),
2902as retrieved from a power controller or equivalent component on the platform.
2903Upon successful completion, the implementation must map and return the final
2904status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it
2905must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as
2906appropriate.
2907
2908Implementations are not expected to handle ``power_levels`` greater than
2909``PLAT_MAX_PWR_LVL``.
2910
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002911plat_psci_ops.system_reset2()
2912.............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002913
2914This is an optional function. If implemented this function is
2915called during the ``SYSTEM_RESET2`` call to perform a reset
2916based on the first parameter ``reset_type`` as specified in
2917`PSCI`_. The parameter ``cookie`` can be used to pass additional
2918reset information. If the ``reset_type`` is not supported, the
2919function must return ``PSCI_E_NOT_SUPPORTED``. For architectural
2920resets, all failures must return ``PSCI_E_INVALID_PARAMETERS``
2921and vendor reset can return other PSCI error codes as defined
2922in `PSCI`_. On success this function will not return.
2923
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002924plat_psci_ops.write_mem_protect()
2925.................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002926
2927This is an optional function. If implemented it enables or disables the
2928``MEM_PROTECT`` functionality based on the value of ``val``.
2929A non-zero value enables ``MEM_PROTECT`` and a value of zero
2930disables it. Upon encountering failures it must return a negative value
2931and on success it must return 0.
2932
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002933plat_psci_ops.read_mem_protect()
2934................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002935
2936This is an optional function. If implemented it returns the current
2937state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering
2938failures it must return a negative value and on success it must
2939return 0.
2940
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002941plat_psci_ops.mem_protect_chk()
2942...............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002943
2944This is an optional function. If implemented it checks if a memory
2945region defined by a base address ``base`` and with a size of ``length``
2946bytes is protected by ``MEM_PROTECT``. If the region is protected
2947then it must return 0, otherwise it must return a negative number.
2948
Paul Beesleyf8640672019-04-12 14:19:42 +01002949.. _porting_guide_imf_in_bl31:
2950
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002951Interrupt Management framework (in BL31)
2952----------------------------------------
2953
2954BL31 implements an Interrupt Management Framework (IMF) to manage interrupts
2955generated in either security state and targeted to EL1 or EL2 in the non-secure
2956state or EL3/S-EL1 in the secure state. The design of this framework is
Paul Beesleyf8640672019-04-12 14:19:42 +01002957described in the :ref:`Interrupt Management Framework`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002958
2959A platform should export the following APIs to support the IMF. The following
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002960text briefly describes each API and its implementation in Arm standard
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002961platforms. The API implementation depends upon the type of interrupt controller
Dan Handley610e7e12018-03-01 18:44:00 +00002962present in the platform. Arm standard platform layer supports both
2963`Arm Generic Interrupt Controller version 2.0 (GICv2)`_
2964and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the
2965FVP can be configured to use either GICv2 or GICv3 depending on the build flag
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01002966``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more
2967details).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002968
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05002969See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`.
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002970
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002971Function : plat_interrupt_type_to_line() [mandatory]
2972~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002973
2974::
2975
2976 Argument : uint32_t, uint32_t
2977 Return : uint32_t
2978
Dan Handley610e7e12018-03-01 18:44:00 +00002979The Arm processor signals an interrupt exception either through the IRQ or FIQ
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002980interrupt line. The specific line that is signaled depends on how the interrupt
2981controller (IC) reports different interrupt types from an execution context in
2982either security state. The IMF uses this API to determine which interrupt line
2983the platform IC uses to signal each type of interrupt supported by the framework
2984from a given security state. This API must be invoked at EL3.
2985
2986The first parameter will be one of the ``INTR_TYPE_*`` values (see
Paul Beesleyf8640672019-04-12 14:19:42 +01002987:ref:`Interrupt Management Framework`) indicating the target type of the
2988interrupt, the second parameter is the security state of the originating
2989execution context. The return result is the bit position in the ``SCR_EL3``
2990register of the respective interrupt trap: IRQ=1, FIQ=2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002991
Dan Handley610e7e12018-03-01 18:44:00 +00002992In the case of Arm standard platforms using GICv2, S-EL1 interrupts are
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002993configured as FIQs and Non-secure interrupts as IRQs from either security
2994state.
2995
Dan Handley610e7e12018-03-01 18:44:00 +00002996In the case of Arm standard platforms using GICv3, the interrupt line to be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002997configured depends on the security state of the execution context when the
2998interrupt is signalled and are as follows:
2999
3000- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in
3001 NS-EL0/1/2 context.
3002- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ
3003 in the NS-EL0/1/2 context.
3004- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2
3005 context.
3006
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003007Function : plat_ic_get_pending_interrupt_type() [mandatory]
3008~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003009
3010::
3011
3012 Argument : void
3013 Return : uint32_t
3014
3015This API returns the type of the highest priority pending interrupt at the
3016platform IC. The IMF uses the interrupt type to retrieve the corresponding
3017handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt
3018pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``,
3019``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3.
3020
Dan Handley610e7e12018-03-01 18:44:00 +00003021In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003022Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of
3023the pending interrupt. The type of interrupt depends upon the id value as
3024follows.
3025
3026#. id < 1022 is reported as a S-EL1 interrupt
3027#. id = 1022 is reported as a Non-secure interrupt.
3028#. id = 1023 is reported as an invalid interrupt type.
3029
Dan Handley610e7e12018-03-01 18:44:00 +00003030In the case of Arm standard platforms using GICv3, the system register
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003031``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*,
3032is read to determine the id of the pending interrupt. The type of interrupt
3033depends upon the id value as follows.
3034
3035#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt
3036#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt.
3037#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type.
3038#. All other interrupt id's are reported as EL3 interrupt.
3039
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003040Function : plat_ic_get_pending_interrupt_id() [mandatory]
3041~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003042
3043::
3044
3045 Argument : void
3046 Return : uint32_t
3047
3048This API returns the id of the highest priority pending interrupt at the
3049platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt
3050pending.
3051
Dan Handley610e7e12018-03-01 18:44:00 +00003052In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003053Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the
3054pending interrupt. The id that is returned by API depends upon the value of
3055the id read from the interrupt controller as follows.
3056
3057#. id < 1022. id is returned as is.
3058#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register*
3059 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt.
3060 This id is returned by the API.
3061#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned.
3062
Dan Handley610e7e12018-03-01 18:44:00 +00003063In the case of Arm standard platforms using GICv3, if the API is invoked from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003064EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt
3065group 0 Register*, is read to determine the id of the pending interrupt. The id
3066that is returned by API depends upon the value of the id read from the
3067interrupt controller as follows.
3068
3069#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is.
3070#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system
3071 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1
3072 Register* is read to determine the id of the group 1 interrupt. This id
3073 is returned by the API as long as it is a valid interrupt id
3074#. If the id is any of the special interrupt identifiers,
3075 ``INTR_ID_UNAVAILABLE`` is returned.
3076
3077When the API invoked from S-EL1 for GICv3 systems, the id read from system
3078register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003079Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003080``INTR_ID_UNAVAILABLE`` is returned.
3081
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003082Function : plat_ic_acknowledge_interrupt() [mandatory]
3083~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003084
3085::
3086
3087 Argument : void
3088 Return : uint32_t
3089
3090This API is used by the CPU to indicate to the platform IC that processing of
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01003091the highest pending interrupt has begun. It should return the raw, unmodified
3092value obtained from the interrupt controller when acknowledging an interrupt.
3093The actual interrupt number shall be extracted from this raw value using the API
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05003094`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003095
Dan Handley610e7e12018-03-01 18:44:00 +00003096This function in Arm standard platforms using GICv2, reads the *Interrupt
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003097Acknowledge Register* (``GICC_IAR``). This changes the state of the highest
3098priority pending interrupt from pending to active in the interrupt controller.
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01003099It returns the value read from the ``GICC_IAR``, unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003100
Dan Handley610e7e12018-03-01 18:44:00 +00003101In the case of Arm standard platforms using GICv3, if the API is invoked
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003102from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt
3103Acknowledge Register group 0*. If the API is invoked from S-EL1, the function
3104reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register
3105group 1*. The read changes the state of the highest pending interrupt from
3106pending to active in the interrupt controller. The value read is returned
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01003107unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003108
3109The TSP uses this API to start processing of the secure physical timer
3110interrupt.
3111
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003112Function : plat_ic_end_of_interrupt() [mandatory]
3113~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003114
3115::
3116
3117 Argument : uint32_t
3118 Return : void
3119
3120This API is used by the CPU to indicate to the platform IC that processing of
3121the interrupt corresponding to the id (passed as the parameter) has
3122finished. The id should be the same as the id returned by the
3123``plat_ic_acknowledge_interrupt()`` API.
3124
Dan Handley610e7e12018-03-01 18:44:00 +00003125Arm standard platforms write the id to the *End of Interrupt Register*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003126(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1``
3127system register in case of GICv3 depending on where the API is invoked from,
3128EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt
3129controller.
3130
3131The TSP uses this API to finish processing of the secure physical timer
3132interrupt.
3133
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003134Function : plat_ic_get_interrupt_type() [mandatory]
3135~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003136
3137::
3138
3139 Argument : uint32_t
3140 Return : uint32_t
3141
3142This API returns the type of the interrupt id passed as the parameter.
3143``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid
3144interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is
3145returned depending upon how the interrupt has been configured by the platform
3146IC. This API must be invoked at EL3.
3147
Dan Handley610e7e12018-03-01 18:44:00 +00003148Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003149and Non-secure interrupts as Group1 interrupts. It reads the group value
3150corresponding to the interrupt id from the relevant *Interrupt Group Register*
3151(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt.
3152
Dan Handley610e7e12018-03-01 18:44:00 +00003153In the case of Arm standard platforms using GICv3, both the *Interrupt Group
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003154Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register*
3155(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured
3156as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt.
3157
3158Crash Reporting mechanism (in BL31)
3159-----------------------------------
3160
3161BL31 implements a crash reporting mechanism which prints the various registers
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01003162of the CPU to enable quick crash analysis and debugging. This mechanism relies
Paul Beesley1fbc97b2019-01-11 18:26:51 +00003163on the platform implementing ``plat_crash_console_init``,
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01003164``plat_crash_console_putc`` and ``plat_crash_console_flush``.
3165
3166The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample
3167implementation of all of them. Platforms may include this file to their
3168makefiles in order to benefit from them. By default, they will cause the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07003169output to be routed over the normal console infrastructure and get printed on
3170consoles configured to output in crash state. ``console_set_scope()`` can be
3171used to control whether a console is used for crash output.
Paul Beesleyba3ed402019-03-13 16:20:44 +00003172
3173.. note::
3174 Platforms are responsible for making sure that they only mark consoles for
3175 use in the crash scope that are able to support this, i.e. that are written
3176 in assembly and conform with the register clobber rules for putc()
3177 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003178
Julius Werneraae9bb12017-09-18 16:49:48 -07003179In some cases (such as debugging very early crashes that happen before the
3180normal boot console can be set up), platforms may want to control crash output
Julius Werner1338c9c2018-11-19 14:25:55 -08003181more explicitly. These platforms may instead provide custom implementations for
3182these. They are executed outside of a C environment and without a stack. Many
3183console drivers provide functions named ``console_xxx_core_init/putc/flush``
3184that are designed to be used by these functions. See Arm platforms (like juno)
3185for an example of this.
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01003186
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003187Function : plat_crash_console_init [mandatory]
3188~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003189
3190::
3191
3192 Argument : void
3193 Return : int
3194
3195This API is used by the crash reporting mechanism to initialize the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07003196console. It must only use the general purpose registers x0 through x7 to do the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003197initialization and returns 1 on success.
3198
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003199Function : plat_crash_console_putc [mandatory]
3200~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003201
3202::
3203
3204 Argument : int
3205 Return : int
3206
3207This API is used by the crash reporting mechanism to print a character on the
3208designated crash console. It must only use general purpose registers x1 and
3209x2 to do its work. The parameter and the return value are in general purpose
3210register x0.
3211
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003212Function : plat_crash_console_flush [mandatory]
3213~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003214
3215::
3216
3217 Argument : void
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05003218 Return : void
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003219
3220This API is used by the crash reporting mechanism to force write of all buffered
3221data on the designated crash console. It should only use general purpose
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05003222registers x0 through x5 to do its work.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003223
Manish Pandey9c9f38a2020-06-30 00:46:08 +01003224.. _External Abort handling and RAS Support:
3225
Jeenu Viswambharane34bf582018-10-12 08:48:36 +01003226External Abort handling and RAS Support
3227---------------------------------------
Jeenu Viswambharanbf235bc2018-07-12 10:00:01 +01003228
3229Function : plat_ea_handler
3230~~~~~~~~~~~~~~~~~~~~~~~~~~
3231
3232::
3233
3234 Argument : int
3235 Argument : uint64_t
3236 Argument : void *
3237 Argument : void *
3238 Argument : uint64_t
3239 Return : void
3240
3241This function is invoked by the RAS framework for the platform to handle an
3242External Abort received at EL3. The intention of the function is to attempt to
3243resolve the cause of External Abort and return; if that's not possible, to
3244initiate orderly shutdown of the system.
3245
3246The first parameter (``int ea_reason``) indicates the reason for External Abort.
3247Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``.
3248
3249The second parameter (``uint64_t syndrome``) is the respective syndrome
3250presented to EL3 after having received the External Abort. Depending on the
3251nature of the abort (as can be inferred from the ``ea_reason`` parameter), this
3252can be the content of either ``ESR_EL3`` or ``DISR_EL1``.
3253
3254The third parameter (``void *cookie``) is unused for now. The fourth parameter
3255(``void *handle``) is a pointer to the preempted context. The fifth parameter
3256(``uint64_t flags``) indicates the preempted security state. These parameters
3257are received from the top-level exception handler.
3258
3259If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this
3260function iterates through RAS handlers registered by the platform. If any of the
3261RAS handlers resolve the External Abort, no further action is taken.
3262
3263If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers
3264could resolve the External Abort, the default implementation prints an error
3265message, and panics.
3266
3267Function : plat_handle_uncontainable_ea
3268~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3269
3270::
3271
3272 Argument : int
3273 Argument : uint64_t
3274 Return : void
3275
3276This function is invoked by the RAS framework when an External Abort of
3277Uncontainable type is received at EL3. Due to the critical nature of
3278Uncontainable errors, the intention of this function is to initiate orderly
3279shutdown of the system, and is not expected to return.
3280
3281This function must be implemented in assembly.
3282
3283The first and second parameters are the same as that of ``plat_ea_handler``.
3284
3285The default implementation of this function calls
3286``report_unhandled_exception``.
3287
3288Function : plat_handle_double_fault
3289~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3290
3291::
3292
3293 Argument : int
3294 Argument : uint64_t
3295 Return : void
3296
3297This function is invoked by the RAS framework when another External Abort is
3298received at EL3 while one is already being handled. I.e., a call to
3299``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of
3300this function is to initiate orderly shutdown of the system, and is not expected
3301recover or return.
3302
3303This function must be implemented in assembly.
3304
3305The first and second parameters are the same as that of ``plat_ea_handler``.
3306
3307The default implementation of this function calls
3308``report_unhandled_exception``.
3309
3310Function : plat_handle_el3_ea
3311~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3312
3313::
3314
3315 Return : void
3316
3317This function is invoked when an External Abort is received while executing in
3318EL3. Due to its critical nature, the intention of this function is to initiate
3319orderly shutdown of the system, and is not expected recover or return.
3320
3321This function must be implemented in assembly.
3322
3323The default implementation of this function calls
3324``report_unhandled_exception``.
3325
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003326Build flags
3327-----------
3328
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003329There are some build flags which can be defined by the platform to control
3330inclusion or exclusion of certain BL stages from the FIP image. These flags
3331need to be defined in the platform makefile which will get included by the
3332build system.
3333
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003334- **NEED_BL33**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003335 By default, this flag is defined ``yes`` by the build system and ``BL33``
3336 build option should be supplied as a build option. The platform has the
3337 option of excluding the BL33 image in the ``fip`` image by defining this flag
3338 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE``
3339 are used, this flag will be set to ``no`` automatically.
3340
Paul Beesley07f0a312019-05-16 13:33:18 +01003341Platform include paths
3342----------------------
3343
3344Platforms are allowed to add more include paths to be passed to the compiler.
3345The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in
3346particular for the file ``platform_def.h``.
3347
3348Example:
3349
3350.. code:: c
3351
3352 PLAT_INCLUDES += -Iinclude/plat/myplat/include
3353
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003354C Library
3355---------
3356
3357To avoid subtle toolchain behavioral dependencies, the header files provided
3358by the compiler are not used. The software is built with the ``-nostdinc`` flag
3359to ensure no headers are included from the toolchain inadvertently. Instead the
Dan Handley610e7e12018-03-01 18:44:00 +00003360required headers are included in the TF-A source tree. The library only
3361contains those C library definitions required by the local implementation. If
3362more functionality is required, the needed library functions will need to be
3363added to the local implementation.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003364
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003365Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have
Paul Beesleyf2ec7142019-10-04 16:17:46 +00003366been written specifically for TF-A. Some implementation files have been obtained
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003367from `FreeBSD`_, others have been written specifically for TF-A as well. The
3368files can be found in ``include/lib/libc`` and ``lib/libc``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003369
Sandrine Bailleux6f0ecd72019-02-08 14:46:42 +01003370SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources
3371can be obtained from http://github.com/freebsd/freebsd.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003372
3373Storage abstraction layer
3374-------------------------
3375
Louis Mayencourtb5469002019-07-15 13:56:03 +01003376In order to improve platform independence and portability a storage abstraction
3377layer is used to load data from non-volatile platform storage. Currently
3378storage access is only required by BL1 and BL2 phases and performed inside the
3379``load_image()`` function in ``bl_common.c``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003380
Louis Mayencourtb5469002019-07-15 13:56:03 +01003381.. uml:: ../resources/diagrams/plantuml/io_framework_usage_overview.puml
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003382
Dan Handley610e7e12018-03-01 18:44:00 +00003383It is mandatory to implement at least one storage driver. For the Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003384development platforms the Firmware Image Package (FIP) driver is provided as
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01003385the default means to load data from storage (see :ref:`firmware_design_fip`).
3386The storage layer is described in the header file
3387``include/drivers/io/io_storage.h``. The implementation of the common library is
3388in ``drivers/io/io_storage.c`` and the driver files are located in
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003389``drivers/io/``.
3390
Louis Mayencourtb5469002019-07-15 13:56:03 +01003391.. uml:: ../resources/diagrams/plantuml/io_arm_class_diagram.puml
3392
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003393Each IO driver must provide ``io_dev_*`` structures, as described in
3394``drivers/io/io_driver.h``. These are returned via a mandatory registration
3395function that is called on platform initialization. The semi-hosting driver
3396implementation in ``io_semihosting.c`` can be used as an example.
3397
Louis Mayencourtb5469002019-07-15 13:56:03 +01003398Each platform should register devices and their drivers via the storage
3399abstraction layer. These drivers then need to be initialized by bootloader
3400phases as required in their respective ``blx_platform_setup()`` functions.
3401
3402.. uml:: ../resources/diagrams/plantuml/io_dev_registration.puml
3403
3404The storage abstraction layer provides mechanisms (``io_dev_init()``) to
3405initialize storage devices before IO operations are called.
3406
3407.. uml:: ../resources/diagrams/plantuml/io_dev_init_and_check.puml
3408
3409The basic operations supported by the layer
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003410include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``.
3411Drivers do not have to implement all operations, but each platform must
3412provide at least one driver for a device capable of supporting generic
3413operations such as loading a bootloader image.
3414
3415The current implementation only allows for known images to be loaded by the
3416firmware. These images are specified by using their identifiers, as defined in
Antonio Nino Diaz645feb42019-02-13 14:07:38 +00003417``include/plat/common/common_def.h`` (or a separate header file included from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003418there). The platform layer (``plat_get_image_source()``) then returns a reference
3419to a device and a driver-specific ``spec`` which will be understood by the driver
3420to allow access to the image data.
3421
3422The layer is designed in such a way that is it possible to chain drivers with
3423other drivers. For example, file-system drivers may be implemented on top of
3424physical block devices, both represented by IO devices with corresponding
3425drivers. In such a case, the file-system "binding" with the block device may
3426be deferred until the file-system device is initialised.
3427
3428The abstraction currently depends on structures being statically allocated
3429by the drivers and callers, as the system does not yet provide a means of
3430dynamically allocating memory. This may also have the affect of limiting the
3431amount of open resources per driver.
3432
3433--------------
3434
Soby Mathewf05d93a2022-03-22 16:21:19 +00003435*Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003436
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003437.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
Dan Handley610e7e12018-03-01 18:44:00 +00003438.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003439.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html
Paul Beesley2437ddc2019-02-08 16:43:05 +00003440.. _FreeBSD: https://www.freebsd.org
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003441.. _SCC: http://www.simple-cc.org/
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +01003442.. _DRTM: https://developer.arm.com/documentation/den0113/a