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Paul Beesleyfc9ee362019-03-07 15:47:15 +00001Porting Guide
2=============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Douglas Raillardd7c21b72017-06-28 15:23:03 +01004Introduction
5------------
6
Dan Handley610e7e12018-03-01 18:44:00 +00007Porting Trusted Firmware-A (TF-A) to a new platform involves making some
Douglas Raillardd7c21b72017-06-28 15:23:03 +01008mandatory and optional modifications for both the cold and warm boot paths.
9Modifications consist of:
10
11- Implementing a platform-specific function or variable,
12- Setting up the execution context in a certain way, or
13- Defining certain constants (for example #defines).
14
15The platform-specific functions and variables are declared in
Paul Beesleyf8640672019-04-12 14:19:42 +010016``include/plat/common/platform.h``. The firmware provides a default
Sandrine Bailleux7a53a912023-02-08 13:55:51 +010017implementation of variables and functions to fulfill the optional requirements
18in order to ease the porting effort. Each platform port can use them as is or
19provide their own implementation if the default implementation is inadequate.
20
21 .. note::
22
23 TF-A historically provided default implementations of platform interfaces
24 as *weak* functions. This practice is now discouraged and new platform
25 interfaces as they get introduced in the code base should be *strongly*
26 defined. We intend to convert existing weak functions over time. Until
27 then, you will find references to *weak* functions in this document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010028
Douglas Raillardd7c21b72017-06-28 15:23:03 +010029Some modifications are common to all Boot Loader (BL) stages. Section 2
30discusses these in detail. The subsequent sections discuss the remaining
31modifications for each BL stage in detail.
32
Sandrine Bailleuxdad35612022-11-08 13:36:42 +010033Please refer to the :ref:`Platform Ports Policy` for the policy regarding
34compatibility and deprecation of these porting interfaces.
Soby Mathew02bdbb92018-09-26 11:17:23 +010035
Antonio Nino Diaz645feb42019-02-13 14:07:38 +000036Only Arm development platforms (such as FVP and Juno) may use the
37functions/definitions in ``include/plat/arm/common/`` and the corresponding
38source files in ``plat/arm/common/``. This is done so that there are no
39dependencies between platforms maintained by different people/companies. If you
40want to use any of the functionality present in ``plat/arm`` files, please
41create a pull request that moves the code to ``plat/common`` so that it can be
42discussed.
43
Douglas Raillardd7c21b72017-06-28 15:23:03 +010044Common modifications
45--------------------
46
47This section covers the modifications that should be made by the platform for
48each BL stage to correctly port the firmware stack. They are categorized as
49either mandatory or optional.
50
51Common mandatory modifications
52------------------------------
53
54A platform port must enable the Memory Management Unit (MMU) as well as the
55instruction and data caches for each BL stage. Setting up the translation
56tables is the responsibility of the platform port because memory maps differ
57across platforms. A memory translation library (see ``lib/xlat_tables/``) is
Sandrine Bailleux1861b7a2017-07-20 16:11:01 +010058provided to help in this setup.
59
60Note that although this library supports non-identity mappings, this is intended
61only for re-mapping peripheral physical addresses and allows platforms with high
62I/O addresses to reduce their virtual address space. All other addresses
63corresponding to code and data must currently use an identity mapping.
64
Dan Handley610e7e12018-03-01 18:44:00 +000065Also, the only translation granule size supported in TF-A is 4KB, as various
66parts of the code assume that is the case. It is not possible to switch to
6716 KB or 64 KB granule sizes at the moment.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010068
Dan Handley610e7e12018-03-01 18:44:00 +000069In Arm standard platforms, each BL stage configures the MMU in the
Douglas Raillardd7c21b72017-06-28 15:23:03 +010070platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses
71an identity mapping for all addresses.
72
73If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a
74block of identity mapped secure memory with Device-nGnRE attributes aligned to
75page boundary (4K) for each BL stage. All sections which allocate coherent
Chris Kay33bfc5e2023-02-14 11:30:04 +000076memory are grouped under ``.coherent_ram``. For ex: Bakery locks are placed in a
77section identified by name ``.bakery_lock`` inside ``.coherent_ram`` so that its
Douglas Raillardd7c21b72017-06-28 15:23:03 +010078possible for the firmware to place variables in it using the following C code
79directive:
80
81::
82
Chris Kay33bfc5e2023-02-14 11:30:04 +000083 __section(".bakery_lock")
Douglas Raillardd7c21b72017-06-28 15:23:03 +010084
85Or alternatively the following assembler code directive:
86
87::
88
Chris Kay33bfc5e2023-02-14 11:30:04 +000089 .section .bakery_lock
Douglas Raillardd7c21b72017-06-28 15:23:03 +010090
Chris Kay33bfc5e2023-02-14 11:30:04 +000091The ``.coherent_ram`` section is a sum of all sections like ``.bakery_lock`` which are
Douglas Raillardd7c21b72017-06-28 15:23:03 +010092used to allocate any data structures that are accessed both when a CPU is
93executing with its MMU and caches enabled, and when it's running with its MMU
94and caches disabled. Examples are given below.
95
96The following variables, functions and constants must be defined by the platform
97for the firmware to work correctly.
98
Javier Almansa Sobrino37bf69c2022-04-07 18:26:49 +010099.. _platform_def_mandatory:
100
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100101File : platform_def.h [mandatory]
102~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100103
104Each platform must ensure that a header file of this name is in the system
Antonio Nino Diaz50a4d1a2019-02-01 12:22:22 +0000105include path with the following constants defined. This will require updating
106the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100107
Paul Beesleyf8640672019-04-12 14:19:42 +0100108Platform ports may optionally use the file ``include/plat/common/common_def.h``,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100109which provides typical values for some of the constants below. These values are
110likely to be suitable for all platform ports.
111
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100112- **#define : PLATFORM_LINKER_FORMAT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100113
114 Defines the linker format used by the platform, for example
115 ``elf64-littleaarch64``.
116
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100117- **#define : PLATFORM_LINKER_ARCH**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100118
119 Defines the processor architecture for the linker by the platform, for
120 example ``aarch64``.
121
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100122- **#define : PLATFORM_STACK_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100123
124 Defines the normal stack memory available to each CPU. This constant is used
Paul Beesleyf8640672019-04-12 14:19:42 +0100125 by ``plat/common/aarch64/platform_mp_stack.S`` and
126 ``plat/common/aarch64/platform_up_stack.S``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100127
David Horstmann051fd6d2020-11-12 15:19:04 +0000128- **#define : CACHE_WRITEBACK_GRANULE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100129
Max Yufa0b4e82022-09-08 23:21:21 +0000130 Defines the size in bytes of the largest cache line across all the cache
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100131 levels in the platform.
132
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100133- **#define : FIRMWARE_WELCOME_STR**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100134
135 Defines the character string printed by BL1 upon entry into the ``bl1_main()``
136 function.
137
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100138- **#define : PLATFORM_CORE_COUNT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100139
140 Defines the total number of CPUs implemented by the platform across all
141 clusters in the system.
142
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100143- **#define : PLAT_NUM_PWR_DOMAINS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100144
145 Defines the total number of nodes in the power domain topology
146 tree at all the power domain levels used by the platform.
147 This macro is used by the PSCI implementation to allocate
148 data structures to represent power domain topology.
149
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100150- **#define : PLAT_MAX_PWR_LVL**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100151
152 Defines the maximum power domain level that the power management operations
153 should apply to. More often, but not always, the power domain level
154 corresponds to affinity level. This macro allows the PSCI implementation
155 to know the highest power domain level that it should consider for power
156 management operations in the system that the platform implements. For
157 example, the Base AEM FVP implements two clusters with a configurable
158 number of CPUs and it reports the maximum power domain level as 1.
159
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100160- **#define : PLAT_MAX_OFF_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100161
162 Defines the local power state corresponding to the deepest power down
163 possible at every power domain level in the platform. The local power
164 states for each level may be sparsely allocated between 0 and this value
165 with 0 being reserved for the RUN state. The PSCI implementation uses this
166 value to initialize the local power states of the power domain nodes and
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100167 to specify the requested power state for a PSCI_CPU_OFF call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100168
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100169- **#define : PLAT_MAX_RET_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100170
171 Defines the local power state corresponding to the deepest retention state
172 possible at every power domain level in the platform. This macro should be
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100173 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100174 PSCI implementation to distinguish between retention and power down local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100175 power states within PSCI_CPU_SUSPEND call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100176
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100177- **#define : PLAT_MAX_PWR_LVL_STATES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100178
179 Defines the maximum number of local power states per power domain level
180 that the platform supports. The default value of this macro is 2 since
181 most platforms just support a maximum of two local power states at each
182 power domain level (power-down and retention). If the platform needs to
183 account for more local power states, then it must redefine this macro.
184
185 Currently, this macro is used by the Generic PSCI implementation to size
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100186 the array used for PSCI_STAT_COUNT/RESIDENCY accounting.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100187
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100188- **#define : BL1_RO_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100189
190 Defines the base address in secure ROM where BL1 originally lives. Must be
191 aligned on a page-size boundary.
192
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100193- **#define : BL1_RO_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100194
195 Defines the maximum address in secure ROM that BL1's actual content (i.e.
196 excluding any data section allocated at runtime) can occupy.
197
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100198- **#define : BL1_RW_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100199
200 Defines the base address in secure RAM where BL1's read-write data will live
201 at runtime. Must be aligned on a page-size boundary.
202
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100203- **#define : BL1_RW_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100204
205 Defines the maximum address in secure RAM that BL1's read-write data can
206 occupy at runtime.
207
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100208- **#define : BL2_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100209
210 Defines the base address in secure RAM where BL1 loads the BL2 binary image.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000211 Must be aligned on a page-size boundary. This constant is not applicable
212 when BL2_IN_XIP_MEM is set to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100213
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100214- **#define : BL2_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100215
216 Defines the maximum address in secure RAM that the BL2 image can occupy.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000217 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'.
218
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100219- **#define : BL2_RO_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000220
221 Defines the base address in secure XIP memory where BL2 RO section originally
222 lives. Must be aligned on a page-size boundary. This constant is only needed
223 when BL2_IN_XIP_MEM is set to '1'.
224
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100225- **#define : BL2_RO_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000226
227 Defines the maximum address in secure XIP memory that BL2's actual content
228 (i.e. excluding any data section allocated at runtime) can occupy. This
229 constant is only needed when BL2_IN_XIP_MEM is set to '1'.
230
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100231- **#define : BL2_RW_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000232
233 Defines the base address in secure RAM where BL2's read-write data will live
234 at runtime. Must be aligned on a page-size boundary. This constant is only
235 needed when BL2_IN_XIP_MEM is set to '1'.
236
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100237- **#define : BL2_RW_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000238
239 Defines the maximum address in secure RAM that BL2's read-write data can
240 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set
241 to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100242
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100243- **#define : BL31_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100244
245 Defines the base address in secure RAM where BL2 loads the BL31 binary
246 image. Must be aligned on a page-size boundary.
247
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100248- **#define : BL31_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100249
250 Defines the maximum address in secure RAM that the BL31 image can occupy.
251
Tamas Ban1d3354e2022-09-16 14:09:30 +0200252- **#define : PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE**
253
254 Defines the maximum message size between AP and RSS. Need to define if
255 platform supports RSS.
256
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100257For every image, the platform must define individual identifiers that will be
258used by BL1 or BL2 to load the corresponding image into memory from non-volatile
259storage. For the sake of performance, integer numbers will be used as
260identifiers. The platform will use those identifiers to return the relevant
261information about the image to be loaded (file handler, load address,
262authentication information, etc.). The following image identifiers are
263mandatory:
264
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100265- **#define : BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100266
267 BL2 image identifier, used by BL1 to load BL2.
268
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100269- **#define : BL31_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100270
271 BL31 image identifier, used by BL2 to load BL31.
272
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100273- **#define : BL33_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100274
275 BL33 image identifier, used by BL2 to load BL33.
276
277If Trusted Board Boot is enabled, the following certificate identifiers must
278also be defined:
279
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100280- **#define : TRUSTED_BOOT_FW_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100281
282 BL2 content certificate identifier, used by BL1 to load the BL2 content
283 certificate.
284
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100285- **#define : TRUSTED_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100286
287 Trusted key certificate identifier, used by BL2 to load the trusted key
288 certificate.
289
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100290- **#define : SOC_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100291
292 BL31 key certificate identifier, used by BL2 to load the BL31 key
293 certificate.
294
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100295- **#define : SOC_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100296
297 BL31 content certificate identifier, used by BL2 to load the BL31 content
298 certificate.
299
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100300- **#define : NON_TRUSTED_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100301
302 BL33 key certificate identifier, used by BL2 to load the BL33 key
303 certificate.
304
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100305- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100306
307 BL33 content certificate identifier, used by BL2 to load the BL33 content
308 certificate.
309
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100310- **#define : FWU_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100311
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100312 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100313 FWU content certificate.
314
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100315- **#define : PLAT_CRYPTOCELL_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100316
Dan Handley610e7e12018-03-01 18:44:00 +0000317 This defines the base address of Arm® TrustZone® CryptoCell and must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100318 defined if CryptoCell crypto driver is used for Trusted Board Boot. For
Dan Handley610e7e12018-03-01 18:44:00 +0000319 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100320 set.
321
322If the AP Firmware Updater Configuration image, BL2U is used, the following
323must also be defined:
324
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100325- **#define : BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100326
327 Defines the base address in secure memory where BL1 copies the BL2U binary
328 image. Must be aligned on a page-size boundary.
329
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100330- **#define : BL2U_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100331
332 Defines the maximum address in secure memory that the BL2U image can occupy.
333
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100334- **#define : BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100335
336 BL2U image identifier, used by BL1 to fetch an image descriptor
337 corresponding to BL2U.
338
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100339If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100340must also be defined:
341
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100342- **#define : SCP_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100343
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100344 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor
345 corresponding to SCP_BL2U.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000346
347 .. note::
348 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100349
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100350If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100351also be defined:
352
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100353- **#define : NS_BL1U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100354
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100355 Defines the base address in non-secure ROM where NS_BL1U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100356 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000357
358 .. note::
359 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100360
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100361- **#define : NS_BL1U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100362
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100363 NS_BL1U image identifier, used by BL1 to fetch an image descriptor
364 corresponding to NS_BL1U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100365
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100366If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100367be defined:
368
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100369- **#define : NS_BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100370
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100371 Defines the base address in non-secure memory where NS_BL2U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100372 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000373
374 .. note::
375 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100376
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100377- **#define : NS_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100378
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100379 NS_BL2U image identifier, used by BL1 to fetch an image descriptor
380 corresponding to NS_BL2U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100381
382For the the Firmware update capability of TRUSTED BOARD BOOT, the following
383macros may also be defined:
384
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100385- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100386
387 Total number of images that can be loaded simultaneously. If the platform
388 doesn't specify any value, it defaults to 10.
389
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100390If a SCP_BL2 image is supported by the platform, the following constants must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100391also be defined:
392
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100393- **#define : SCP_BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100394
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100395 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000396 from platform storage before being transferred to the SCP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100397
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100398- **#define : SCP_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100399
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100400 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100401 certificate (mandatory when Trusted Board Boot is enabled).
402
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100403- **#define : SCP_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100404
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100405 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100406 content certificate (mandatory when Trusted Board Boot is enabled).
407
408If a BL32 image is supported by the platform, the following constants must
409also be defined:
410
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100411- **#define : BL32_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100412
413 BL32 image identifier, used by BL2 to load BL32.
414
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100415- **#define : TRUSTED_OS_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100416
417 BL32 key certificate identifier, used by BL2 to load the BL32 key
418 certificate (mandatory when Trusted Board Boot is enabled).
419
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100420- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100421
422 BL32 content certificate identifier, used by BL2 to load the BL32 content
423 certificate (mandatory when Trusted Board Boot is enabled).
424
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100425- **#define : BL32_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100426
427 Defines the base address in secure memory where BL2 loads the BL32 binary
428 image. Must be aligned on a page-size boundary.
429
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100430- **#define : BL32_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100431
432 Defines the maximum address that the BL32 image can occupy.
433
434If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the
435platform, the following constants must also be defined:
436
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100437- **#define : TSP_SEC_MEM_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100438
439 Defines the base address of the secure memory used by the TSP image on the
440 platform. This must be at the same address or below ``BL32_BASE``.
441
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100442- **#define : TSP_SEC_MEM_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100443
444 Defines the size of the secure memory used by the BL32 image on the
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000445 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully
446 accommodate the memory required by the BL32 image, defined by ``BL32_BASE``
447 and ``BL32_LIMIT``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100448
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100449- **#define : TSP_IRQ_SEC_PHY_TIMER**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100450
451 Defines the ID of the secure physical generic timer interrupt used by the
452 TSP's interrupt handling code.
453
454If the platform port uses the translation table library code, the following
455constants must also be defined:
456
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100457- **#define : PLAT_XLAT_TABLES_DYNAMIC**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100458
459 Optional flag that can be set per-image to enable the dynamic allocation of
460 regions even when the MMU is enabled. If not defined, only static
461 functionality will be available, if defined and set to 1 it will also
462 include the dynamic functionality.
463
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100464- **#define : MAX_XLAT_TABLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100465
466 Defines the maximum number of translation tables that are allocated by the
467 translation table library code. To minimize the amount of runtime memory
468 used, choose the smallest value needed to map the required virtual addresses
469 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL
470 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions
471 as well.
472
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100473- **#define : MAX_MMAP_REGIONS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100474
475 Defines the maximum number of regions that are allocated by the translation
476 table library code. A region consists of physical base address, virtual base
477 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
478 defined in the ``mmap_region_t`` structure. The platform defines the regions
479 that should be mapped. Then, the translation table library will create the
480 corresponding tables and descriptors at runtime. To minimize the amount of
481 runtime memory used, choose the smallest value needed to register the
482 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is
483 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate
484 the dynamic regions as well.
485
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100486- **#define : PLAT_VIRT_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100487
488 Defines the total size of the virtual address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000489 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100490
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100491- **#define : PLAT_PHY_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100492
493 Defines the total size of the physical address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000494 for a 32 bit physical address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100495
496If the platform port uses the IO storage framework, the following constants
497must also be defined:
498
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100499- **#define : MAX_IO_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100500
501 Defines the maximum number of registered IO devices. Attempting to register
502 more devices than this value using ``io_register_device()`` will fail with
503 -ENOMEM.
504
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100505- **#define : MAX_IO_HANDLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100506
507 Defines the maximum number of open IO handles. Attempting to open more IO
508 entities than this value using ``io_open()`` will fail with -ENOMEM.
509
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100510- **#define : MAX_IO_BLOCK_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100511
512 Defines the maximum number of registered IO block devices. Attempting to
513 register more devices this value using ``io_dev_open()`` will fail
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100514 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100515 With this macro, multiple block devices could be supported at the same
516 time.
517
518If the platform needs to allocate data within the per-cpu data framework in
519BL31, it should define the following macro. Currently this is only required if
520the platform decides not to use the coherent memory section by undefining the
521``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
522required memory within the the per-cpu data to minimize wastage.
523
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100524- **#define : PLAT_PCPU_DATA_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100525
526 Defines the memory (in bytes) to be reserved within the per-cpu data
527 structure for use by the platform layer.
528
529The following constants are optional. They should be defined when the platform
Dan Handley610e7e12018-03-01 18:44:00 +0000530memory layout implies some image overlaying like in Arm standard platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100531
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100532- **#define : BL31_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100533
534 Defines the maximum address in secure RAM that the BL31's progbits sections
535 can occupy.
536
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100537- **#define : TSP_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100538
539 Defines the maximum address that the TSP's progbits sections can occupy.
540
541If the platform port uses the PL061 GPIO driver, the following constant may
542optionally be defined:
543
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100544- **PLAT_PL061_MAX_GPIOS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100545 Maximum number of GPIOs required by the platform. This allows control how
546 much memory is allocated for PL061 GPIO controllers. The default value is
547
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100548 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100549
550If the platform port uses the partition driver, the following constant may
551optionally be defined:
552
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100553- **PLAT_PARTITION_MAX_ENTRIES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100554 Maximum number of partition entries required by the platform. This allows
555 control how much memory is allocated for partition entries. The default
556 value is 128.
Paul Beesleyf8640672019-04-12 14:19:42 +0100557 For example, define the build flag in ``platform.mk``:
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100558 PLAT_PARTITION_MAX_ENTRIES := 12
559 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100560
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800561- **PLAT_PARTITION_BLOCK_SIZE**
562 The size of partition block. It could be either 512 bytes or 4096 bytes.
563 The default value is 512.
Paul Beesleyf2ec7142019-10-04 16:17:46 +0000564 For example, define the build flag in ``platform.mk``:
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800565 PLAT_PARTITION_BLOCK_SIZE := 4096
566 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE))
567
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100568The following constant is optional. It should be defined to override the default
569behaviour of the ``assert()`` function (for example, to save memory).
570
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100571- **PLAT_LOG_LEVEL_ASSERT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100572 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``,
573 ``assert()`` prints the name of the file, the line number and the asserted
574 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file
575 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it
576 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't
577 defined, it defaults to ``LOG_LEVEL``.
578
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +0100579If the platform port uses the DRTM feature, the following constants must be
580defined:
581
582- **#define : PLAT_DRTM_EVENT_LOG_MAX_SIZE**
583
584 Maximum Event Log size used by the platform. Platform can decide the maximum
585 size of the Event Log buffer, depending upon the highest hash algorithm
586 chosen and the number of components selected to measure during the DRTM
587 execution flow.
588
589- **#define : PLAT_DRTM_MMAP_ENTRIES**
590
591 Number of the MMAP entries used by the DRTM implementation to calculate the
592 size of address map region of the platform.
593
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100594File : plat_macros.S [mandatory]
595~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100596
597Each platform must ensure a file of this name is in the system include path with
Dan Handley610e7e12018-03-01 18:44:00 +0000598the following macro defined. In the Arm development platforms, this file is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100599found in ``plat/arm/board/<plat_name>/include/plat_macros.S``.
600
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100601- **Macro : plat_crash_print_regs**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100602
603 This macro allows the crash reporting routine to print relevant platform
604 registers in case of an unhandled exception in BL31. This aids in debugging
605 and this macro can be defined to be empty in case register reporting is not
606 desired.
607
608 For instance, GIC or interconnect registers may be helpful for
609 troubleshooting.
610
611Handling Reset
612--------------
613
614BL1 by default implements the reset vector where execution starts from a cold
615or warm boot. BL31 can be optionally set as a reset vector using the
616``RESET_TO_BL31`` make variable.
617
618For each CPU, the reset vector code is responsible for the following tasks:
619
620#. Distinguishing between a cold boot and a warm boot.
621
622#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
623 the CPU is placed in a platform-specific state until the primary CPU
624 performs the necessary steps to remove it from this state.
625
626#. In the case of a warm boot, ensuring that the CPU jumps to a platform-
627 specific address in the BL31 image in the same processor mode as it was
628 when released from reset.
629
630The following functions need to be implemented by the platform port to enable
631reset vector code to perform the above tasks.
632
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100633Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0]
634~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100635
636::
637
638 Argument : void
639 Return : uintptr_t
640
641This function is called with the MMU and caches disabled
642(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for
643distinguishing between a warm and cold reset for the current CPU using
644platform-specific means. If it's a warm reset, then it returns the warm
645reset entrypoint point provided to ``plat_setup_psci_ops()`` during
646BL31 initialization. If it's a cold reset then this function must return zero.
647
648This function does not follow the Procedure Call Standard used by the
Dan Handley610e7e12018-03-01 18:44:00 +0000649Application Binary Interface for the Arm 64-bit architecture. The caller should
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100650not assume that callee saved registers are preserved across a call to this
651function.
652
653This function fulfills requirement 1 and 3 listed above.
654
655Note that for platforms that support programming the reset address, it is
656expected that a CPU will start executing code directly at the right address,
657both on a cold and warm reset. In this case, there is no need to identify the
658type of reset nor to query the warm reset entrypoint. Therefore, implementing
659this function is not required on such platforms.
660
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100661Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
662~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100663
664::
665
666 Argument : void
667
668This function is called with the MMU and data caches disabled. It is responsible
669for placing the executing secondary CPU in a platform-specific state until the
670primary CPU performs the necessary actions to bring it out of that state and
671allow entry into the OS. This function must not return.
672
Dan Handley610e7e12018-03-01 18:44:00 +0000673In the Arm FVP port, when using the normal boot flow, each secondary CPU powers
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100674itself off. The primary CPU is responsible for powering up the secondary CPUs
675when normal world software requires them. When booting an EL3 payload instead,
676they stay powered on and are put in a holding pen until their mailbox gets
677populated.
678
679This function fulfills requirement 2 above.
680
681Note that for platforms that can't release secondary CPUs out of reset, only the
682primary CPU will execute the cold boot code. Therefore, implementing this
683function is not required on such platforms.
684
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100685Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
686~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100687
688::
689
690 Argument : void
691 Return : unsigned int
692
693This function identifies whether the current CPU is the primary CPU or a
694secondary CPU. A return value of zero indicates that the CPU is not the
695primary CPU, while a non-zero return value indicates that the CPU is the
696primary CPU.
697
698Note that for platforms that can't release secondary CPUs out of reset, only the
699primary CPU will execute the cold boot code. Therefore, there is no need to
700distinguish between primary and secondary CPUs and implementing this function is
701not required.
702
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100703Function : platform_mem_init() [mandatory]
704~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100705
706::
707
708 Argument : void
709 Return : void
710
711This function is called before any access to data is made by the firmware, in
712order to carry out any essential memory initialization.
713
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100714Function: plat_get_rotpk_info()
715~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100716
717::
718
719 Argument : void *, void **, unsigned int *, unsigned int *
720 Return : int
721
722This function is mandatory when Trusted Board Boot is enabled. It returns a
723pointer to the ROTPK stored in the platform (or a hash of it) and its length.
724The ROTPK must be encoded in DER format according to the following ASN.1
725structure:
726
727::
728
729 AlgorithmIdentifier ::= SEQUENCE {
730 algorithm OBJECT IDENTIFIER,
731 parameters ANY DEFINED BY algorithm OPTIONAL
732 }
733
734 SubjectPublicKeyInfo ::= SEQUENCE {
735 algorithm AlgorithmIdentifier,
736 subjectPublicKey BIT STRING
737 }
738
739In case the function returns a hash of the key:
740
741::
742
743 DigestInfo ::= SEQUENCE {
744 digestAlgorithm AlgorithmIdentifier,
745 digest OCTET STRING
746 }
747
748The function returns 0 on success. Any other value is treated as error by the
749Trusted Board Boot. The function also reports extra information related
750to the ROTPK in the flags parameter:
751
752::
753
754 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a
755 hash.
756 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK
757 verification while the platform ROTPK is not deployed.
758 When this flag is set, the function does not need to
759 return a platform ROTPK, and the authentication
760 framework uses the ROTPK in the certificate without
761 verifying it against the platform value. This flag
762 must not be used in a deployed production environment.
763
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100764Function: plat_get_nv_ctr()
765~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100766
767::
768
769 Argument : void *, unsigned int *
770 Return : int
771
772This function is mandatory when Trusted Board Boot is enabled. It returns the
773non-volatile counter value stored in the platform in the second argument. The
774cookie in the first argument may be used to select the counter in case the
775platform provides more than one (for example, on platforms that use the default
776TBBR CoT, the cookie will correspond to the OID values defined in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100777TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100778
779The function returns 0 on success. Any other value means the counter value could
780not be retrieved from the platform.
781
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100782Function: plat_set_nv_ctr()
783~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100784
785::
786
787 Argument : void *, unsigned int
788 Return : int
789
790This function is mandatory when Trusted Board Boot is enabled. It sets a new
791counter value in the platform. The cookie in the first argument may be used to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100792select the counter (as explained in plat_get_nv_ctr()). The second argument is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100793the updated counter value to be written to the NV counter.
794
795The function returns 0 on success. Any other value means the counter value could
796not be updated.
797
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100798Function: plat_set_nv_ctr2()
799~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100800
801::
802
803 Argument : void *, const auth_img_desc_t *, unsigned int
804 Return : int
805
806This function is optional when Trusted Board Boot is enabled. If this
807interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The
808first argument passed is a cookie and is typically used to
809differentiate between a Non Trusted NV Counter and a Trusted NV
810Counter. The second argument is a pointer to an authentication image
811descriptor and may be used to decide if the counter is allowed to be
812updated or not. The third argument is the updated counter value to
813be written to the NV counter.
814
815The function returns 0 on success. Any other value means the counter value
816either could not be updated or the authentication image descriptor indicates
817that it is not allowed to be updated.
818
Nicolas Toromanoff7f95ac82020-11-09 12:14:52 +0100819Function: plat_convert_pk()
820~~~~~~~~~~~~~~~~~~~~~~~~~~~
821
822::
823
824 Argument : void *, unsigned int, void **, unsigned int *
825 Return : int
826
827This function is optional when Trusted Board Boot is enabled, and only
828used if the platform saves a hash of the ROTPK.
829First argument is the Distinguished Encoding Rules (DER) ROTPK.
830Second argument is its size.
831Third argument is used to return a pointer to a buffer, which hash should
832be the one saved in OTP.
833Fourth argument is a pointer to return its size.
834
835Most platforms save the hash of the ROTPK, but some may save slightly different
836information - e.g the hash of the ROTPK plus some related information.
837Defining this function allows to transform the ROTPK used to verify
838the signature to the buffer (a platform specific public key) which
839hash is saved in OTP.
840
841The default implementation copies the input key and length to the output without
842modification.
843
844The function returns 0 on success. Any other value means the expected
845public key buffer cannot be extracted.
846
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +0100847Dynamic Root of Trust for Measurement support (in BL31)
848-------------------------------------------------------
849
850The functions mentioned in this section are mandatory, when platform enables
851DRTM_SUPPORT build flag.
852
853Function : plat_get_addr_mmap()
854~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
855
856::
857
858 Argument : void
859 Return : const mmap_region_t *
860
861This function is used to return the address of the platform *address-map* table,
862which describes the regions of normal memory, memory mapped I/O
863and non-volatile memory.
864
865Function : plat_has_non_host_platforms()
866~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
867
868::
869
870 Argument : void
871 Return : bool
872
873This function returns *true* if the platform has any trusted devices capable of
874DMA, otherwise returns *false*.
875
876Function : plat_has_unmanaged_dma_peripherals()
877~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
878
879::
880
881 Argument : void
882 Return : bool
883
884This function returns *true* if platform uses peripherals whose DMA is not
885managed by an SMMU, otherwise returns *false*.
886
887Note -
888If the platform has peripherals that are not managed by the SMMU, then the
889platform should investigate such peripherals to determine whether they can
890be trusted, and such peripherals should be moved under "Non-host platforms"
891if they can be trusted.
892
893Function : plat_get_total_num_smmus()
894~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
895
896::
897
898 Argument : void
899 Return : unsigned int
900
901This function returns the total number of SMMUs in the platform.
902
903Function : plat_enumerate_smmus()
904~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
905::
906
907
908 Argument : void
909 Return : const uintptr_t *, size_t
910
911This function returns an array of SMMU addresses and the actual number of SMMUs
912reported by the platform.
913
914Function : plat_drtm_get_dma_prot_features()
915~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
916
917::
918
919 Argument : void
920 Return : const plat_drtm_dma_prot_features_t*
921
922This function returns the address of plat_drtm_dma_prot_features_t structure
923containing the maximum number of protected regions and bitmap with the types
924of DMA protection supported by the platform.
925For more details see section 3.3 Table 6 of `DRTM`_ specification.
926
927Function : plat_drtm_dma_prot_get_max_table_bytes()
928~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
929
930::
931
932 Argument : void
933 Return : uint64_t
934
935This function returns the maximum size of DMA protected regions table in
936bytes.
937
938Function : plat_drtm_get_tpm_features()
939~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
940
941::
942
943 Argument : void
944 Return : const plat_drtm_tpm_features_t*
945
946This function returns the address of *plat_drtm_tpm_features_t* structure
947containing PCR usage schema, TPM-based hash, and firmware hash algorithm
948supported by the platform.
949
950Function : plat_drtm_get_min_size_normal_world_dce()
951~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
952
953::
954
955 Argument : void
956 Return : uint64_t
957
958This function returns the size normal-world DCE of the platform.
959
960Function : plat_drtm_get_imp_def_dlme_region_size()
961~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
962
963::
964
965 Argument : void
966 Return : uint64_t
967
968This function returns the size of implementation defined DLME region
969of the platform.
970
971Function : plat_drtm_get_tcb_hash_table_size()
972~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
973
974::
975
976 Argument : void
977 Return : uint64_t
978
979This function returns the size of TCB hash table of the platform.
980
981Function : plat_drtm_get_tcb_hash_features()
982~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
983
984::
985
986 Argument : void
987 Return : uint64_t
988
989This function returns the Maximum number of TCB hashes recorded by the
990platform.
991For more details see section 3.3 Table 6 of `DRTM`_ specification.
992
993Function : plat_drtm_validate_ns_region()
994~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
995
996::
997
998 Argument : uintptr_t, uintptr_t
999 Return : int
1000
1001This function validates that given region is within the Non-Secure region
1002of DRAM. This function takes a region start address and size an input
1003arguments, and returns 0 on success and -1 on failure.
1004
1005Function : plat_set_drtm_error()
1006~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1007
1008::
1009
1010 Argument : uint64_t
1011 Return : int
1012
1013This function writes a 64 bit error code received as input into
1014non-volatile storage and returns 0 on success and -1 on failure.
1015
1016Function : plat_get_drtm_error()
1017~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1018
1019::
1020
1021 Argument : uint64_t*
1022 Return : int
1023
1024This function reads a 64 bit error code from the non-volatile storage
1025into the received address, and returns 0 on success and -1 on failure.
1026
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001027Common mandatory function modifications
1028---------------------------------------
1029
1030The following functions are mandatory functions which need to be implemented
1031by the platform port.
1032
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001033Function : plat_my_core_pos()
1034~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001035
1036::
1037
1038 Argument : void
1039 Return : unsigned int
1040
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001041This function returns the index of the calling CPU which is used as a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001042CPU-specific linear index into blocks of memory (for example while allocating
1043per-CPU stacks). This function will be invoked very early in the
1044initialization sequence which mandates that this function should be
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001045implemented in assembly and should not rely on the availability of a C
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001046runtime environment. This function can clobber x0 - x8 and must preserve
1047x9 - x29.
1048
1049This function plays a crucial role in the power domain topology framework in
Paul Beesleyf8640672019-04-12 14:19:42 +01001050PSCI and details of this can be found in
1051:ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001052
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001053Function : plat_core_pos_by_mpidr()
1054~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001055
1056::
1057
1058 Argument : u_register_t
1059 Return : int
1060
1061This function validates the ``MPIDR`` of a CPU and converts it to an index,
1062which can be used as a CPU-specific linear index into blocks of memory. In
1063case the ``MPIDR`` is invalid, this function returns -1. This function will only
1064be invoked by BL31 after the power domain topology is initialized and can
Dan Handley610e7e12018-03-01 18:44:00 +00001065utilize the C runtime environment. For further details about how TF-A
1066represents the power domain topology and how this relates to the linear CPU
Paul Beesleyf8640672019-04-12 14:19:42 +01001067index, please refer :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001068
Ambroise Vincentd207f562019-04-10 12:50:27 +01001069Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1]
1070~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1071
1072::
1073
1074 Arguments : void **heap_addr, size_t *heap_size
1075 Return : int
1076
1077This function is invoked during Mbed TLS library initialisation to get a heap,
1078by means of a starting address and a size. This heap will then be used
1079internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS
1080must be able to provide a heap to it.
1081
1082A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in
1083which a heap is statically reserved during compile time inside every image
1084(i.e. every BL stage) that utilises Mbed TLS. In this default implementation,
1085the function simply returns the address and size of this "pre-allocated" heap.
1086For a platform to use this default implementation, only a call to the helper
1087from inside plat_get_mbedtls_heap() body is enough and nothing else is needed.
1088
1089However, by writting their own implementation, platforms have the potential to
1090optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is
1091shared between BL1 and BL2 stages and, thus, the necessary space is not reserved
1092twice.
1093
1094On success the function should return 0 and a negative error code otherwise.
1095
Sumit Gargc0c369c2019-11-15 18:47:53 +05301096Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1]
1097~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1098
1099::
1100
1101 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key,
1102 size_t *key_len, unsigned int *flags, const uint8_t *img_id,
1103 size_t img_id_len
1104 Return : int
1105
1106This function provides a symmetric key (either SSK or BSSK depending on
1107fw_enc_status) which is invoked during runtime decryption of encrypted
1108firmware images. `plat/common/plat_bl_common.c` provides a dummy weak
1109implementation for testing purposes which must be overridden by the platform
1110trying to implement a real world firmware encryption use-case.
1111
1112It also allows the platform to pass symmetric key identifier rather than
1113actual symmetric key which is useful in cases where the crypto backend provides
1114secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER``
1115flag must be set in ``flags``.
1116
1117In addition to above a platform may also choose to provide an image specific
1118symmetric key/identifier using img_id.
1119
1120On success the function should return 0 and a negative error code otherwise.
1121
Manish Pandey34a305e2021-10-21 21:53:49 +01001122Note that this API depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +05301123
Manish V Badarkheda87af12021-06-20 21:14:46 +01001124Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1]
1125~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1126
1127::
1128
Sughosh Ganuf40154f2021-11-17 17:08:10 +05301129 Argument : const struct fwu_metadata *metadata
Manish V Badarkheda87af12021-06-20 21:14:46 +01001130 Return : void
1131
1132This function is mandatory when PSA_FWU_SUPPORT is enabled.
1133It provides a means to retrieve image specification (offset in
1134non-volatile storage and length) of active/updated images using the passed
1135FWU metadata, and update I/O policies of active/updated images using retrieved
1136image specification information.
1137Further I/O layer operations such as I/O open, I/O read, etc. on these
1138images rely on this function call.
1139
1140In Arm platforms, this function is used to set an I/O policy of the FIP image,
1141container of all active/updated secure and non-secure images.
1142
1143Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1]
1144~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1145
1146::
1147
1148 Argument : unsigned int image_id, uintptr_t *dev_handle,
1149 uintptr_t *image_spec
1150 Return : int
1151
1152This function is mandatory when PSA_FWU_SUPPORT is enabled. It is
1153responsible for setting up the platform I/O policy of the requested metadata
1154image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will
1155be used to load this image from the platform's non-volatile storage.
1156
1157FWU metadata can not be always stored as a raw image in non-volatile storage
1158to define its image specification (offset in non-volatile storage and length)
1159statically in I/O policy.
1160For example, the FWU metadata image is stored as a partition inside the GUID
1161partition table image. Its specification is defined in the partition table
1162that needs to be parsed dynamically.
1163This function provides a means to retrieve such dynamic information to set
1164the I/O policy of the FWU metadata image.
1165Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata
1166image relies on this function call.
1167
1168It returns '0' on success, otherwise a negative error value on error.
1169Alongside, returns device handle and image specification from the I/O policy
1170of the requested FWU metadata image.
1171
Sughosh Ganu4e336a62021-12-01 15:53:32 +05301172Function : plat_fwu_get_boot_idx() [when PSA_FWU_SUPPORT == 1]
1173~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1174
1175::
1176
1177 Argument : void
1178 Return : uint32_t
1179
1180This function is mandatory when PSA_FWU_SUPPORT is enabled. It provides the
1181means to retrieve the boot index value from the platform. The boot index is the
1182bank from which the platform has booted the firmware images.
1183
1184By default, the platform will read the metadata structure and try to boot from
1185the active bank. If the platform fails to boot from the active bank due to
1186reasons like an Authentication failure, or on crossing a set number of watchdog
1187resets while booting from the active bank, the platform can then switch to boot
1188from a different bank. This function then returns the bank that the platform
1189should boot its images from.
1190
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001191Common optional modifications
1192-----------------------------
1193
1194The following are helper functions implemented by the firmware that perform
1195common platform-specific tasks. A platform may choose to override these
1196definitions.
1197
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001198Function : plat_set_my_stack()
1199~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001200
1201::
1202
1203 Argument : void
1204 Return : void
1205
1206This function sets the current stack pointer to the normal memory stack that
1207has been allocated for the current CPU. For BL images that only require a
1208stack for the primary CPU, the UP version of the function is used. The size
1209of the stack allocated to each CPU is specified by the platform defined
1210constant ``PLATFORM_STACK_SIZE``.
1211
1212Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +01001213provided in ``plat/common/aarch64/platform_up_stack.S`` and
1214``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001215
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001216Function : plat_get_my_stack()
1217~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001218
1219::
1220
1221 Argument : void
1222 Return : uintptr_t
1223
1224This function returns the base address of the normal memory stack that
1225has been allocated for the current CPU. For BL images that only require a
1226stack for the primary CPU, the UP version of the function is used. The size
1227of the stack allocated to each CPU is specified by the platform defined
1228constant ``PLATFORM_STACK_SIZE``.
1229
1230Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +01001231provided in ``plat/common/aarch64/platform_up_stack.S`` and
1232``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001233
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001234Function : plat_report_exception()
1235~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001236
1237::
1238
1239 Argument : unsigned int
1240 Return : void
1241
1242A platform may need to report various information about its status when an
1243exception is taken, for example the current exception level, the CPU security
1244state (secure/non-secure), the exception type, and so on. This function is
1245called in the following circumstances:
1246
1247- In BL1, whenever an exception is taken.
1248- In BL2, whenever an exception is taken.
1249
1250The default implementation doesn't do anything, to avoid making assumptions
1251about the way the platform displays its status information.
1252
1253For AArch64, this function receives the exception type as its argument.
1254Possible values for exceptions types are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +01001255``include/common/bl_common.h`` header file. Note that these constants are not
Dan Handley610e7e12018-03-01 18:44:00 +00001256related to any architectural exception code; they are just a TF-A convention.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001257
1258For AArch32, this function receives the exception mode as its argument.
1259Possible values for exception modes are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +01001260``include/lib/aarch32/arch.h`` header file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001261
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001262Function : plat_reset_handler()
1263~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001264
1265::
1266
1267 Argument : void
1268 Return : void
1269
1270A platform may need to do additional initialization after reset. This function
Paul Beesleyf2ec7142019-10-04 16:17:46 +00001271allows the platform to do the platform specific initializations. Platform
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001272specific errata workarounds could also be implemented here. The API should
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001273preserve the values of callee saved registers x19 to x29.
1274
1275The default implementation doesn't do anything. If a platform needs to override
Paul Beesleyf8640672019-04-12 14:19:42 +01001276the default implementation, refer to the :ref:`Firmware Design` for general
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001277guidelines.
1278
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001279Function : plat_disable_acp()
1280~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001281
1282::
1283
1284 Argument : void
1285 Return : void
1286
John Tsichritzis6dda9762018-07-23 09:18:04 +01001287This API allows a platform to disable the Accelerator Coherency Port (if
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001288present) during a cluster power down sequence. The default weak implementation
John Tsichritzis6dda9762018-07-23 09:18:04 +01001289doesn't do anything. Since this API is called during the power down sequence,
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001290it has restrictions for stack usage and it can use the registers x0 - x17 as
1291scratch registers. It should preserve the value in x18 register as it is used
1292by the caller to store the return address.
1293
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001294Function : plat_error_handler()
1295~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001296
1297::
1298
1299 Argument : int
1300 Return : void
1301
1302This API is called when the generic code encounters an error situation from
1303which it cannot continue. It allows the platform to perform error reporting or
1304recovery actions (for example, reset the system). This function must not return.
1305
1306The parameter indicates the type of error using standard codes from ``errno.h``.
1307Possible errors reported by the generic code are:
1308
1309- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted
1310 Board Boot is enabled)
1311- ``-ENOENT``: the requested image or certificate could not be found or an IO
1312 error was detected
Dan Handley610e7e12018-03-01 18:44:00 +00001313- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this
1314 error is usually an indication of an incorrect array size
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001315
1316The default implementation simply spins.
1317
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001318Function : plat_panic_handler()
1319~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001320
1321::
1322
1323 Argument : void
1324 Return : void
1325
1326This API is called when the generic code encounters an unexpected error
1327situation from which it cannot recover. This function must not return,
1328and must be implemented in assembly because it may be called before the C
1329environment is initialized.
1330
Paul Beesleyba3ed402019-03-13 16:20:44 +00001331.. note::
1332 The address from where it was called is stored in x30 (Link Register).
1333 The default implementation simply spins.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001334
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +01001335Function : plat_system_reset()
1336~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1337
1338::
1339
1340 Argument : void
1341 Return : void
1342
1343This function is used by the platform to resets the system. It can be used
1344in any specific use-case where system needs to be resetted. For example,
1345in case of DRTM implementation this function reset the system after
1346writing the DRTM error code in the non-volatile storage. This function
1347never returns. Failure in reset results in panic.
1348
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001349Function : plat_get_bl_image_load_info()
1350~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001351
1352::
1353
1354 Argument : void
1355 Return : bl_load_info_t *
1356
1357This function returns pointer to the list of images that the platform has
Soby Mathew97b1bff2018-09-27 16:46:41 +01001358populated to load. This function is invoked in BL2 to load the
1359BL3xx images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001360
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001361Function : plat_get_next_bl_params()
1362~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001363
1364::
1365
1366 Argument : void
1367 Return : bl_params_t *
1368
1369This function returns a pointer to the shared memory that the platform has
Dan Handley610e7e12018-03-01 18:44:00 +00001370kept aside to pass TF-A related information that next BL image needs. This
Soby Mathew97b1bff2018-09-27 16:46:41 +01001371function is invoked in BL2 to pass this information to the next BL
1372image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001373
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001374Function : plat_get_stack_protector_canary()
1375~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001376
1377::
1378
1379 Argument : void
1380 Return : u_register_t
1381
1382This function returns a random value that is used to initialize the canary used
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001383when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001384value will weaken the protection as the attacker could easily write the right
1385value as part of the attack most of the time. Therefore, it should return a
1386true random number.
1387
Paul Beesleyba3ed402019-03-13 16:20:44 +00001388.. warning::
1389 For the protection to be effective, the global data need to be placed at
1390 a lower address than the stack bases. Failure to do so would allow an
1391 attacker to overwrite the canary as part of the stack buffer overflow attack.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001392
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001393Function : plat_flush_next_bl_params()
1394~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001395
1396::
1397
1398 Argument : void
1399 Return : void
1400
1401This function flushes to main memory all the image params that are passed to
Soby Mathew97b1bff2018-09-27 16:46:41 +01001402next image. This function is invoked in BL2 to flush this information
1403to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001404
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001405Function : plat_log_get_prefix()
1406~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewaaf15f52017-09-04 11:49:29 +01001407
1408::
1409
1410 Argument : unsigned int
1411 Return : const char *
1412
1413This function defines the prefix string corresponding to the `log_level` to be
Dan Handley610e7e12018-03-01 18:44:00 +00001414prepended to all the log output from TF-A. The `log_level` (argument) will
1415correspond to one of the standard log levels defined in debug.h. The platform
1416can override the common implementation to define a different prefix string for
John Tsichritzis30f89642018-06-07 16:31:34 +01001417the log output. The implementation should be robust to future changes that
Dan Handley610e7e12018-03-01 18:44:00 +00001418increase the number of log levels.
Soby Mathewaaf15f52017-09-04 11:49:29 +01001419
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001420Function : plat_get_soc_version()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001421~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001422
1423::
1424
1425 Argument : void
1426 Return : int32_t
1427
1428This function returns soc version which mainly consist of below fields
1429
1430::
1431
1432 soc_version[30:24] = JEP-106 continuation code for the SiP
1433 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001434 soc_version[15:0] = Implementation defined SoC ID
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001435
1436Function : plat_get_soc_revision()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001437~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001438
1439::
1440
1441 Argument : void
1442 Return : int32_t
1443
1444This function returns soc revision in below format
1445
1446::
1447
1448 soc_revision[0:30] = SOC revision of specific SOC
1449
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001450Function : plat_is_smccc_feature_available()
1451~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1452
1453::
1454
1455 Argument : u_register_t
1456 Return : int32_t
1457
1458This function returns SMC_ARCH_CALL_SUCCESS if the platform supports
1459the SMCCC function specified in the argument; otherwise returns
1460SMC_ARCH_CALL_NOT_SUPPORTED.
1461
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001462Function : plat_mboot_measure_image()
1463~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1464
1465::
1466
1467 Argument : unsigned int, image_info_t *
Manish V Badarkhe931c6ef2021-10-21 09:06:18 +01001468 Return : int
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001469
1470When the MEASURED_BOOT flag is enabled:
1471
1472- This function measures the given image and records its measurement using
1473 the measured boot backend driver.
1474- On the Arm FVP port, this function measures the given image using its
1475 passed id and information and then records that measurement in the
1476 Event Log buffer.
Manish V Badarkhe931c6ef2021-10-21 09:06:18 +01001477- This function must return 0 on success, a signed integer error code
1478 otherwise.
1479
1480When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1481
1482Function : plat_mboot_measure_critical_data()
1483~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1484
1485::
1486
1487 Argument : unsigned int, const void *, size_t
1488 Return : int
1489
1490When the MEASURED_BOOT flag is enabled:
1491
1492- This function measures the given critical data structure and records its
1493 measurement using the measured boot backend driver.
1494- This function must return 0 on success, a signed integer error code
1495 otherwise.
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001496
1497When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1498
Okash Khawaja037b56e2022-11-04 12:38:01 +00001499Function : plat_can_cmo()
1500~~~~~~~~~~~~~~~~~~~~~~~~~
1501
1502::
1503
1504 Argument : void
1505 Return : uint64_t
1506
1507When CONDITIONAL_CMO flag is enabled:
1508
1509- This function indicates whether cache management operations should be
1510 performed. It returns 0 if CMOs should be skipped and non-zero
1511 otherwise.
Okash Khawaja94532202022-11-14 12:50:30 +00001512- The function must not clobber x1, x2 and x3. It's also not safe to rely on
1513 stack. Otherwise obey AAPCS.
Okash Khawaja037b56e2022-11-04 12:38:01 +00001514
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001515Modifications specific to a Boot Loader stage
1516---------------------------------------------
1517
1518Boot Loader Stage 1 (BL1)
1519-------------------------
1520
1521BL1 implements the reset vector where execution starts from after a cold or
1522warm boot. For each CPU, BL1 is responsible for the following tasks:
1523
1524#. Handling the reset as described in section 2.2
1525
1526#. In the case of a cold boot and the CPU being the primary CPU, ensuring that
1527 only this CPU executes the remaining BL1 code, including loading and passing
1528 control to the BL2 stage.
1529
1530#. Identifying and starting the Firmware Update process (if required).
1531
1532#. Loading the BL2 image from non-volatile storage into secure memory at the
1533 address specified by the platform defined constant ``BL2_BASE``.
1534
1535#. Populating a ``meminfo`` structure with the following information in memory,
1536 accessible by BL2 immediately upon entry.
1537
1538 ::
1539
1540 meminfo.total_base = Base address of secure RAM visible to BL2
1541 meminfo.total_size = Size of secure RAM visible to BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001542
Soby Mathew97b1bff2018-09-27 16:46:41 +01001543 By default, BL1 places this ``meminfo`` structure at the end of secure
1544 memory visible to BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001545
Soby Mathewb1bf0442018-02-16 14:52:52 +00001546 It is possible for the platform to decide where it wants to place the
1547 ``meminfo`` structure for BL2 or restrict the amount of memory visible to
1548 BL2 by overriding the weak default implementation of
1549 ``bl1_plat_handle_post_image_load`` API.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001550
1551The following functions need to be implemented by the platform port to enable
1552BL1 to perform the above tasks.
1553
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001554Function : bl1_early_platform_setup() [mandatory]
1555~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001556
1557::
1558
1559 Argument : void
1560 Return : void
1561
1562This function executes with the MMU and data caches disabled. It is only called
1563by the primary CPU.
1564
Dan Handley610e7e12018-03-01 18:44:00 +00001565On Arm standard platforms, this function:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001566
1567- Enables a secure instance of SP805 to act as the Trusted Watchdog.
1568
1569- Initializes a UART (PL011 console), which enables access to the ``printf``
1570 family of functions in BL1.
1571
1572- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to
1573 the CCI slave interface corresponding to the cluster that includes the
1574 primary CPU.
1575
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001576Function : bl1_plat_arch_setup() [mandatory]
1577~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001578
1579::
1580
1581 Argument : void
1582 Return : void
1583
1584This function performs any platform-specific and architectural setup that the
1585platform requires. Platform-specific setup might include configuration of
1586memory controllers and the interconnect.
1587
Dan Handley610e7e12018-03-01 18:44:00 +00001588In Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001589
1590This function helps fulfill requirement 2 above.
1591
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001592Function : bl1_platform_setup() [mandatory]
1593~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001594
1595::
1596
1597 Argument : void
1598 Return : void
1599
1600This function executes with the MMU and data caches enabled. It is responsible
1601for performing any remaining platform-specific setup that can occur after the
1602MMU and data cache have been enabled.
1603
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001604if support for multiple boot sources is required, it initializes the boot
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001605sequence used by plat_try_next_boot_source().
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001606
Dan Handley610e7e12018-03-01 18:44:00 +00001607In Arm standard platforms, this function initializes the storage abstraction
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001608layer used to load the next bootloader image.
1609
1610This function helps fulfill requirement 4 above.
1611
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001612Function : bl1_plat_sec_mem_layout() [mandatory]
1613~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001614
1615::
1616
1617 Argument : void
1618 Return : meminfo *
1619
1620This function should only be called on the cold boot path. It executes with the
1621MMU and data caches enabled. The pointer returned by this function must point to
1622a ``meminfo`` structure containing the extents and availability of secure RAM for
1623the BL1 stage.
1624
1625::
1626
1627 meminfo.total_base = Base address of secure RAM visible to BL1
1628 meminfo.total_size = Size of secure RAM visible to BL1
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001629
1630This information is used by BL1 to load the BL2 image in secure RAM. BL1 also
1631populates a similar structure to tell BL2 the extents of memory available for
1632its own use.
1633
1634This function helps fulfill requirements 4 and 5 above.
1635
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001636Function : bl1_plat_prepare_exit() [optional]
1637~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001638
1639::
1640
1641 Argument : entry_point_info_t *
1642 Return : void
1643
1644This function is called prior to exiting BL1 in response to the
1645``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform
1646platform specific clean up or bookkeeping operations before transferring
1647control to the next image. It receives the address of the ``entry_point_info_t``
1648structure passed from BL2. This function runs with MMU disabled.
1649
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001650Function : bl1_plat_set_ep_info() [optional]
1651~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001652
1653::
1654
1655 Argument : unsigned int image_id, entry_point_info_t *ep_info
1656 Return : void
1657
1658This function allows platforms to override ``ep_info`` for the given ``image_id``.
1659
1660The default implementation just returns.
1661
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001662Function : bl1_plat_get_next_image_id() [optional]
1663~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001664
1665::
1666
1667 Argument : void
1668 Return : unsigned int
1669
1670This and the following function must be overridden to enable the FWU feature.
1671
1672BL1 calls this function after platform setup to identify the next image to be
1673loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds
1674with the normal boot sequence, which loads and executes BL2. If the platform
1675returns a different image id, BL1 assumes that Firmware Update is required.
1676
Dan Handley610e7e12018-03-01 18:44:00 +00001677The default implementation always returns ``BL2_IMAGE_ID``. The Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001678platforms override this function to detect if firmware update is required, and
1679if so, return the first image in the firmware update process.
1680
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001681Function : bl1_plat_get_image_desc() [optional]
1682~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001683
1684::
1685
1686 Argument : unsigned int image_id
1687 Return : image_desc_t *
1688
1689BL1 calls this function to get the image descriptor information ``image_desc_t``
1690for the provided ``image_id`` from the platform.
1691
Dan Handley610e7e12018-03-01 18:44:00 +00001692The default implementation always returns a common BL2 image descriptor. Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001693standard platforms return an image descriptor corresponding to BL2 or one of
1694the firmware update images defined in the Trusted Board Boot Requirements
1695specification.
1696
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001697Function : bl1_plat_handle_pre_image_load() [optional]
1698~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001699
1700::
1701
Soby Mathew2f38ce32018-02-08 17:45:12 +00001702 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001703 Return : int
1704
1705This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001706corresponding to ``image_id``. This function is invoked in BL1, both in cold
1707boot and FWU code path, before loading the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001708
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001709Function : bl1_plat_handle_post_image_load() [optional]
1710~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001711
1712::
1713
Soby Mathew2f38ce32018-02-08 17:45:12 +00001714 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001715 Return : int
1716
1717This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001718corresponding to ``image_id``. This function is invoked in BL1, both in cold
1719boot and FWU code path, after loading and authenticating the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001720
Soby Mathewb1bf0442018-02-16 14:52:52 +00001721The default weak implementation of this function calculates the amount of
1722Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t``
1723structure at the beginning of this free memory and populates it. The address
1724of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint
1725information to BL2.
1726
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001727Function : bl1_plat_fwu_done() [optional]
1728~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001729
1730::
1731
1732 Argument : unsigned int image_id, uintptr_t image_src,
1733 unsigned int image_size
1734 Return : void
1735
1736BL1 calls this function when the FWU process is complete. It must not return.
1737The platform may override this function to take platform specific action, for
1738example to initiate the normal boot flow.
1739
1740The default implementation spins forever.
1741
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001742Function : bl1_plat_mem_check() [mandatory]
1743~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001744
1745::
1746
1747 Argument : uintptr_t mem_base, unsigned int mem_size,
1748 unsigned int flags
1749 Return : int
1750
1751BL1 calls this function while handling FWU related SMCs, more specifically when
1752copying or authenticating an image. Its responsibility is to ensure that the
1753region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and
1754that this memory corresponds to either a secure or non-secure memory region as
1755indicated by the security state of the ``flags`` argument.
1756
1757This function can safely assume that the value resulting from the addition of
1758``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not
1759overflow.
1760
1761This function must return 0 on success, a non-null error code otherwise.
1762
1763The default implementation of this function asserts therefore platforms must
1764override it when using the FWU feature.
1765
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001766Function : bl1_plat_mboot_init() [optional]
1767~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1768
1769::
1770
1771 Argument : void
1772 Return : void
1773
1774When the MEASURED_BOOT flag is enabled:
1775
1776- This function is used to initialize the backend driver(s) of measured boot.
1777- On the Arm FVP port, this function is used to initialize the Event Log
1778 backend driver, and also to write header information in the Event Log buffer.
1779
1780When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1781
1782Function : bl1_plat_mboot_finish() [optional]
1783~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1784
1785::
1786
1787 Argument : void
1788 Return : void
1789
1790When the MEASURED_BOOT flag is enabled:
1791
1792- This function is used to finalize the measured boot backend driver(s),
1793 and also, set the information for the next bootloader component to
1794 extend the measurement if needed.
1795- On the Arm FVP port, this function is used to pass the base address of
1796 the Event Log buffer and its size to BL2 via tb_fw_config to extend the
1797 Event Log buffer with the measurement of various images loaded by BL2.
1798 It results in panic on error.
1799
1800When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1801
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001802Boot Loader Stage 2 (BL2)
1803-------------------------
1804
1805The BL2 stage is executed only by the primary CPU, which is determined in BL1
1806using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at
Soby Mathew97b1bff2018-09-27 16:46:41 +01001807``BL2_BASE``. BL2 executes in Secure EL1 and and invokes
1808``plat_get_bl_image_load_info()`` to retrieve the list of images to load from
1809non-volatile storage to secure/non-secure RAM. After all the images are loaded
1810then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable
1811images to be passed to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001812
1813The following functions must be implemented by the platform port to enable BL2
1814to perform the above tasks.
1815
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001816Function : bl2_early_platform_setup2() [mandatory]
1817~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001818
1819::
1820
Soby Mathew97b1bff2018-09-27 16:46:41 +01001821 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001822 Return : void
1823
1824This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001825by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments
1826are platform specific.
1827
1828On Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001829
Manish V Badarkhe81414512020-06-24 15:58:38 +01001830 arg0 - Points to load address of FW_CONFIG
Soby Mathew97b1bff2018-09-27 16:46:41 +01001831
1832 arg1 - ``meminfo`` structure populated by BL1. The platform copies
1833 the contents of ``meminfo`` as it may be subsequently overwritten by BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001834
Dan Handley610e7e12018-03-01 18:44:00 +00001835On Arm standard platforms, this function also:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001836
1837- Initializes a UART (PL011 console), which enables access to the ``printf``
1838 family of functions in BL2.
1839
1840- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001841 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1842 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001843
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001844Function : bl2_plat_arch_setup() [mandatory]
1845~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001846
1847::
1848
1849 Argument : void
1850 Return : void
1851
1852This function executes with the MMU and data caches disabled. It is only called
1853by the primary CPU.
1854
1855The purpose of this function is to perform any architectural initialization
1856that varies across platforms.
1857
Dan Handley610e7e12018-03-01 18:44:00 +00001858On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001859
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001860Function : bl2_platform_setup() [mandatory]
1861~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001862
1863::
1864
1865 Argument : void
1866 Return : void
1867
1868This function may execute with the MMU and data caches enabled if the platform
1869port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only
1870called by the primary CPU.
1871
1872The purpose of this function is to perform any platform initialization
1873specific to BL2.
1874
Dan Handley610e7e12018-03-01 18:44:00 +00001875In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001876configuration of the TrustZone controller to allow non-secure masters access
1877to most of DRAM. Part of DRAM is reserved for secure world use.
1878
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001879Function : bl2_plat_handle_pre_image_load() [optional]
1880~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001881
1882::
1883
1884 Argument : unsigned int
1885 Return : int
1886
1887This function can be used by the platforms to update/use image information
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001888for given ``image_id``. This function is currently invoked in BL2 before
Soby Mathew97b1bff2018-09-27 16:46:41 +01001889loading each image.
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001890
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001891Function : bl2_plat_handle_post_image_load() [optional]
1892~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001893
1894::
1895
1896 Argument : unsigned int
1897 Return : int
1898
1899This function can be used by the platforms to update/use image information
1900for given ``image_id``. This function is currently invoked in BL2 after
Soby Mathew97b1bff2018-09-27 16:46:41 +01001901loading each image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001902
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001903Function : bl2_plat_preload_setup [optional]
1904~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001905
1906::
John Tsichritzisee10e792018-06-06 09:38:10 +01001907
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001908 Argument : void
1909 Return : void
1910
1911This optional function performs any BL2 platform initialization
1912required before image loading, that is not done later in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001913bl2_platform_setup(). Specifically, if support for multiple
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001914boot sources is required, it initializes the boot sequence used by
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001915plat_try_next_boot_source().
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001916
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001917Function : plat_try_next_boot_source() [optional]
1918~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001919
1920::
John Tsichritzisee10e792018-06-06 09:38:10 +01001921
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001922 Argument : void
1923 Return : int
1924
1925This optional function passes to the next boot source in the redundancy
1926sequence.
1927
1928This function moves the current boot redundancy source to the next
1929element in the boot sequence. If there are no more boot sources then it
1930must return 0, otherwise it must return 1. The default implementation
1931of this always returns 0.
1932
Sandrine Bailleuxeb5fadc2022-07-13 10:07:54 +02001933Function : bl2_plat_mboot_init() [optional]
1934~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1935
1936::
1937
1938 Argument : void
1939 Return : void
1940
1941When the MEASURED_BOOT flag is enabled:
1942
1943- This function is used to initialize the backend driver(s) of measured boot.
1944- On the Arm FVP port, this function is used to initialize the Event Log
1945 backend driver with the Event Log buffer information (base address and
1946 size) received from BL1. It results in panic on error.
1947
1948When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1949
1950Function : bl2_plat_mboot_finish() [optional]
1951~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1952
1953::
1954
1955 Argument : void
1956 Return : void
1957
1958When the MEASURED_BOOT flag is enabled:
1959
1960- This function is used to finalize the measured boot backend driver(s),
1961 and also, set the information for the next bootloader component to extend
1962 the measurement if needed.
1963- On the Arm FVP port, this function is used to pass the Event Log buffer
1964 information (base address and size) to non-secure(BL33) and trusted OS(BL32)
1965 via nt_fw and tos_fw config respectively. It results in panic on error.
1966
1967When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1968
Roberto Vargasb1584272017-11-20 13:36:10 +00001969Boot Loader Stage 2 (BL2) at EL3
1970--------------------------------
1971
Dan Handley610e7e12018-03-01 18:44:00 +00001972When the platform has a non-TF-A Boot ROM it is desirable to jump
1973directly to BL2 instead of TF-A BL1. In this case BL2 is expected to
Paul Beesleyf8640672019-04-12 14:19:42 +01001974execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design`
1975document for more information.
Roberto Vargasb1584272017-11-20 13:36:10 +00001976
1977All mandatory functions of BL2 must be implemented, except the functions
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001978bl2_early_platform_setup and bl2_el3_plat_arch_setup, because
1979their work is done now by bl2_el3_early_platform_setup and
1980bl2_el3_plat_arch_setup. These functions should generally implement
1981the bl1_plat_xxx() and bl2_plat_xxx() functionality combined.
Roberto Vargasb1584272017-11-20 13:36:10 +00001982
1983
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001984Function : bl2_el3_early_platform_setup() [mandatory]
1985~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001986
1987::
John Tsichritzisee10e792018-06-06 09:38:10 +01001988
Roberto Vargasb1584272017-11-20 13:36:10 +00001989 Argument : u_register_t, u_register_t, u_register_t, u_register_t
1990 Return : void
1991
1992This function executes with the MMU and data caches disabled. It is only called
1993by the primary CPU. This function receives four parameters which can be used
1994by the platform to pass any needed information from the Boot ROM to BL2.
1995
Dan Handley610e7e12018-03-01 18:44:00 +00001996On Arm standard platforms, this function does the following:
Roberto Vargasb1584272017-11-20 13:36:10 +00001997
1998- Initializes a UART (PL011 console), which enables access to the ``printf``
1999 family of functions in BL2.
2000
2001- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002002 images. It is necessary to do this early on platforms with a SCP_BL2 image,
2003 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Roberto Vargasb1584272017-11-20 13:36:10 +00002004
2005- Initializes the private variables that define the memory layout used.
2006
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002007Function : bl2_el3_plat_arch_setup() [mandatory]
2008~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00002009
2010::
John Tsichritzisee10e792018-06-06 09:38:10 +01002011
Roberto Vargasb1584272017-11-20 13:36:10 +00002012 Argument : void
2013 Return : void
2014
2015This function executes with the MMU and data caches disabled. It is only called
2016by the primary CPU.
2017
2018The purpose of this function is to perform any architectural initialization
2019that varies across platforms.
2020
Dan Handley610e7e12018-03-01 18:44:00 +00002021On Arm standard platforms, this function enables the MMU.
Roberto Vargasb1584272017-11-20 13:36:10 +00002022
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002023Function : bl2_el3_plat_prepare_exit() [optional]
2024~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00002025
2026::
John Tsichritzisee10e792018-06-06 09:38:10 +01002027
Roberto Vargasb1584272017-11-20 13:36:10 +00002028 Argument : void
2029 Return : void
2030
2031This function is called prior to exiting BL2 and run the next image.
2032It should be used to perform platform specific clean up or bookkeeping
2033operations before transferring control to the next image. This function
2034runs with MMU disabled.
2035
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002036FWU Boot Loader Stage 2 (BL2U)
2037------------------------------
2038
2039The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU
2040process and is executed only by the primary CPU. BL1 passes control to BL2U at
2041``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for:
2042
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002043#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure
2044 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1.
2045 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U
2046 should be copied from. Subsequent handling of the SCP_BL2U image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002047 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function.
2048 If ``SCP_BL2U_BASE`` is not defined then this step is not performed.
2049
2050#. Any platform specific setup required to perform the FWU process. For
Dan Handley610e7e12018-03-01 18:44:00 +00002051 example, Arm standard platforms initialize the TZC controller so that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002052 normal world can access DDR memory.
2053
2054The following functions must be implemented by the platform port to enable
2055BL2U to perform the tasks mentioned above.
2056
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002057Function : bl2u_early_platform_setup() [mandatory]
2058~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002059
2060::
2061
2062 Argument : meminfo *mem_info, void *plat_info
2063 Return : void
2064
2065This function executes with the MMU and data caches disabled. It is only
2066called by the primary CPU. The arguments to this function is the address
2067of the ``meminfo`` structure and platform specific info provided by BL1.
2068
2069The platform may copy the contents of the ``mem_info`` and ``plat_info`` into
2070private storage as the original memory may be subsequently overwritten by BL2U.
2071
Dan Handley610e7e12018-03-01 18:44:00 +00002072On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002073to extract SCP_BL2U image information, which is then copied into a private
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002074variable.
2075
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002076Function : bl2u_plat_arch_setup() [mandatory]
2077~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002078
2079::
2080
2081 Argument : void
2082 Return : void
2083
2084This function executes with the MMU and data caches disabled. It is only
2085called by the primary CPU.
2086
2087The purpose of this function is to perform any architectural initialization
2088that varies across platforms, for example enabling the MMU (since the memory
2089map differs across platforms).
2090
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002091Function : bl2u_platform_setup() [mandatory]
2092~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002093
2094::
2095
2096 Argument : void
2097 Return : void
2098
2099This function may execute with the MMU and data caches enabled if the platform
2100port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only
2101called by the primary CPU.
2102
2103The purpose of this function is to perform any platform initialization
2104specific to BL2U.
2105
Dan Handley610e7e12018-03-01 18:44:00 +00002106In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002107configuration of the TrustZone controller to allow non-secure masters access
2108to most of DRAM. Part of DRAM is reserved for secure world use.
2109
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002110Function : bl2u_plat_handle_scp_bl2u() [optional]
2111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002112
2113::
2114
2115 Argument : void
2116 Return : int
2117
2118This function is used to perform any platform-specific actions required to
2119handle the SCP firmware. Typically it transfers the image into SCP memory using
2120a platform-specific protocol and waits until SCP executes it and signals to the
2121Application Processor (AP) for BL2U execution to continue.
2122
2123This function returns 0 on success, a negative error code otherwise.
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002124This function is included if SCP_BL2U_BASE is defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002125
2126Boot Loader Stage 3-1 (BL31)
2127----------------------------
2128
2129During cold boot, the BL31 stage is executed only by the primary CPU. This is
2130determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes
2131control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all
2132CPUs. BL31 executes at EL3 and is responsible for:
2133
2134#. Re-initializing all architectural and platform state. Although BL1 performs
2135 some of this initialization, BL31 remains resident in EL3 and must ensure
2136 that EL3 architectural and platform state is completely initialized. It
2137 should make no assumptions about the system state when it receives control.
2138
2139#. Passing control to a normal world BL image, pre-loaded at a platform-
Soby Mathew97b1bff2018-09-27 16:46:41 +01002140 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list
2141 populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002142
2143#. Providing runtime firmware services. Currently, BL31 only implements a
2144 subset of the Power State Coordination Interface (PSCI) API as a runtime
Boyan Karatotev907d38b2022-11-22 12:01:09 +00002145 service. See :ref:`psci_in_bl31` below for details of porting the PSCI
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002146 implementation.
2147
2148#. Optionally passing control to the BL32 image, pre-loaded at a platform-
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002149 specific address by BL2. BL31 exports a set of APIs that allow runtime
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002150 services to specify the security state in which the next image should be
Soby Mathew97b1bff2018-09-27 16:46:41 +01002151 executed and run the corresponding image. On ARM platforms, BL31 uses the
2152 ``bl_params`` list populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002153
2154If BL31 is a reset vector, It also needs to handle the reset as specified in
2155section 2.2 before the tasks described above.
2156
2157The following functions must be implemented by the platform port to enable BL31
2158to perform the above tasks.
2159
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002160Function : bl31_early_platform_setup2() [mandatory]
2161~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002162
2163::
2164
Soby Mathew97b1bff2018-09-27 16:46:41 +01002165 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002166 Return : void
2167
2168This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01002169by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are
2170platform specific.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002171
Soby Mathew97b1bff2018-09-27 16:46:41 +01002172In Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002173
Soby Mathew97b1bff2018-09-27 16:46:41 +01002174 arg0 - The pointer to the head of `bl_params_t` list
2175 which is list of executable images following BL31,
2176
2177 arg1 - Points to load address of SOC_FW_CONFIG if present
Mikael Olsson0232da22021-02-12 17:30:16 +01002178 except in case of Arm FVP and Juno platform.
Manish V Badarkhe81414512020-06-24 15:58:38 +01002179
Mikael Olsson0232da22021-02-12 17:30:16 +01002180 In case of Arm FVP and Juno platform, points to load address
Manish V Badarkhe81414512020-06-24 15:58:38 +01002181 of FW_CONFIG.
Soby Mathew97b1bff2018-09-27 16:46:41 +01002182
2183 arg2 - Points to load address of HW_CONFIG if present
2184
2185 arg3 - A special value to verify platform parameters from BL2 to BL31. Not
2186 used in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002187
Soby Mathew97b1bff2018-09-27 16:46:41 +01002188The function runs through the `bl_param_t` list and extracts the entry point
2189information for BL32 and BL33. It also performs the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002190
2191- Initialize a UART (PL011 console), which enables access to the ``printf``
2192 family of functions in BL31.
2193
2194- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the
2195 CCI slave interface corresponding to the cluster that includes the primary
2196 CPU.
2197
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002198Function : bl31_plat_arch_setup() [mandatory]
2199~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002200
2201::
2202
2203 Argument : void
2204 Return : void
2205
2206This function executes with the MMU and data caches disabled. It is only called
2207by the primary CPU.
2208
2209The purpose of this function is to perform any architectural initialization
2210that varies across platforms.
2211
Dan Handley610e7e12018-03-01 18:44:00 +00002212On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002213
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002214Function : bl31_platform_setup() [mandatory]
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002215~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2216
2217::
2218
2219 Argument : void
2220 Return : void
2221
2222This function may execute with the MMU and data caches enabled if the platform
2223port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only
2224called by the primary CPU.
2225
2226The purpose of this function is to complete platform initialization so that both
2227BL31 runtime services and normal world software can function correctly.
2228
Dan Handley610e7e12018-03-01 18:44:00 +00002229On Arm standard platforms, this function does the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002230
2231- Initialize the generic interrupt controller.
2232
2233 Depending on the GIC driver selected by the platform, the appropriate GICv2
2234 or GICv3 initialization will be done, which mainly consists of:
2235
2236 - Enable secure interrupts in the GIC CPU interface.
2237 - Disable the legacy interrupt bypass mechanism.
2238 - Configure the priority mask register to allow interrupts of all priorities
2239 to be signaled to the CPU interface.
2240 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure.
2241 - Target all secure SPIs to CPU0.
2242 - Enable these secure interrupts in the GIC distributor.
2243 - Configure all other interrupts as non-secure.
2244 - Enable signaling of secure interrupts in the GIC distributor.
2245
2246- Enable system-level implementation of the generic timer counter through the
2247 memory mapped interface.
2248
2249- Grant access to the system counter timer module
2250
2251- Initialize the power controller device.
2252
2253 In particular, initialise the locks that prevent concurrent accesses to the
2254 power controller device.
2255
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002256Function : bl31_plat_runtime_setup() [optional]
2257~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002258
2259::
2260
2261 Argument : void
2262 Return : void
2263
2264The purpose of this function is allow the platform to perform any BL31 runtime
2265setup just prior to BL31 exit during cold boot. The default weak
Julius Werneraae9bb12017-09-18 16:49:48 -07002266implementation of this function will invoke ``console_switch_state()`` to switch
2267console output to consoles marked for use in the ``runtime`` state.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002268
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002269Function : bl31_plat_get_next_image_ep_info() [mandatory]
2270~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002271
2272::
2273
Sandrine Bailleux842117d2018-05-14 14:25:47 +02002274 Argument : uint32_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002275 Return : entry_point_info *
2276
2277This function may execute with the MMU and data caches enabled if the platform
2278port does the necessary initializations in ``bl31_plat_arch_setup()``.
2279
2280This function is called by ``bl31_main()`` to retrieve information provided by
2281BL2 for the next image in the security state specified by the argument. BL31
2282uses this information to pass control to that image in the specified security
2283state. This function must return a pointer to the ``entry_point_info`` structure
2284(that was copied during ``bl31_early_platform_setup()``) if the image exists. It
2285should return NULL otherwise.
2286
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002287Function : plat_rmmd_get_cca_attest_token() [mandatory when ENABLE_RME == 1]
Soby Mathew294e1cf2022-03-22 16:19:39 +00002288~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2289
2290::
2291
2292 Argument : uintptr_t, size_t *, uintptr_t, size_t
2293 Return : int
2294
2295This function returns the Platform attestation token.
2296
2297The parameters of the function are:
2298
2299 arg0 - A pointer to the buffer where the Platform token should be copied by
2300 this function. The buffer must be big enough to hold the Platform
2301 token.
2302
2303 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
2304 function returns the platform token length in this parameter.
2305
2306 arg2 - A pointer to the buffer where the challenge object is stored.
2307
2308 arg3 - The length of the challenge object in bytes. Possible values are 32,
2309 48 and 64.
2310
2311The function returns 0 on success, -EINVAL on failure.
2312
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002313Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1]
2314~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewf05d93a2022-03-22 16:21:19 +00002315
2316::
2317
2318 Argument : uintptr_t, size_t *, unsigned int
2319 Return : int
2320
2321This function returns the delegated realm attestation key which will be used to
2322sign Realm attestation token. The API currently only supports P-384 ECC curve
2323key.
2324
2325The parameters of the function are:
2326
2327 arg0 - A pointer to the buffer where the attestation key should be copied
2328 by this function. The buffer must be big enough to hold the
2329 attestation key.
2330
2331 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
2332 function returns the attestation key length in this parameter.
2333
2334 arg2 - The type of the elliptic curve to which the requested attestation key
2335 belongs.
2336
2337The function returns 0 on success, -EINVAL on failure.
2338
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002339Function : plat_rmmd_get_el3_rmm_shared_mem() [when ENABLE_RME == 1]
2340~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2341
2342::
2343
2344 Argument : uintptr_t *
2345 Return : size_t
2346
2347This function returns the size of the shared area between EL3 and RMM (or 0 on
2348failure). A pointer to the shared area (or a NULL pointer on failure) is stored
2349in the pointer passed as argument.
2350
Javier Almansa Sobrino4165e842022-04-25 17:18:15 +01002351Function : plat_rmmd_load_manifest() [when ENABLE_RME == 1]
2352~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2353
2354::
2355
2356 Arguments : rmm_manifest_t *manifest
2357 Return : int
2358
2359When ENABLE_RME is enabled, this function populates a boot manifest for the
2360RMM image and stores it in the area specified by manifest.
2361
2362When ENABLE_RME is disabled, this function is not used.
2363
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01002364Function : bl31_plat_enable_mmu [optional]
2365~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2366
2367::
2368
2369 Argument : uint32_t
2370 Return : void
2371
2372This function enables the MMU. The boot code calls this function with MMU and
2373caches disabled. This function should program necessary registers to enable
2374translation, and upon return, the MMU on the calling PE must be enabled.
2375
2376The function must honor flags passed in the first argument. These flags are
2377defined by the translation library, and can be found in the file
2378``include/lib/xlat_tables/xlat_mmu_helpers.h``.
2379
2380On DynamIQ systems, this function must not use stack while enabling MMU, which
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002381is how the function in xlat table library version 2 is implemented.
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01002382
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002383Function : plat_init_apkey [optional]
2384~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002385
2386::
2387
2388 Argument : void
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002389 Return : uint128_t
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002390
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002391This function returns the 128-bit value which can be used to program ARMv8.3
2392pointer authentication keys.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002393
2394The value should be obtained from a reliable source of randomness.
2395
2396This function is only needed if ARMv8.3 pointer authentication is used in the
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002397Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002398
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002399Function : plat_get_syscnt_freq2() [mandatory]
2400~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002401
2402::
2403
2404 Argument : void
2405 Return : unsigned int
2406
2407This function is used by the architecture setup code to retrieve the counter
2408frequency for the CPU's generic timer. This value will be programmed into the
Dan Handley610e7e12018-03-01 18:44:00 +00002409``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002410of the system counter, which is retrieved from the first entry in the frequency
2411modes table.
2412
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002413#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]
2414~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002415
2416When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in
2417bytes) aligned to the cache line boundary that should be allocated per-cpu to
2418accommodate all the bakery locks.
2419
2420If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker
Chris Kay33bfc5e2023-02-14 11:30:04 +00002421calculates the size of the ``.bakery_lock`` input section, aligns it to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002422nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT``
2423and stores the result in a linker symbol. This constant prevents a platform
2424from relying on the linker and provide a more efficient mechanism for
2425accessing per-cpu bakery lock information.
2426
2427If this constant is defined and its value is not equal to the value
2428calculated by the linker then a link time assertion is raised. A compile time
2429assertion is raised if the value of the constant is not aligned to the cache
2430line boundary.
2431
Paul Beesleyf8640672019-04-12 14:19:42 +01002432.. _porting_guide_sdei_requirements:
2433
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002434SDEI porting requirements
2435~~~~~~~~~~~~~~~~~~~~~~~~~
2436
Paul Beesley606d8072019-03-13 13:58:02 +00002437The |SDEI| dispatcher requires the platform to provide the following macros
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002438and functions, of which some are optional, and some others mandatory.
2439
2440Macros
2441......
2442
2443Macro: PLAT_SDEI_NORMAL_PRI [mandatory]
2444^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2445
2446This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00002447Normal |SDEI| events on the platform. This must have a higher value
2448(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002449
2450Macro: PLAT_SDEI_CRITICAL_PRI [mandatory]
2451^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2452
2453This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00002454Critical |SDEI| events on the platform. This must have a lower value
2455(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002456
Paul Beesley606d8072019-03-13 13:58:02 +00002457**Note**: |SDEI| exception priorities must be the lowest among Secure
2458priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must
2459be higher than Normal |SDEI| priority.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002460
2461Functions
2462.........
2463
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002464Function: int plat_sdei_validate_entry_point() [optional]
2465^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002466
2467::
2468
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002469 Argument: uintptr_t ep, unsigned int client_mode
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002470 Return: int
2471
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002472This function validates the entry point address of the event handler provided by
2473the client for both event registration and *Complete and Resume* |SDEI| calls.
2474The function ensures that the address is valid in the client translation regime.
2475
2476The second argument is the exception level that the client is executing in. It
2477can be Non-Secure EL1 or Non-Secure EL2.
2478
2479The function must return ``0`` for successful validation, or ``-1`` upon failure.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002480
Dan Handley610e7e12018-03-01 18:44:00 +00002481The default implementation always returns ``0``. On Arm platforms, this function
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002482translates the entry point address within the client translation regime and
2483further ensures that the resulting physical address is located in Non-secure
2484DRAM.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002485
2486Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional]
2487^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2488
2489::
2490
2491 Argument: uint64_t
2492 Argument: unsigned int
2493 Return: void
2494
Paul Beesley606d8072019-03-13 13:58:02 +00002495|SDEI| specification requires that a PE comes out of reset with the events
2496masked. The client therefore is expected to call ``PE_UNMASK`` to unmask
2497|SDEI| events on the PE. No |SDEI| events can be dispatched until such
2498time.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002499
Paul Beesley606d8072019-03-13 13:58:02 +00002500Should a PE receive an interrupt that was bound to an |SDEI| event while the
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002501events are masked on the PE, the dispatcher implementation invokes the function
2502``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the
2503interrupt and the interrupt ID are passed as parameters.
2504
2505The default implementation only prints out a warning message.
2506
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -05002507.. _porting_guide_trng_requirements:
2508
2509TRNG porting requirements
2510~~~~~~~~~~~~~~~~~~~~~~~~~
2511
2512The |TRNG| backend requires the platform to provide the following values
2513and mandatory functions.
2514
2515Values
2516......
2517
2518value: uuid_t plat_trng_uuid [mandatory]
2519^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2520
2521This value must be defined to the UUID of the TRNG backend that is specific to
Jayanth Dodderi Chidanand7c7faff2022-10-11 17:16:07 +01002522the hardware after ``plat_entropy_setup`` function is called. This value must
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -05002523conform to the SMCCC calling convention; The most significant 32 bits of the
2524UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in
2525w0 indicates failure to get a TRNG source.
2526
2527Functions
2528.........
2529
2530Function: void plat_entropy_setup(void) [mandatory]
2531^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2532
2533::
2534
2535 Argument: none
2536 Return: none
2537
2538This function is expected to do platform-specific initialization of any TRNG
2539hardware. This may include generating a UUID from a hardware-specific seed.
2540
2541Function: bool plat_get_entropy(uint64_t \*out) [mandatory]
2542^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2543
2544::
2545
2546 Argument: uint64_t *
2547 Return: bool
2548 Out : when the return value is true, the entropy has been written into the
2549 storage pointed to
2550
2551This function writes entropy into storage provided by the caller. If no entropy
2552is available, it must return false and the storage must not be written.
2553
Boyan Karatotev907d38b2022-11-22 12:01:09 +00002554.. _psci_in_bl31:
2555
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002556Power State Coordination Interface (in BL31)
2557--------------------------------------------
2558
Dan Handley610e7e12018-03-01 18:44:00 +00002559The TF-A implementation of the PSCI API is based around the concept of a
2560*power domain*. A *power domain* is a CPU or a logical group of CPUs which
2561share some state on which power management operations can be performed as
2562specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is
2563a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The
2564*power domains* are arranged in a hierarchical tree structure and each
2565*power domain* can be identified in a system by the cpu index of any CPU that
2566is part of that domain and a *power domain level*. A processing element (for
2567example, a CPU) is at level 0. If the *power domain* node above a CPU is a
2568logical grouping of CPUs that share some state, then level 1 is that group of
2569CPUs (for example, a cluster), and level 2 is a group of clusters (for
2570example, the system). More details on the power domain topology and its
Paul Beesleyf8640672019-04-12 14:19:42 +01002571organization can be found in :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002572
2573BL31's platform initialization code exports a pointer to the platform-specific
2574power management operations required for the PSCI implementation to function
2575correctly. This information is populated in the ``plat_psci_ops`` structure. The
2576PSCI implementation calls members of the ``plat_psci_ops`` structure for performing
2577power management operations on the power domains. For example, the target
2578CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()``
2579handler (if present) is called for the CPU power domain.
2580
2581The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to
2582describe composite power states specific to a platform. The PSCI implementation
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00002583defines a generic representation of the power-state parameter, which is an
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002584array of local power states where each index corresponds to a power domain
2585level. Each entry contains the local power state the power domain at that power
2586level could enter. It depends on the ``validate_power_state()`` handler to
2587convert the power-state parameter (possibly encoding a composite power state)
2588passed in a PSCI ``CPU_SUSPEND`` call to this representation.
2589
2590The following functions form part of platform port of PSCI functionality.
2591
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002592Function : plat_psci_stat_accounting_start() [optional]
2593~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002594
2595::
2596
2597 Argument : const psci_power_state_t *
2598 Return : void
2599
2600This is an optional hook that platforms can implement for residency statistics
2601accounting before entering a low power state. The ``pwr_domain_state`` field of
2602``state_info`` (first argument) can be inspected if stat accounting is done
2603differently at CPU level versus higher levels. As an example, if the element at
2604index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2605state, special hardware logic may be programmed in order to keep track of the
2606residency statistics. For higher levels (array indices > 0), the residency
2607statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2608default implementation will use PMF to capture timestamps.
2609
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002610Function : plat_psci_stat_accounting_stop() [optional]
2611~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002612
2613::
2614
2615 Argument : const psci_power_state_t *
2616 Return : void
2617
2618This is an optional hook that platforms can implement for residency statistics
2619accounting after exiting from a low power state. The ``pwr_domain_state`` field
2620of ``state_info`` (first argument) can be inspected if stat accounting is done
2621differently at CPU level versus higher levels. As an example, if the element at
2622index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2623state, special hardware logic may be programmed in order to keep track of the
2624residency statistics. For higher levels (array indices > 0), the residency
2625statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2626default implementation will use PMF to capture timestamps.
2627
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002628Function : plat_psci_stat_get_residency() [optional]
2629~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002630
2631::
2632
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -06002633 Argument : unsigned int, const psci_power_state_t *, unsigned int
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002634 Return : u_register_t
2635
2636This is an optional interface that is is invoked after resuming from a low power
2637state and provides the time spent resident in that low power state by the power
2638domain at a particular power domain level. When a CPU wakes up from suspend,
2639all its parent power domain levels are also woken up. The generic PSCI code
2640invokes this function for each parent power domain that is resumed and it
2641identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second
2642argument) describes the low power state that the power domain has resumed from.
2643The current CPU is the first CPU in the power domain to resume from the low
2644power state and the ``last_cpu_idx`` (third parameter) is the index of the last
2645CPU in the power domain to suspend and may be needed to calculate the residency
2646for that power domain.
2647
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002648Function : plat_get_target_pwr_state() [optional]
2649~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002650
2651::
2652
2653 Argument : unsigned int, const plat_local_state_t *, unsigned int
2654 Return : plat_local_state_t
2655
2656The PSCI generic code uses this function to let the platform participate in
2657state coordination during a power management operation. The function is passed
2658a pointer to an array of platform specific local power state ``states`` (second
2659argument) which contains the requested power state for each CPU at a particular
2660power domain level ``lvl`` (first argument) within the power domain. The function
2661is expected to traverse this array of upto ``ncpus`` (third argument) and return
2662a coordinated target power state by the comparing all the requested power
2663states. The target power state should not be deeper than any of the requested
2664power states.
2665
2666A weak definition of this API is provided by default wherein it assumes
2667that the platform assigns a local state value in order of increasing depth
2668of the power state i.e. for two power states X & Y, if X < Y
2669then X represents a shallower power state than Y. As a result, the
2670coordinated target local power state for a power domain will be the minimum
2671of the requested local power state values.
2672
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002673Function : plat_get_power_domain_tree_desc() [mandatory]
2674~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002675
2676::
2677
2678 Argument : void
2679 Return : const unsigned char *
2680
2681This function returns a pointer to the byte array containing the power domain
2682topology tree description. The format and method to construct this array are
Paul Beesleyf8640672019-04-12 14:19:42 +01002683described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI
2684initialization code requires this array to be described by the platform, either
2685statically or dynamically, to initialize the power domain topology tree. In case
2686the array is populated dynamically, then plat_core_pos_by_mpidr() and
2687plat_my_core_pos() should also be implemented suitably so that the topology tree
2688description matches the CPU indices returned by these APIs. These APIs together
2689form the platform interface for the PSCI topology framework.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002690
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002691Function : plat_setup_psci_ops() [mandatory]
2692~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002693
2694::
2695
2696 Argument : uintptr_t, const plat_psci_ops **
2697 Return : int
2698
2699This function may execute with the MMU and data caches enabled if the platform
2700port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
2701called by the primary CPU.
2702
2703This function is called by PSCI initialization code. Its purpose is to let
2704the platform layer know about the warm boot entrypoint through the
2705``sec_entrypoint`` (first argument) and to export handler routines for
2706platform-specific psci power management actions by populating the passed
2707pointer with a pointer to BL31's private ``plat_psci_ops`` structure.
2708
2709A description of each member of this structure is given below. Please refer to
Dan Handley610e7e12018-03-01 18:44:00 +00002710the Arm FVP specific implementation of these handlers in
Paul Beesleyf8640672019-04-12 14:19:42 +01002711``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002712platform wants to support, the associated operation or operations in this
2713structure must be provided and implemented (Refer section 4 of
Paul Beesleyf8640672019-04-12 14:19:42 +01002714:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI
Dan Handley610e7e12018-03-01 18:44:00 +00002715function in a platform port, the operation should be removed from this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002716structure instead of providing an empty implementation.
2717
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002718plat_psci_ops.cpu_standby()
2719...........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002720
2721Perform the platform-specific actions to enter the standby state for a cpu
2722indicated by the passed argument. This provides a fast path for CPU standby
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002723wherein overheads of PSCI state management and lock acquisition is avoided.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002724For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation,
2725the suspend state type specified in the ``power-state`` parameter should be
2726STANDBY and the target power domain level specified should be the CPU. The
2727handler should put the CPU into a low power retention state (usually by
2728issuing a wfi instruction) and ensure that it can be woken up from that
2729state by a normal interrupt. The generic code expects the handler to succeed.
2730
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002731plat_psci_ops.pwr_domain_on()
2732.............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002733
2734Perform the platform specific actions to power on a CPU, specified
2735by the ``MPIDR`` (first argument). The generic code expects the platform to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002736return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002737
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002738plat_psci_ops.pwr_domain_off()
2739..............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002740
2741Perform the platform specific actions to prepare to power off the calling CPU
2742and its higher parent power domain levels as indicated by the ``target_state``
2743(first argument). It is called by the PSCI ``CPU_OFF`` API implementation.
2744
2745The ``target_state`` encodes the platform coordinated target local power states
2746for the CPU power domain and its parent power domain levels. The handler
2747needs to perform power management operation corresponding to the local state
2748at each power level.
2749
2750For this handler, the local power state for the CPU power domain will be a
2751power down state where as it could be either power down, retention or run state
2752for the higher power domain levels depending on the result of state
2753coordination. The generic code expects the handler to succeed.
2754
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002755plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]
2756...........................................................
Varun Wadekarae87f4b2017-07-10 16:02:05 -07002757
2758This optional function may be used as a performance optimization to replace
2759or complement pwr_domain_suspend() on some platforms. Its calling semantics
2760are identical to pwr_domain_suspend(), except the PSCI implementation only
2761calls this function when suspending to a power down state, and it guarantees
2762that data caches are enabled.
2763
2764When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches
2765before calling pwr_domain_suspend(). If the target_state corresponds to a
2766power down state and it is safe to perform some or all of the platform
2767specific actions in that function with data caches enabled, it may be more
2768efficient to move those actions to this function. When HW_ASSISTED_COHERENCY
2769= 1, data caches remain enabled throughout, and so there is no advantage to
2770moving platform specific actions to this function.
2771
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002772plat_psci_ops.pwr_domain_suspend()
2773..................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002774
2775Perform the platform specific actions to prepare to suspend the calling
2776CPU and its higher parent power domain levels as indicated by the
2777``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND``
2778API implementation.
2779
2780The ``target_state`` has a similar meaning as described in
2781the ``pwr_domain_off()`` operation. It encodes the platform coordinated
2782target local power states for the CPU power domain and its parent
2783power domain levels. The handler needs to perform power management operation
2784corresponding to the local state at each power level. The generic code
2785expects the handler to succeed.
2786
Douglas Raillarda84996b2017-08-02 16:57:32 +01002787The difference between turning a power domain off versus suspending it is that
2788in the former case, the power domain is expected to re-initialize its state
2789when it is next powered on (see ``pwr_domain_on_finish()``). In the latter
2790case, the power domain is expected to save enough state so that it can resume
2791execution by restoring this state when its powered on (see
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002792``pwr_domain_suspend_finish()``).
2793
Douglas Raillarda84996b2017-08-02 16:57:32 +01002794When suspending a core, the platform can also choose to power off the GICv3
2795Redistributor and ITS through an implementation-defined sequence. To achieve
2796this safely, the ITS context must be saved first. The architectural part is
2797implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed
2798sequence is implementation defined and it is therefore the responsibility of
2799the platform code to implement the necessary sequence. Then the GIC
2800Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper.
2801Powering off the Redistributor requires the implementation to support it and it
2802is the responsibility of the platform code to execute the right implementation
2803defined sequence.
2804
2805When a system suspend is requested, the platform can also make use of the
2806``gicv3_distif_save()`` helper to save the context of the GIC Distributor after
2807it has saved the context of the Redistributors and ITS of all the cores in the
2808system. The context of the Distributor can be large and may require it to be
2809allocated in a special area if it cannot fit in the platform's global static
2810data, for example in DRAM. The Distributor can then be powered down using an
2811implementation-defined sequence.
2812
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002813plat_psci_ops.pwr_domain_pwr_down_wfi()
2814.......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002815
2816This is an optional function and, if implemented, is expected to perform
2817platform specific actions including the ``wfi`` invocation which allows the
2818CPU to powerdown. Since this function is invoked outside the PSCI locks,
2819the actions performed in this hook must be local to the CPU or the platform
2820must ensure that races between multiple CPUs cannot occur.
2821
2822The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()``
2823operation and it encodes the platform coordinated target local power states for
2824the CPU power domain and its parent power domain levels. This function must
Boyan Karatotev43771f32022-10-05 13:41:56 +01002825not return back to the caller (by calling wfi in an infinite loop to ensure
2826some CPUs power down mitigations work properly).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002827
2828If this function is not implemented by the platform, PSCI generic
2829implementation invokes ``psci_power_down_wfi()`` for power down.
2830
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002831plat_psci_ops.pwr_domain_on_finish()
2832....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002833
2834This function is called by the PSCI implementation after the calling CPU is
2835powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
2836It performs the platform-specific setup required to initialize enough state for
2837this CPU to enter the normal world and also provide secure runtime firmware
2838services.
2839
2840The ``target_state`` (first argument) is the prior state of the power domains
2841immediately before the CPU was turned on. It indicates which power domains
2842above the CPU might require initialization due to having previously been in
2843low power states. The generic code expects the handler to succeed.
2844
Madhukar Pappireddy33bd5142019-08-12 18:31:33 -05002845plat_psci_ops.pwr_domain_on_finish_late() [optional]
2846...........................................................
2847
2848This optional function is called by the PSCI implementation after the calling
2849CPU is fully powered on with respective data caches enabled. The calling CPU and
2850the associated cluster are guaranteed to be participating in coherency. This
2851function gives the flexibility to perform any platform-specific actions safely,
2852such as initialization or modification of shared data structures, without the
2853overhead of explicit cache maintainace operations.
2854
2855The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()``
2856operation. The generic code expects the handler to succeed.
2857
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002858plat_psci_ops.pwr_domain_suspend_finish()
2859.........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002860
2861This function is called by the PSCI implementation after the calling CPU is
2862powered on and released from reset in response to an asynchronous wakeup
2863event, for example a timer interrupt that was programmed by the CPU during the
2864``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
2865setup required to restore the saved state for this CPU to resume execution
2866in the normal world and also provide secure runtime firmware services.
2867
2868The ``target_state`` (first argument) has a similar meaning as described in
2869the ``pwr_domain_on_finish()`` operation. The generic code expects the platform
2870to succeed.
2871
Douglas Raillarda84996b2017-08-02 16:57:32 +01002872If the Distributor, Redistributors or ITS have been powered off as part of a
2873suspend, their context must be restored in this function in the reverse order
2874to how they were saved during suspend sequence.
2875
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002876plat_psci_ops.system_off()
2877..........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002878
2879This function is called by PSCI implementation in response to a ``SYSTEM_OFF``
2880call. It performs the platform-specific system poweroff sequence after
2881notifying the Secure Payload Dispatcher.
2882
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002883plat_psci_ops.system_reset()
2884............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002885
2886This function is called by PSCI implementation in response to a ``SYSTEM_RESET``
2887call. It performs the platform-specific system reset sequence after
2888notifying the Secure Payload Dispatcher.
2889
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002890plat_psci_ops.validate_power_state()
2891....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002892
2893This function is called by the PSCI implementation during the ``CPU_SUSPEND``
2894call to validate the ``power_state`` parameter of the PSCI API and if valid,
2895populate it in ``req_state`` (second argument) array as power domain level
2896specific local states. If the ``power_state`` is invalid, the platform must
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002897return PSCI_E_INVALID_PARAMS as error, which is propagated back to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002898normal world PSCI client.
2899
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002900plat_psci_ops.validate_ns_entrypoint()
2901......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002902
2903This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
2904``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point``
2905parameter passed by the normal world. If the ``entry_point`` is invalid,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002906the platform must return PSCI_E_INVALID_ADDRESS as error, which is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002907propagated back to the normal world PSCI client.
2908
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002909plat_psci_ops.get_sys_suspend_power_state()
2910...........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002911
2912This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
2913call to get the ``req_state`` parameter from platform which encodes the power
2914domain level specific local states to suspend to system affinity level. The
2915``req_state`` will be utilized to do the PSCI state coordination and
2916``pwr_domain_suspend()`` will be invoked with the coordinated target state to
2917enter system suspend.
2918
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002919plat_psci_ops.get_pwr_lvl_state_idx()
2920.....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002921
2922This is an optional function and, if implemented, is invoked by the PSCI
2923implementation to convert the ``local_state`` (first argument) at a specified
2924``pwr_lvl`` (second argument) to an index between 0 and
2925``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform
2926supports more than two local power states at each power domain level, that is
2927``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these
2928local power states.
2929
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002930plat_psci_ops.translate_power_state_by_mpidr()
2931..............................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002932
2933This is an optional function and, if implemented, verifies the ``power_state``
2934(second argument) parameter of the PSCI API corresponding to a target power
2935domain. The target power domain is identified by using both ``MPIDR`` (first
2936argument) and the power domain level encoded in ``power_state``. The power domain
2937level specific local states are to be extracted from ``power_state`` and be
2938populated in the ``output_state`` (third argument) array. The functionality
2939is similar to the ``validate_power_state`` function described above and is
2940envisaged to be used in case the validity of ``power_state`` depend on the
2941targeted power domain. If the ``power_state`` is invalid for the targeted power
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002942domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002943function is not implemented, then the generic implementation relies on
2944``validate_power_state`` function to translate the ``power_state``.
2945
2946This function can also be used in case the platform wants to support local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002947power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002948APIs as described in Section 5.18 of `PSCI`_.
2949
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002950plat_psci_ops.get_node_hw_state()
2951.................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002952
2953This is an optional function. If implemented this function is intended to return
2954the power state of a node (identified by the first parameter, the ``MPIDR``) in
2955the power domain topology (identified by the second parameter, ``power_level``),
2956as retrieved from a power controller or equivalent component on the platform.
2957Upon successful completion, the implementation must map and return the final
2958status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it
2959must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as
2960appropriate.
2961
2962Implementations are not expected to handle ``power_levels`` greater than
2963``PLAT_MAX_PWR_LVL``.
2964
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002965plat_psci_ops.system_reset2()
2966.............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002967
2968This is an optional function. If implemented this function is
2969called during the ``SYSTEM_RESET2`` call to perform a reset
2970based on the first parameter ``reset_type`` as specified in
2971`PSCI`_. The parameter ``cookie`` can be used to pass additional
2972reset information. If the ``reset_type`` is not supported, the
2973function must return ``PSCI_E_NOT_SUPPORTED``. For architectural
2974resets, all failures must return ``PSCI_E_INVALID_PARAMETERS``
2975and vendor reset can return other PSCI error codes as defined
2976in `PSCI`_. On success this function will not return.
2977
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002978plat_psci_ops.write_mem_protect()
2979.................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002980
2981This is an optional function. If implemented it enables or disables the
2982``MEM_PROTECT`` functionality based on the value of ``val``.
2983A non-zero value enables ``MEM_PROTECT`` and a value of zero
2984disables it. Upon encountering failures it must return a negative value
2985and on success it must return 0.
2986
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002987plat_psci_ops.read_mem_protect()
2988................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002989
2990This is an optional function. If implemented it returns the current
2991state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering
2992failures it must return a negative value and on success it must
2993return 0.
2994
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002995plat_psci_ops.mem_protect_chk()
2996...............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002997
2998This is an optional function. If implemented it checks if a memory
2999region defined by a base address ``base`` and with a size of ``length``
3000bytes is protected by ``MEM_PROTECT``. If the region is protected
3001then it must return 0, otherwise it must return a negative number.
3002
Paul Beesleyf8640672019-04-12 14:19:42 +01003003.. _porting_guide_imf_in_bl31:
3004
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003005Interrupt Management framework (in BL31)
3006----------------------------------------
3007
3008BL31 implements an Interrupt Management Framework (IMF) to manage interrupts
3009generated in either security state and targeted to EL1 or EL2 in the non-secure
3010state or EL3/S-EL1 in the secure state. The design of this framework is
Paul Beesleyf8640672019-04-12 14:19:42 +01003011described in the :ref:`Interrupt Management Framework`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003012
3013A platform should export the following APIs to support the IMF. The following
Paul Beesley1fbc97b2019-01-11 18:26:51 +00003014text briefly describes each API and its implementation in Arm standard
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003015platforms. The API implementation depends upon the type of interrupt controller
Dan Handley610e7e12018-03-01 18:44:00 +00003016present in the platform. Arm standard platform layer supports both
3017`Arm Generic Interrupt Controller version 2.0 (GICv2)`_
3018and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the
3019FVP can be configured to use either GICv2 or GICv3 depending on the build flag
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01003020``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more
3021details).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003022
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05003023See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`.
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01003024
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003025Function : plat_interrupt_type_to_line() [mandatory]
3026~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003027
3028::
3029
3030 Argument : uint32_t, uint32_t
3031 Return : uint32_t
3032
Dan Handley610e7e12018-03-01 18:44:00 +00003033The Arm processor signals an interrupt exception either through the IRQ or FIQ
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003034interrupt line. The specific line that is signaled depends on how the interrupt
3035controller (IC) reports different interrupt types from an execution context in
3036either security state. The IMF uses this API to determine which interrupt line
3037the platform IC uses to signal each type of interrupt supported by the framework
3038from a given security state. This API must be invoked at EL3.
3039
3040The first parameter will be one of the ``INTR_TYPE_*`` values (see
Paul Beesleyf8640672019-04-12 14:19:42 +01003041:ref:`Interrupt Management Framework`) indicating the target type of the
3042interrupt, the second parameter is the security state of the originating
3043execution context. The return result is the bit position in the ``SCR_EL3``
3044register of the respective interrupt trap: IRQ=1, FIQ=2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003045
Dan Handley610e7e12018-03-01 18:44:00 +00003046In the case of Arm standard platforms using GICv2, S-EL1 interrupts are
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003047configured as FIQs and Non-secure interrupts as IRQs from either security
3048state.
3049
Dan Handley610e7e12018-03-01 18:44:00 +00003050In the case of Arm standard platforms using GICv3, the interrupt line to be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003051configured depends on the security state of the execution context when the
3052interrupt is signalled and are as follows:
3053
3054- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in
3055 NS-EL0/1/2 context.
3056- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ
3057 in the NS-EL0/1/2 context.
3058- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2
3059 context.
3060
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003061Function : plat_ic_get_pending_interrupt_type() [mandatory]
3062~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003063
3064::
3065
3066 Argument : void
3067 Return : uint32_t
3068
3069This API returns the type of the highest priority pending interrupt at the
3070platform IC. The IMF uses the interrupt type to retrieve the corresponding
3071handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt
3072pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``,
3073``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3.
3074
Dan Handley610e7e12018-03-01 18:44:00 +00003075In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003076Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of
3077the pending interrupt. The type of interrupt depends upon the id value as
3078follows.
3079
3080#. id < 1022 is reported as a S-EL1 interrupt
3081#. id = 1022 is reported as a Non-secure interrupt.
3082#. id = 1023 is reported as an invalid interrupt type.
3083
Dan Handley610e7e12018-03-01 18:44:00 +00003084In the case of Arm standard platforms using GICv3, the system register
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003085``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*,
3086is read to determine the id of the pending interrupt. The type of interrupt
3087depends upon the id value as follows.
3088
3089#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt
3090#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt.
3091#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type.
3092#. All other interrupt id's are reported as EL3 interrupt.
3093
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003094Function : plat_ic_get_pending_interrupt_id() [mandatory]
3095~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003096
3097::
3098
3099 Argument : void
3100 Return : uint32_t
3101
3102This API returns the id of the highest priority pending interrupt at the
3103platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt
3104pending.
3105
Dan Handley610e7e12018-03-01 18:44:00 +00003106In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003107Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the
3108pending interrupt. The id that is returned by API depends upon the value of
3109the id read from the interrupt controller as follows.
3110
3111#. id < 1022. id is returned as is.
3112#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register*
3113 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt.
3114 This id is returned by the API.
3115#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned.
3116
Dan Handley610e7e12018-03-01 18:44:00 +00003117In the case of Arm standard platforms using GICv3, if the API is invoked from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003118EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt
3119group 0 Register*, is read to determine the id of the pending interrupt. The id
3120that is returned by API depends upon the value of the id read from the
3121interrupt controller as follows.
3122
3123#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is.
3124#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system
3125 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1
3126 Register* is read to determine the id of the group 1 interrupt. This id
3127 is returned by the API as long as it is a valid interrupt id
3128#. If the id is any of the special interrupt identifiers,
3129 ``INTR_ID_UNAVAILABLE`` is returned.
3130
3131When the API invoked from S-EL1 for GICv3 systems, the id read from system
3132register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003133Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003134``INTR_ID_UNAVAILABLE`` is returned.
3135
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003136Function : plat_ic_acknowledge_interrupt() [mandatory]
3137~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003138
3139::
3140
3141 Argument : void
3142 Return : uint32_t
3143
3144This API is used by the CPU to indicate to the platform IC that processing of
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01003145the highest pending interrupt has begun. It should return the raw, unmodified
3146value obtained from the interrupt controller when acknowledging an interrupt.
3147The actual interrupt number shall be extracted from this raw value using the API
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05003148`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003149
Dan Handley610e7e12018-03-01 18:44:00 +00003150This function in Arm standard platforms using GICv2, reads the *Interrupt
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003151Acknowledge Register* (``GICC_IAR``). This changes the state of the highest
3152priority pending interrupt from pending to active in the interrupt controller.
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01003153It returns the value read from the ``GICC_IAR``, unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003154
Dan Handley610e7e12018-03-01 18:44:00 +00003155In the case of Arm standard platforms using GICv3, if the API is invoked
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003156from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt
3157Acknowledge Register group 0*. If the API is invoked from S-EL1, the function
3158reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register
3159group 1*. The read changes the state of the highest pending interrupt from
3160pending to active in the interrupt controller. The value read is returned
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01003161unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003162
3163The TSP uses this API to start processing of the secure physical timer
3164interrupt.
3165
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003166Function : plat_ic_end_of_interrupt() [mandatory]
3167~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003168
3169::
3170
3171 Argument : uint32_t
3172 Return : void
3173
3174This API is used by the CPU to indicate to the platform IC that processing of
3175the interrupt corresponding to the id (passed as the parameter) has
3176finished. The id should be the same as the id returned by the
3177``plat_ic_acknowledge_interrupt()`` API.
3178
Dan Handley610e7e12018-03-01 18:44:00 +00003179Arm standard platforms write the id to the *End of Interrupt Register*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003180(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1``
3181system register in case of GICv3 depending on where the API is invoked from,
3182EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt
3183controller.
3184
3185The TSP uses this API to finish processing of the secure physical timer
3186interrupt.
3187
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003188Function : plat_ic_get_interrupt_type() [mandatory]
3189~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003190
3191::
3192
3193 Argument : uint32_t
3194 Return : uint32_t
3195
3196This API returns the type of the interrupt id passed as the parameter.
3197``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid
3198interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is
3199returned depending upon how the interrupt has been configured by the platform
3200IC. This API must be invoked at EL3.
3201
Dan Handley610e7e12018-03-01 18:44:00 +00003202Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003203and Non-secure interrupts as Group1 interrupts. It reads the group value
3204corresponding to the interrupt id from the relevant *Interrupt Group Register*
3205(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt.
3206
Dan Handley610e7e12018-03-01 18:44:00 +00003207In the case of Arm standard platforms using GICv3, both the *Interrupt Group
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003208Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register*
3209(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured
3210as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt.
3211
Manish Pandey3161fa52022-11-02 16:30:09 +00003212Common helper functions
3213-----------------------
Govindraj Rajab6709b02023-02-21 17:43:55 +00003214Function : elx_panic()
3215~~~~~~~~~~~~~~~~~~~~~~
Manish Pandey3161fa52022-11-02 16:30:09 +00003216
Govindraj Rajab6709b02023-02-21 17:43:55 +00003217::
3218
3219 Argument : void
3220 Return : void
3221
3222This API is called from assembly files when reporting a critical failure
3223that has occured in lower EL and is been trapped in EL3. This call
3224**must not** return.
Manish Pandey3161fa52022-11-02 16:30:09 +00003225
Govindraj Rajaa796b1b2023-01-16 17:35:07 +00003226Function : el3_panic()
3227~~~~~~~~~~~~~~~~~~~~~~
Manish Pandey3161fa52022-11-02 16:30:09 +00003228
3229::
3230
3231 Argument : void
3232 Return : void
3233
3234This API is called from assembly files when encountering a critical failure that
Govindraj Rajaa796b1b2023-01-16 17:35:07 +00003235cannot be recovered from. This function assumes that it is invoked from a C
3236runtime environment i.e. valid stack exists. This call **must not** return.
Manish Pandey3161fa52022-11-02 16:30:09 +00003237
3238Function : panic()
3239~~~~~~~~~~~~~~~~~~
3240
3241::
3242
3243 Argument : void
3244 Return : void
3245
3246This API called from C files when encountering a critical failure that cannot
3247be recovered from. This function in turn prints backtrace (if enabled) and calls
Govindraj Rajaa796b1b2023-01-16 17:35:07 +00003248el3_panic(). This call **must not** return.
Manish Pandey3161fa52022-11-02 16:30:09 +00003249
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003250Crash Reporting mechanism (in BL31)
3251-----------------------------------
3252
3253BL31 implements a crash reporting mechanism which prints the various registers
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01003254of the CPU to enable quick crash analysis and debugging. This mechanism relies
Paul Beesley1fbc97b2019-01-11 18:26:51 +00003255on the platform implementing ``plat_crash_console_init``,
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01003256``plat_crash_console_putc`` and ``plat_crash_console_flush``.
3257
3258The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample
3259implementation of all of them. Platforms may include this file to their
3260makefiles in order to benefit from them. By default, they will cause the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07003261output to be routed over the normal console infrastructure and get printed on
3262consoles configured to output in crash state. ``console_set_scope()`` can be
3263used to control whether a console is used for crash output.
Paul Beesleyba3ed402019-03-13 16:20:44 +00003264
3265.. note::
3266 Platforms are responsible for making sure that they only mark consoles for
3267 use in the crash scope that are able to support this, i.e. that are written
3268 in assembly and conform with the register clobber rules for putc()
3269 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003270
Julius Werneraae9bb12017-09-18 16:49:48 -07003271In some cases (such as debugging very early crashes that happen before the
3272normal boot console can be set up), platforms may want to control crash output
Julius Werner1338c9c2018-11-19 14:25:55 -08003273more explicitly. These platforms may instead provide custom implementations for
3274these. They are executed outside of a C environment and without a stack. Many
3275console drivers provide functions named ``console_xxx_core_init/putc/flush``
3276that are designed to be used by these functions. See Arm platforms (like juno)
3277for an example of this.
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01003278
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003279Function : plat_crash_console_init [mandatory]
3280~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003281
3282::
3283
3284 Argument : void
3285 Return : int
3286
3287This API is used by the crash reporting mechanism to initialize the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07003288console. It must only use the general purpose registers x0 through x7 to do the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003289initialization and returns 1 on success.
3290
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003291Function : plat_crash_console_putc [mandatory]
3292~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003293
3294::
3295
3296 Argument : int
3297 Return : int
3298
3299This API is used by the crash reporting mechanism to print a character on the
3300designated crash console. It must only use general purpose registers x1 and
3301x2 to do its work. The parameter and the return value are in general purpose
3302register x0.
3303
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003304Function : plat_crash_console_flush [mandatory]
3305~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003306
3307::
3308
3309 Argument : void
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05003310 Return : void
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003311
3312This API is used by the crash reporting mechanism to force write of all buffered
3313data on the designated crash console. It should only use general purpose
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05003314registers x0 through x5 to do its work.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003315
Manish Pandey9c9f38a2020-06-30 00:46:08 +01003316.. _External Abort handling and RAS Support:
3317
Jeenu Viswambharane34bf582018-10-12 08:48:36 +01003318External Abort handling and RAS Support
3319---------------------------------------
Jeenu Viswambharanbf235bc2018-07-12 10:00:01 +01003320
3321Function : plat_ea_handler
3322~~~~~~~~~~~~~~~~~~~~~~~~~~
3323
3324::
3325
3326 Argument : int
3327 Argument : uint64_t
3328 Argument : void *
3329 Argument : void *
3330 Argument : uint64_t
3331 Return : void
3332
3333This function is invoked by the RAS framework for the platform to handle an
3334External Abort received at EL3. The intention of the function is to attempt to
3335resolve the cause of External Abort and return; if that's not possible, to
3336initiate orderly shutdown of the system.
3337
3338The first parameter (``int ea_reason``) indicates the reason for External Abort.
3339Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``.
3340
3341The second parameter (``uint64_t syndrome``) is the respective syndrome
3342presented to EL3 after having received the External Abort. Depending on the
3343nature of the abort (as can be inferred from the ``ea_reason`` parameter), this
3344can be the content of either ``ESR_EL3`` or ``DISR_EL1``.
3345
3346The third parameter (``void *cookie``) is unused for now. The fourth parameter
3347(``void *handle``) is a pointer to the preempted context. The fifth parameter
3348(``uint64_t flags``) indicates the preempted security state. These parameters
3349are received from the top-level exception handler.
3350
3351If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this
3352function iterates through RAS handlers registered by the platform. If any of the
3353RAS handlers resolve the External Abort, no further action is taken.
3354
3355If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers
3356could resolve the External Abort, the default implementation prints an error
3357message, and panics.
3358
3359Function : plat_handle_uncontainable_ea
3360~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3361
3362::
3363
3364 Argument : int
3365 Argument : uint64_t
3366 Return : void
3367
3368This function is invoked by the RAS framework when an External Abort of
3369Uncontainable type is received at EL3. Due to the critical nature of
3370Uncontainable errors, the intention of this function is to initiate orderly
3371shutdown of the system, and is not expected to return.
3372
3373This function must be implemented in assembly.
3374
3375The first and second parameters are the same as that of ``plat_ea_handler``.
3376
3377The default implementation of this function calls
3378``report_unhandled_exception``.
3379
3380Function : plat_handle_double_fault
3381~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3382
3383::
3384
3385 Argument : int
3386 Argument : uint64_t
3387 Return : void
3388
3389This function is invoked by the RAS framework when another External Abort is
3390received at EL3 while one is already being handled. I.e., a call to
3391``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of
3392this function is to initiate orderly shutdown of the system, and is not expected
3393recover or return.
3394
3395This function must be implemented in assembly.
3396
3397The first and second parameters are the same as that of ``plat_ea_handler``.
3398
3399The default implementation of this function calls
3400``report_unhandled_exception``.
3401
3402Function : plat_handle_el3_ea
3403~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3404
3405::
3406
3407 Return : void
3408
3409This function is invoked when an External Abort is received while executing in
3410EL3. Due to its critical nature, the intention of this function is to initiate
3411orderly shutdown of the system, and is not expected recover or return.
3412
3413This function must be implemented in assembly.
3414
3415The default implementation of this function calls
3416``report_unhandled_exception``.
3417
Andre Przywarabdc76f12022-11-21 17:07:25 +00003418Function : plat_handle_rng_trap
3419~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3420
3421::
3422
3423 Argument : uint64_t
3424 Argument : cpu_context_t *
3425 Return : int
3426
3427This function is invoked by BL31's exception handler when there is a synchronous
3428system register trap caused by access to the RNDR or RNDRRS registers. It allows
3429platforms implementing ``FEAT_RNG_TRAP`` and enabling ``ENABLE_FEAT_RNG_TRAP`` to
3430emulate those system registers by returing back some entropy to the lower EL.
3431
3432The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3
3433syndrome register, which encodes the instruction that was trapped. The interesting
3434information in there is the target register (``get_sysreg_iss_rt()``).
3435
3436The second parameter (``cpu_context_t *ctx``) represents the CPU state in the
3437lower exception level, at the time when the execution of the ``mrs`` instruction
3438was trapped. Its content can be changed, to put the entropy into the target
3439register.
3440
3441The return value indicates how to proceed:
3442
3443- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic.
3444- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return
3445 to the same instruction, so its execution will be repeated.
3446- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return
3447 to the next instruction.
3448
3449This function needs to be implemented by a platform if it enables FEAT_RNG_TRAP.
3450
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003451Build flags
3452-----------
3453
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003454There are some build flags which can be defined by the platform to control
3455inclusion or exclusion of certain BL stages from the FIP image. These flags
3456need to be defined in the platform makefile which will get included by the
3457build system.
3458
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003459- **NEED_BL33**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003460 By default, this flag is defined ``yes`` by the build system and ``BL33``
3461 build option should be supplied as a build option. The platform has the
3462 option of excluding the BL33 image in the ``fip`` image by defining this flag
3463 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE``
3464 are used, this flag will be set to ``no`` automatically.
3465
Paul Beesley07f0a312019-05-16 13:33:18 +01003466Platform include paths
3467----------------------
3468
3469Platforms are allowed to add more include paths to be passed to the compiler.
3470The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in
3471particular for the file ``platform_def.h``.
3472
3473Example:
3474
3475.. code:: c
3476
3477 PLAT_INCLUDES += -Iinclude/plat/myplat/include
3478
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003479C Library
3480---------
3481
3482To avoid subtle toolchain behavioral dependencies, the header files provided
3483by the compiler are not used. The software is built with the ``-nostdinc`` flag
3484to ensure no headers are included from the toolchain inadvertently. Instead the
Dan Handley610e7e12018-03-01 18:44:00 +00003485required headers are included in the TF-A source tree. The library only
3486contains those C library definitions required by the local implementation. If
3487more functionality is required, the needed library functions will need to be
3488added to the local implementation.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003489
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003490Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have
Paul Beesleyf2ec7142019-10-04 16:17:46 +00003491been written specifically for TF-A. Some implementation files have been obtained
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003492from `FreeBSD`_, others have been written specifically for TF-A as well. The
3493files can be found in ``include/lib/libc`` and ``lib/libc``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003494
Sandrine Bailleux6f0ecd72019-02-08 14:46:42 +01003495SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources
3496can be obtained from http://github.com/freebsd/freebsd.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003497
3498Storage abstraction layer
3499-------------------------
3500
Louis Mayencourtb5469002019-07-15 13:56:03 +01003501In order to improve platform independence and portability a storage abstraction
3502layer is used to load data from non-volatile platform storage. Currently
3503storage access is only required by BL1 and BL2 phases and performed inside the
3504``load_image()`` function in ``bl_common.c``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003505
Louis Mayencourtb5469002019-07-15 13:56:03 +01003506.. uml:: ../resources/diagrams/plantuml/io_framework_usage_overview.puml
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003507
Dan Handley610e7e12018-03-01 18:44:00 +00003508It is mandatory to implement at least one storage driver. For the Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003509development platforms the Firmware Image Package (FIP) driver is provided as
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01003510the default means to load data from storage (see :ref:`firmware_design_fip`).
3511The storage layer is described in the header file
3512``include/drivers/io/io_storage.h``. The implementation of the common library is
3513in ``drivers/io/io_storage.c`` and the driver files are located in
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003514``drivers/io/``.
3515
Louis Mayencourtb5469002019-07-15 13:56:03 +01003516.. uml:: ../resources/diagrams/plantuml/io_arm_class_diagram.puml
3517
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003518Each IO driver must provide ``io_dev_*`` structures, as described in
3519``drivers/io/io_driver.h``. These are returned via a mandatory registration
3520function that is called on platform initialization. The semi-hosting driver
3521implementation in ``io_semihosting.c`` can be used as an example.
3522
Louis Mayencourtb5469002019-07-15 13:56:03 +01003523Each platform should register devices and their drivers via the storage
3524abstraction layer. These drivers then need to be initialized by bootloader
3525phases as required in their respective ``blx_platform_setup()`` functions.
3526
3527.. uml:: ../resources/diagrams/plantuml/io_dev_registration.puml
3528
3529The storage abstraction layer provides mechanisms (``io_dev_init()``) to
3530initialize storage devices before IO operations are called.
3531
3532.. uml:: ../resources/diagrams/plantuml/io_dev_init_and_check.puml
3533
3534The basic operations supported by the layer
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003535include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``.
3536Drivers do not have to implement all operations, but each platform must
3537provide at least one driver for a device capable of supporting generic
3538operations such as loading a bootloader image.
3539
3540The current implementation only allows for known images to be loaded by the
3541firmware. These images are specified by using their identifiers, as defined in
Antonio Nino Diaz645feb42019-02-13 14:07:38 +00003542``include/plat/common/common_def.h`` (or a separate header file included from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003543there). The platform layer (``plat_get_image_source()``) then returns a reference
3544to a device and a driver-specific ``spec`` which will be understood by the driver
3545to allow access to the image data.
3546
3547The layer is designed in such a way that is it possible to chain drivers with
3548other drivers. For example, file-system drivers may be implemented on top of
3549physical block devices, both represented by IO devices with corresponding
3550drivers. In such a case, the file-system "binding" with the block device may
3551be deferred until the file-system device is initialised.
3552
3553The abstraction currently depends on structures being statically allocated
3554by the drivers and callers, as the system does not yet provide a means of
3555dynamically allocating memory. This may also have the affect of limiting the
3556amount of open resources per driver.
3557
3558--------------
3559
Chris Kay33bfc5e2023-02-14 11:30:04 +00003560*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003561
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003562.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
Dan Handley610e7e12018-03-01 18:44:00 +00003563.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003564.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html
Paul Beesley2437ddc2019-02-08 16:43:05 +00003565.. _FreeBSD: https://www.freebsd.org
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003566.. _SCC: http://www.simple-cc.org/
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +01003567.. _DRTM: https://developer.arm.com/documentation/den0113/a