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Ian Campbelld8e69e02014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Siva Durga Prasad Paladugu809438d2016-07-29 15:31:47 +05303config IDENT_STRING
4 default " Allwinner Technology"
5
Jagan Teki3994b1e2018-01-10 16:03:34 +05306config DRAM_SUN4I
7 bool
8 help
9 Select this dram controller driver for Sun4/5/7i platforms,
10 like A10/A13/A20.
11
Jagan Teki68d0f5f2018-03-17 00:16:36 +053012config DRAM_SUN6I
13 bool
14 help
15 Select this dram controller driver for Sun6i platforms,
16 like A31/A31s.
17
Jagan Teki318e4e52018-01-10 16:15:14 +053018config DRAM_SUN8I_A23
19 bool
20 help
21 Select this dram controller driver for Sun8i platforms,
22 for A23 SOC.
23
Jagan Tekie624d4c2018-01-10 16:17:39 +053024config DRAM_SUN8I_A33
25 bool
26 help
27 Select this dram controller driver for Sun8i platforms,
28 for A33 SOC.
29
Jagan Teki270a6f62018-01-10 16:20:26 +053030config DRAM_SUN8I_A83T
31 bool
32 help
33 Select this dram controller driver for Sun8i platforms,
34 for A83T SOC.
35
Jagan Teki6aa7f712018-03-17 00:18:01 +053036config DRAM_SUN9I
37 bool
38 help
39 Select this dram controller driver for Sun9i platforms,
40 like A80.
41
Icenowy Zheng4e287f62018-07-23 06:13:34 +080042config DRAM_SUN50I_H6
43 bool
44 help
45 Select this dram controller driver for some sun50i platforms,
46 like H6.
47
Jernej Skrabece4aa24b2021-01-11 21:11:43 +010048config DRAM_SUN50I_H616
49 bool
50 help
51 Select this dram controller driver for some sun50i platforms,
52 like H616.
53
54if DRAM_SUN50I_H616
Jernej Skrabecdd533da2023-04-10 10:21:12 +020055config DRAM_SUN50I_H616_DX_ODT
56 hex "H616 DRAM DX ODT parameter"
57 help
58 DX ODT value from vendor DRAM settings.
59
60config DRAM_SUN50I_H616_DX_DRI
61 hex "H616 DRAM DX DRI parameter"
62 help
63 DX DRI value from vendor DRAM settings.
64
65config DRAM_SUN50I_H616_CA_DRI
66 hex "H616 DRAM CA DRI parameter"
67 help
68 CA DRI value from vendor DRAM settings.
Jernej Skrabec6a6fe862023-04-10 10:21:13 +020069
Jernej Skrabec63ab9552023-04-10 10:21:16 +020070config DRAM_SUN50I_H616_ODT_EN
71 hex "H616 DRAM ODT EN parameter"
72 default 0x1
73 help
74 ODT EN value from vendor DRAM settings.
75
Jernej Skrabec9ec04b02023-04-10 10:21:17 +020076config DRAM_SUN50I_H616_TPR0
77 hex "H616 DRAM TPR0 parameter"
78 default 0x0
79 help
80 TPR0 value from vendor DRAM settings.
81
Jernej Skrabecac8154d2023-04-10 10:21:19 +020082config DRAM_SUN50I_H616_TPR2
83 hex "H616 DRAM TPR2 parameter"
84 default 0x0
85 help
86 TPR2 value from vendor DRAM settings.
87
Jernej Skrabec6a6fe862023-04-10 10:21:13 +020088config DRAM_SUN50I_H616_TPR10
89 hex "H616 DRAM TPR10 parameter"
90 help
91 TPR10 value from vendor DRAM settings. It tells which features
92 should be configured, like write leveling, read calibration, etc.
Jernej Skrabec63ab9552023-04-10 10:21:16 +020093
94config DRAM_SUN50I_H616_TPR11
95 hex "H616 DRAM TPR11 parameter"
96 default 0x0
97 help
98 TPR11 value from vendor DRAM settings.
99
100config DRAM_SUN50I_H616_TPR12
101 hex "H616 DRAM TPR12 parameter"
102 default 0x0
103 help
104 TPR12 value from vendor DRAM settings.
Jernej Skrabece4aa24b2021-01-11 21:11:43 +0100105endif
106
Jagan Teki932f5e02018-01-11 13:21:15 +0530107config SUN6I_PRCM
108 bool
109 help
110 Support for the PRCM (Power/Reset/Clock Management) unit available
111 in A31 SoC.
112
Jagan Tekifeb29272018-02-14 22:28:30 +0530113config AXP_PMIC_BUS
Samuel Holland623b8042021-10-08 00:17:19 -0500114 bool
Samuel Holland388fe642021-10-08 00:17:23 -0500115 select DM_PMIC if DM_I2C
116 select PMIC_AXP if DM_I2C
Jagan Tekifeb29272018-02-14 22:28:30 +0530117 help
118 Select this PMIC bus access helpers for Sunxi platform PRCM or other
119 AXP family PMIC devices.
120
Icenowy Zheng5e6dd272018-07-21 16:20:20 +0800121config SUNXI_SRAM_ADDRESS
122 hex
123 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
Andre Przywara068962b2022-10-05 17:54:19 +0100124 default 0x20000 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
Icenowy Zheng5e6dd272018-07-21 16:20:20 +0800125 default 0x0
Andre Przywarade454ec2017-02-16 01:20:23 +0000126 ---help---
127 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
128 with the first SRAM region being located at address 0.
129 Some newer SoCs map the boot ROM at address 0 instead and move the
Icenowy Zheng5e6dd272018-07-21 16:20:20 +0800130 SRAM to a different address.
Andre Przywarade454ec2017-02-16 01:20:23 +0000131
Andre Przywara0b5e4282022-12-08 20:33:57 +0000132config SUNXI_RVBAR_ADDRESS
133 hex
134 depends on ARM64
135 default 0x09010040 if SUN50I_GEN_H6
136 default 0x017000a0
137 ---help---
138 The read-only RVBAR system register holds the address of the first
139 instruction to execute after a reset. Allwinner cores provide a
140 writable MMIO backing store for this register, to allow to set the
141 entry point when switching to AArch64. This store is on different
142 addresses, depending on the SoC.
143
Andre Przywara710c7a22023-04-05 21:30:11 +0100144config SUNXI_RVBAR_ALTERNATIVE
145 hex
146 depends on ARM64
147 default 0x08100040 if MACH_SUN50I_H616
148 default SUNXI_RVBAR_ADDRESS
149 ---help---
150 The H616 die exists in at least two variants, with one having the
151 RVBAR registers at a different address. If the SoC variant ID
152 (stored in SRAM_VER_REG[7:0]) is not 0, we need to use the
153 other address.
154 Set this alternative address to the same as the normal address
155 for all other SoCs, so the content of the SRAM_VER_REG becomes
156 irrelevant there, and we can use the same code.
157
Andre Przywarad1de0bb2018-06-27 01:42:53 +0100158config SUNXI_A64_TIMER_ERRATUM
159 bool
160
Hans de Goedef07872b2015-04-06 20:33:34 +0200161# Note only one of these may be selected at a time! But hidden choices are
162# not supported by Kconfig
163config SUNXI_GEN_SUN4I
164 bool
165 ---help---
166 Select this for sunxi SoCs which have resets and clocks set up
167 as the original A10 (mach-sun4i).
168
169config SUNXI_GEN_SUN6I
170 bool
171 ---help---
172 Select this for sunxi SoCs which have sun6i like periphery, like
173 separate ahb reset control registers, custom pmic bus, new style
174 watchdog, etc.
175
Jernej Skrabecda8ae612021-01-11 21:11:34 +0100176config SUN50I_GEN_H6
177 bool
178 select FIT
179 select SPL_LOAD_FIT
Andre Przywarab8816f02021-05-05 10:04:41 +0100180 select MMC_SUNXI_HAS_NEW_MODE
Jernej Skrabecda8ae612021-01-11 21:11:34 +0100181 select SUPPORT_SPL
182 ---help---
183 Select this for sunxi SoCs which have H6 like peripherals, clocks
184 and memory map.
185
Andre Przywara068962b2022-10-05 17:54:19 +0100186config SUNXI_GEN_NCAT2
187 bool
188 select MMC_SUNXI_HAS_NEW_MODE
189 select SUPPORT_SPL
190 ---help---
191 Select this for sunxi SoCs which have D1 like peripherals, clocks
192 and memory map.
193
Icenowy Zhengca0bc022017-06-03 17:10:14 +0800194config SUNXI_DRAM_DW
195 bool
196 ---help---
197 Select this for sunxi SoCs which uses a DRAM controller like the
198 DesignWare controller used in H3, mainly SoCs after H3, which do
199 not have official open-source DRAM initialization code, but can
200 use modified H3 DRAM initialization code.
Hans de Goedef07872b2015-04-06 20:33:34 +0200201
Icenowy Zhengb2607512017-06-03 17:10:16 +0800202if SUNXI_DRAM_DW
203config SUNXI_DRAM_DW_16BIT
204 bool
205 ---help---
206 Select this for sunxi SoCs with DesignWare DRAM controller and
207 have only 16-bit memory buswidth.
208
209config SUNXI_DRAM_DW_32BIT
210 bool
211 ---help---
212 Select this for sunxi SoCs with DesignWare DRAM controller with
213 32-bit memory buswidth.
214endif
215
Andre Przywara5fb97432017-02-16 01:20:27 +0000216config MACH_SUNXI_H3_H5
217 bool
Jernej Skrabec9b4ca922017-03-27 19:22:31 +0200218 select SUNXI_DE2
Icenowy Zhengca0bc022017-06-03 17:10:14 +0800219 select SUNXI_DRAM_DW
Icenowy Zhengb2607512017-06-03 17:10:16 +0800220 select SUNXI_DRAM_DW_32BIT
Andre Przywara5fb97432017-02-16 01:20:27 +0000221 select SUNXI_GEN_SUN6I
222 select SUPPORT_SPL
223
Icenowy Zheng14170a42018-10-25 17:23:06 +0800224# TODO: try out A80's 8GiB DRAM space
225config SUNXI_DRAM_MAX_SIZE
226 hex
Andre Przywarac0387f12021-04-28 21:29:55 +0100227 default 0x100000000 if MACH_SUN50I_H616
228 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
Icenowy Zheng14170a42018-10-25 17:23:06 +0800229 default 0x80000000
230
Ian Campbelld8e69e02014-10-24 21:20:44 +0100231choice
232 prompt "Sunxi SoC Variant"
Hans de Goedeb05a6482016-06-12 11:57:07 +0200233 optional
Ian Campbelld8e69e02014-10-24 21:20:44 +0100234
Icenowy Zheng8f2d1c02022-01-29 10:23:07 -0500235config MACH_SUNIV
236 bool "suniv (Allwinner F1C100s/F1C200s/F1C600/R6)"
237 select CPU_ARM926EJS
238 select SUNXI_GEN_SUN6I
239 select SUPPORT_SPL
Andre Przywaracfacdfa2022-10-05 23:19:28 +0100240 select SKIP_LOWLEVEL_INIT_ONLY
241 select SPL_SKIP_LOWLEVEL_INIT_ONLY
Icenowy Zheng8f2d1c02022-01-29 10:23:07 -0500242
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100243config MACH_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +0100244 bool "sun4i (Allwinner A10)"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530245 select CPU_V7A
Jagan Teki3994b1e2018-01-10 16:03:34 +0530246 select DRAM_SUN4I
Hans de Goedef07872b2015-04-06 20:33:34 +0200247 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +0100248 select SUPPORT_SPL
Tom Rini52b2e262021-08-18 23:12:24 -0400249 imply SPL_SYS_I2C_LEGACY
250 imply SYS_I2C_LEGACY
Ian Campbelld8e69e02014-10-24 21:20:44 +0100251
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100252config MACH_SUN5I
Ian Campbelld8e69e02014-10-24 21:20:44 +0100253 bool "sun5i (Allwinner A13)"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530254 select CPU_V7A
Jagan Teki3994b1e2018-01-10 16:03:34 +0530255 select DRAM_SUN4I
Hans de Goedef07872b2015-04-06 20:33:34 +0200256 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +0100257 select SUPPORT_SPL
Tom Rini52b2e262021-08-18 23:12:24 -0400258 imply SPL_SYS_I2C_LEGACY
259 imply SYS_I2C_LEGACY
Ian Campbelld8e69e02014-10-24 21:20:44 +0100260
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100261config MACH_SUN6I
Ian Campbelld8e69e02014-10-24 21:20:44 +0100262 bool "sun6i (Allwinner A31)"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530263 select CPU_V7A
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +0800264 select CPU_V7_HAS_NONSEC
265 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +0900266 select ARCH_SUPPORT_PSCI
Andre Przywara5fc25562022-01-23 00:27:19 +0000267 select SPL_ARMV7_SET_CORTEX_SMPEN
Jagan Teki68d0f5f2018-03-17 00:16:36 +0530268 select DRAM_SUN6I
Samuel Holland60d49282021-10-08 00:17:20 -0500269 select SPL_I2C
Jagan Teki932f5e02018-01-11 13:21:15 +0530270 select SUN6I_PRCM
Hans de Goedef07872b2015-04-06 20:33:34 +0200271 select SUNXI_GEN_SUN6I
Hans de Goedea5403b92014-10-25 20:18:10 +0200272 select SUPPORT_SPL
Samuel Holland60d49282021-10-08 00:17:20 -0500273 select SYS_I2C_SUN6I_P2WI
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +0800274 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +0100275
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100276config MACH_SUN7I
Ian Campbelld8e69e02014-10-24 21:20:44 +0100277 bool "sun7i (Allwinner A20)"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530278 select CPU_V7A
Hans de Goede85437352014-11-14 09:34:30 +0100279 select CPU_V7_HAS_NONSEC
280 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +0900281 select ARCH_SUPPORT_PSCI
Andre Przywara5fc25562022-01-23 00:27:19 +0000282 select SPL_ARMV7_SET_CORTEX_SMPEN
Jagan Teki3994b1e2018-01-10 16:03:34 +0530283 select DRAM_SUN4I
Hans de Goedef07872b2015-04-06 20:33:34 +0200284 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +0100285 select SUPPORT_SPL
Hans de Goedea5636382014-10-24 20:12:04 +0200286 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Tom Rini52b2e262021-08-18 23:12:24 -0400287 imply SPL_SYS_I2C_LEGACY
288 imply SYS_I2C_LEGACY
Ian Campbelld8e69e02014-10-24 21:20:44 +0100289
Hans de Goedef055ed62015-04-06 20:55:39 +0200290config MACH_SUN8I_A23
Ian Campbelld8e69e02014-10-24 21:20:44 +0100291 bool "sun8i (Allwinner A23)"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530292 select CPU_V7A
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +0800293 select CPU_V7_HAS_NONSEC
294 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +0900295 select ARCH_SUPPORT_PSCI
Jagan Teki318e4e52018-01-10 16:15:14 +0530296 select DRAM_SUN8I_A23
Samuel Hollandb348efb2021-10-08 00:17:21 -0500297 select SPL_I2C
Hans de Goedef07872b2015-04-06 20:33:34 +0200298 select SUNXI_GEN_SUN6I
Hans de Goede966d2392014-12-07 14:34:27 +0100299 select SUPPORT_SPL
Samuel Hollandb348efb2021-10-08 00:17:21 -0500300 select SYS_I2C_SUN8I_RSB
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +0800301 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +0100302
Vishnu Patekar3702f142015-03-01 23:47:48 +0530303config MACH_SUN8I_A33
304 bool "sun8i (Allwinner A33)"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530305 select CPU_V7A
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +0800306 select CPU_V7_HAS_NONSEC
307 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +0900308 select ARCH_SUPPORT_PSCI
Jagan Tekie624d4c2018-01-10 16:17:39 +0530309 select DRAM_SUN8I_A33
Samuel Hollandb348efb2021-10-08 00:17:21 -0500310 select SPL_I2C
Vishnu Patekar3702f142015-03-01 23:47:48 +0530311 select SUNXI_GEN_SUN6I
312 select SUPPORT_SPL
Samuel Hollandb348efb2021-10-08 00:17:21 -0500313 select SYS_I2C_SUN8I_RSB
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +0800314 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar3702f142015-03-01 23:47:48 +0530315
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800316config MACH_SUN8I_A83T
317 bool "sun8i (Allwinner A83T)"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530318 select CPU_V7A
Jagan Teki270a6f62018-01-10 16:20:26 +0530319 select DRAM_SUN8I_A83T
Samuel Hollandb348efb2021-10-08 00:17:21 -0500320 select SPL_I2C
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800321 select SUNXI_GEN_SUN6I
Maxime Ripard4799a1a2017-08-23 12:03:42 +0200322 select MMC_SUNXI_HAS_NEW_MODE
Vasily Khoruzhickb198e2c2018-11-09 20:41:44 -0800323 select MMC_SUNXI_HAS_MODE_SWITCH
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800324 select SUPPORT_SPL
Samuel Hollandb348efb2021-10-08 00:17:21 -0500325 select SYS_I2C_SUN8I_RSB
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800326
Jens Kuskef9770722015-11-17 15:12:58 +0100327config MACH_SUN8I_H3
328 bool "sun8i (Allwinner H3)"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530329 select CPU_V7A
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +0800330 select CPU_V7_HAS_NONSEC
331 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +0900332 select ARCH_SUPPORT_PSCI
Andre Przywara5fb97432017-02-16 01:20:27 +0000333 select MACH_SUNXI_H3_H5
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +0800334 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuskef9770722015-11-17 15:12:58 +0100335
Chen-Yu Tsaicc2605e2016-11-30 14:57:32 +0800336config MACH_SUN8I_R40
337 bool "sun8i (Allwinner R40)"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530338 select CPU_V7A
Chen-Yu Tsaib1a1fda2017-03-01 11:03:15 +0800339 select CPU_V7_HAS_NONSEC
340 select CPU_V7_HAS_VIRT
341 select ARCH_SUPPORT_PSCI
Chen-Yu Tsaicc2605e2016-11-30 14:57:32 +0800342 select SUNXI_GEN_SUN6I
Andre Przywarab8816f02021-05-05 10:04:41 +0100343 select MMC_SUNXI_HAS_NEW_MODE
Chen-Yu Tsai2d5826c2016-12-02 16:09:49 +0800344 select SUPPORT_SPL
Icenowy Zhengca0bc022017-06-03 17:10:14 +0800345 select SUNXI_DRAM_DW
Icenowy Zhengb2607512017-06-03 17:10:16 +0800346 select SUNXI_DRAM_DW_32BIT
Tom Rini52b2e262021-08-18 23:12:24 -0400347 imply SPL_SYS_I2C_LEGACY
Chen-Yu Tsaicc2605e2016-11-30 14:57:32 +0800348
Icenowy Zheng52e61882017-04-08 15:30:12 +0800349config MACH_SUN8I_V3S
Icenowy Zheng7df99102020-10-26 22:15:59 +0800350 bool "sun8i (Allwinner V3/V3s/S3/S3L)"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530351 select CPU_V7A
Icenowy Zheng52e61882017-04-08 15:30:12 +0800352 select CPU_V7_HAS_NONSEC
353 select CPU_V7_HAS_VIRT
354 select ARCH_SUPPORT_PSCI
355 select SUNXI_GEN_SUN6I
Icenowy Zhengb54209f2017-06-03 17:10:22 +0800356 select SUNXI_DRAM_DW
357 select SUNXI_DRAM_DW_16BIT
358 select SUPPORT_SPL
Icenowy Zheng52e61882017-04-08 15:30:12 +0800359 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
360
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100361config MACH_SUN9I
362 bool "sun9i (Allwinner A80)"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530363 select CPU_V7A
Andre Przywara5fc25562022-01-23 00:27:19 +0000364 select SPL_ARMV7_SET_CORTEX_SMPEN
Jagan Teki6aa7f712018-03-17 00:18:01 +0530365 select DRAM_SUN9I
Samuel Hollandb348efb2021-10-08 00:17:21 -0500366 select SPL_I2C
Jagan Teki11f33e12018-01-11 13:23:02 +0530367 select SUN6I_PRCM
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100368 select SUNXI_GEN_SUN6I
Philipp Tomsich470626e2016-10-28 18:21:32 +0800369 select SUPPORT_SPL
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100370
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800371config MACH_SUN50I
372 bool "sun50i (Allwinner A64)"
373 select ARM64
Vasily Khoruzhick6f4c3442018-11-05 20:24:30 -0800374 select SUN6I_PRCM
Jernej Skrabec9b4ca922017-03-27 19:22:31 +0200375 select SUNXI_DE2
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800376 select SUNXI_GEN_SUN6I
Vasily Khoruzhicka4e8dd92018-11-09 20:41:46 -0800377 select MMC_SUNXI_HAS_NEW_MODE
Andre Przywaraa563adc2017-01-02 11:48:45 +0000378 select SUPPORT_SPL
Icenowy Zhengca0bc022017-06-03 17:10:14 +0800379 select SUNXI_DRAM_DW
Icenowy Zhengb2607512017-06-03 17:10:16 +0800380 select SUNXI_DRAM_DW_32BIT
Andre Przywarad8362162017-04-26 01:32:48 +0100381 select FIT
382 select SPL_LOAD_FIT
Andre Przywarad1de0bb2018-06-27 01:42:53 +0100383 select SUNXI_A64_TIMER_ERRATUM
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800384
Andre Przywara5611a2d2017-02-16 01:20:28 +0000385config MACH_SUN50I_H5
386 bool "sun50i (Allwinner H5)"
387 select ARM64
388 select MACH_SUNXI_H3_H5
Andre Przywarab8816f02021-05-05 10:04:41 +0100389 select MMC_SUNXI_HAS_NEW_MODE
Andre Przywarad8362162017-04-26 01:32:48 +0100390 select FIT
391 select SPL_LOAD_FIT
Andre Przywara5611a2d2017-02-16 01:20:28 +0000392
Icenowy Zheng0c01b962018-07-21 16:20:31 +0800393config MACH_SUN50I_H6
394 bool "sun50i (Allwinner H6)"
395 select ARM64
Icenowy Zheng0c01b962018-07-21 16:20:31 +0800396 select DRAM_SUN50I_H6
Jernej Skrabecda8ae612021-01-11 21:11:34 +0100397 select SUN50I_GEN_H6
Icenowy Zheng0c01b962018-07-21 16:20:31 +0800398
Jernej Skrabece638e052021-01-11 21:11:46 +0100399config MACH_SUN50I_H616
400 bool "sun50i (Allwinner H616)"
401 select ARM64
402 select DRAM_SUN50I_H616
403 select SUN50I_GEN_H6
404
Ian Campbelld8e69e02014-10-24 21:20:44 +0100405endchoice
Maxime Ripard2c519412014-10-03 20:16:29 +0800406
Hans de Goedef055ed62015-04-06 20:55:39 +0200407# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
408config MACH_SUN8I
409 bool
Andre Przywara5fc25562022-01-23 00:27:19 +0000410 select SPL_ARMV7_SET_CORTEX_SMPEN if !ARM64
Jagan Teki11f33e12018-01-11 13:23:02 +0530411 select SUN6I_PRCM
Chen-Yu Tsaifa337462017-03-02 16:03:06 +0800412 default y if MACH_SUN8I_A23
413 default y if MACH_SUN8I_A33
414 default y if MACH_SUN8I_A83T
415 default y if MACH_SUNXI_H3_H5
Chen-Yu Tsaicc2605e2016-11-30 14:57:32 +0800416 default y if MACH_SUN8I_R40
Icenowy Zheng52e61882017-04-08 15:30:12 +0800417 default y if MACH_SUN8I_V3S
Hans de Goedef055ed62015-04-06 20:55:39 +0200418
Andre Przywara06893b62017-01-02 11:48:35 +0000419config RESERVE_ALLWINNER_BOOT0_HEADER
420 bool "reserve space for Allwinner boot0 header"
421 select ENABLE_ARM_SOC_BOOT0_HOOK
422 ---help---
423 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
424 filled with magic values post build. The Allwinner provided boot0
425 blob relies on this information to load and execute U-Boot.
426 Only needed on 64-bit Allwinner boards so far when using boot0.
427
Andre Przywara46c3d992017-01-02 11:48:36 +0000428config ARM_BOOT_HOOK_RMR
429 bool
430 depends on ARM64
431 default y
432 select ENABLE_ARM_SOC_BOOT0_HOOK
433 ---help---
434 Insert some ARM32 code at the very beginning of the U-Boot binary
435 which uses an RMR register write to bring the core into AArch64 mode.
436 The very first instruction acts as a switch, since it's carefully
437 chosen to be a NOP in one mode and a branch in the other, so the
438 code would only be executed if not already in AArch64.
439 This allows both the SPL and the U-Boot proper to be entered in
440 either mode and switch to AArch64 if needed.
441
Mikhail Kalashnikov001d2f52023-06-07 01:07:44 +0100442if SUNXI_DRAM_DW || DRAM_SUN50I_H6 || DRAM_SUN50I_H616
Icenowy Zhengf09b48e2017-06-03 17:10:18 +0800443config SUNXI_DRAM_DDR3
444 bool
445
Icenowy Zhenge270a582017-06-03 17:10:20 +0800446config SUNXI_DRAM_DDR2
447 bool
448
Icenowy Zheng3c1b9f12017-06-03 17:10:23 +0800449config SUNXI_DRAM_LPDDR3
450 bool
451
Icenowy Zhengf09b48e2017-06-03 17:10:18 +0800452choice
453 prompt "DRAM Type and Timing"
Icenowy Zhengfe052172017-06-03 17:10:21 +0800454 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
455 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
Icenowy Zhengf09b48e2017-06-03 17:10:18 +0800456
457config SUNXI_DRAM_DDR3_1333
458 bool "DDR3 1333"
459 select SUNXI_DRAM_DDR3
460 ---help---
461 This option is the original only supported memory type, which suits
462 many H3/H5/A64 boards available now.
463
Icenowy Zhengeb4766e2017-06-03 17:10:24 +0800464config SUNXI_DRAM_LPDDR3_STOCK
465 bool "LPDDR3 with Allwinner stock configuration"
466 select SUNXI_DRAM_LPDDR3
467 ---help---
468 This option is the LPDDR3 timing used by the stock boot0 by
469 Allwinner.
470
Andre Przywara1c7a7512019-07-15 02:27:06 +0100471config SUNXI_DRAM_H6_LPDDR3
472 bool "LPDDR3 DRAM chips on the H6 DRAM controller"
473 select SUNXI_DRAM_LPDDR3
474 depends on DRAM_SUN50I_H6
475 ---help---
476 This option is the LPDDR3 timing used by the stock boot0 by
477 Allwinner.
478
Andre Przywara75d38d02019-07-15 02:27:08 +0100479config SUNXI_DRAM_H6_DDR3_1333
480 bool "DDR3-1333 boot0 timings on the H6 DRAM controller"
481 select SUNXI_DRAM_DDR3
482 depends on DRAM_SUN50I_H6
483 ---help---
484 This option is the DDR3 timing used by the boot0 on H6 TV boxes
485 which use a DDR3-1333 timing.
486
Mikhail Kalashnikovcfce8e42023-06-07 01:07:45 +0100487config SUNXI_DRAM_H616_LPDDR3
488 bool "LPDDR3 DRAM chips on the H616 DRAM controller"
489 select SUNXI_DRAM_LPDDR3
490 depends on DRAM_SUN50I_H616
491 help
492 This option is the LPDDR3 timing used by the stock boot0 by
493 Allwinner.
494
Mikhail Kalashnikov001d2f52023-06-07 01:07:44 +0100495config SUNXI_DRAM_H616_DDR3_1333
496 bool "DDR3-1333 boot0 timings on the H616 DRAM controller"
497 select SUNXI_DRAM_DDR3
498 depends on DRAM_SUN50I_H616
499 help
500 This option is the DDR3 timing used by the boot0 on H616 TV boxes
501 which use a DDR3-1333 timing.
502
Icenowy Zhenge270a582017-06-03 17:10:20 +0800503config SUNXI_DRAM_DDR2_V3S
504 bool "DDR2 found in V3s chip"
505 select SUNXI_DRAM_DDR2
Icenowy Zhengfe052172017-06-03 17:10:21 +0800506 depends on MACH_SUN8I_V3S
Icenowy Zhenge270a582017-06-03 17:10:20 +0800507 ---help---
508 This option is only for the DDR2 memory chip which is co-packaged in
509 Allwinner V3s SoC.
510
Icenowy Zhengf09b48e2017-06-03 17:10:18 +0800511endchoice
512endif
513
Vishnu Patekarc49936f2016-01-12 01:20:58 +0800514config DRAM_TYPE
515 int "sunxi dram type"
516 depends on MACH_SUN8I_A83T
517 default 3
518 ---help---
519 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goedef055ed62015-04-06 20:55:39 +0200520
Hans de Goede3aeaa282014-11-15 19:46:39 +0100521config DRAM_CLK
Hans de Goede59d9fc72015-01-17 14:24:55 +0100522 int "sunxi dram clock speed"
Philipp Tomsichd36af1c2016-10-28 18:21:28 +0800523 default 792 if MACH_SUN9I
Chen-Yu Tsaif361d562016-11-30 16:58:35 +0800524 default 648 if MACH_SUN8I_R40
Hans de Goede59d9fc72015-01-17 14:24:55 +0100525 default 312 if MACH_SUN6I || MACH_SUN8I
Icenowy Zhengb54209f2017-06-03 17:10:22 +0800526 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
527 MACH_SUN8I_V3S
Andre Przywaraafd68702017-01-02 11:48:37 +0000528 default 672 if MACH_SUN50I
Icenowy Zheng0c01b962018-07-21 16:20:31 +0800529 default 744 if MACH_SUN50I_H6
Jernej Skrabece4aa24b2021-01-11 21:11:43 +0100530 default 720 if MACH_SUN50I_H616
Hans de Goede3aeaa282014-11-15 19:46:39 +0100531 ---help---
Philipp Tomsichd36af1c2016-10-28 18:21:28 +0800532 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
533 must be a multiple of 24. For the sun9i (A80), the tested values
534 (for DDR3-1600) are 312 to 792.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100535
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200536if MACH_SUN5I || MACH_SUN7I
537config DRAM_MBUS_CLK
538 int "sunxi mbus clock speed"
539 default 300
540 ---help---
541 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
542
543endif
544
Hans de Goede3aeaa282014-11-15 19:46:39 +0100545config DRAM_ZQ
Hans de Goede59d9fc72015-01-17 14:24:55 +0100546 int "sunxi dram zq value"
Jernej Skrabece4aa24b2021-01-11 21:11:43 +0100547 depends on !MACH_SUN50I_H616
Paul Kocialkowski70373ca2019-03-14 11:36:14 +0100548 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
Paul Kocialkowski4d492a32019-03-14 11:36:15 +0100549 MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
Hans de Goede59d9fc72015-01-17 14:24:55 +0100550 default 127 if MACH_SUN7I
Icenowy Zhengb54209f2017-06-03 17:10:22 +0800551 default 14779 if MACH_SUN8I_V3S
Paul Kocialkowski4d492a32019-03-14 11:36:15 +0100552 default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
Chen-Yu Tsai47bb3062016-10-28 18:21:36 +0800553 default 4145117 if MACH_SUN9I
Andre Przywaraafd68702017-01-02 11:48:37 +0000554 default 3881915 if MACH_SUN50I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100555 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100556 Set the dram zq value.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100557
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200558config DRAM_ODT_EN
559 bool "sunxi dram odt enable"
Jernej Skrabec64712da2023-04-10 10:21:14 +0200560 depends on !MACH_SUN50I_H616
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200561 default y if MACH_SUN8I_A23
Paul Kocialkowskid6c5cfc2019-03-14 11:36:16 +0100562 default y if MACH_SUNXI_H3_H5
Chen-Yu Tsaif361d562016-11-30 16:58:35 +0800563 default y if MACH_SUN8I_R40
Andre Przywaraa563adc2017-01-02 11:48:45 +0000564 default y if MACH_SUN50I
Icenowy Zheng0c01b962018-07-21 16:20:31 +0800565 default y if MACH_SUN50I_H6
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200566 ---help---
567 Select this to enable dram odt (on die termination).
568
Hans de Goede59d9fc72015-01-17 14:24:55 +0100569if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
570config DRAM_EMR1
571 int "sunxi dram emr1 value"
572 default 0 if MACH_SUN4I
573 default 4 if MACH_SUN5I || MACH_SUN7I
574 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100575 Set the dram controller emr1 value.
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200576
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200577config DRAM_TPR3
578 hex "sunxi dram tpr3 value"
Tom Rinif18679c2023-08-02 11:09:43 -0400579 default 0x0
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200580 ---help---
581 Set the dram controller tpr3 parameter. This parameter configures
582 the delay on the command lane and also phase shifts, which are
583 applied for sampling incoming read data. The default value 0
584 means that no phase/delay adjustments are necessary. Properly
585 configuring this parameter increases reliability at high DRAM
586 clock speeds.
587
588config DRAM_DQS_GATING_DELAY
589 hex "sunxi dram dqs_gating_delay value"
Tom Rinif18679c2023-08-02 11:09:43 -0400590 default 0x0
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200591 ---help---
592 Set the dram controller dqs_gating_delay parmeter. Each byte
593 encodes the DQS gating delay for each byte lane. The delay
594 granularity is 1/4 cycle. For example, the value 0x05060606
595 means that the delay is 5 quarter-cycles for one lane (1.25
596 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
597 The default value 0 means autodetection. The results of hardware
598 autodetection are not very reliable and depend on the chip
599 temperature (sometimes producing different results on cold start
600 and warm reboot). But the accuracy of hardware autodetection
601 is usually good enough, unless running at really high DRAM
602 clocks speeds (up to 600MHz). If unsure, keep as 0.
603
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200604choice
605 prompt "sunxi dram timings"
606 default DRAM_TIMINGS_VENDOR_MAGIC
607 ---help---
608 Select the timings of the DDR3 chips.
609
610config DRAM_TIMINGS_VENDOR_MAGIC
611 bool "Magic vendor timings from Android"
612 ---help---
613 The same DRAM timings as in the Allwinner boot0 bootloader.
614
615config DRAM_TIMINGS_DDR3_1066F_1333H
616 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
617 ---help---
618 Use the timings of the standard JEDEC DDR3-1066F speed bin for
619 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
620 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
621 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
622 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
623 that down binning to DDR3-1066F is supported (because DDR3-1066F
624 uses a bit faster timings than DDR3-1333H).
625
626config DRAM_TIMINGS_DDR3_800E_1066G_1333J
627 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
628 ---help---
629 Use the timings of the slowest possible JEDEC speed bin for the
630 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
631 DDR3-800E, DDR3-1066G or DDR3-1333J.
632
633endchoice
634
Hans de Goede3aeaa282014-11-15 19:46:39 +0100635endif
636
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200637if MACH_SUN8I_A23
638config DRAM_ODT_CORRECTION
639 int "sunxi dram odt correction value"
640 default 0
641 ---help---
642 Set the dram odt correction value (range -255 - 255). In allwinner
643 fex files, this option is found in bits 8-15 of the u32 odt_en variable
644 in the [dram] section. When bit 31 of the odt_en variable is set
645 then the correction is negative. Usually the value for this is 0.
646endif
647
Iain Paton630df142015-03-28 10:26:38 +0000648config SYS_CLK_FREQ
Icenowy Zheng8f2d1c02022-01-29 10:23:07 -0500649 default 408000000 if MACH_SUNIV
Chen-Yu Tsaifa337462017-03-02 16:03:06 +0800650 default 1008000000 if MACH_SUN4I
651 default 1008000000 if MACH_SUN5I
652 default 1008000000 if MACH_SUN6I
Iain Paton630df142015-03-28 10:26:38 +0000653 default 912000000 if MACH_SUN7I
Icenowy Zheng2e915b42017-10-31 07:36:28 +0800654 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
Chen-Yu Tsaifa337462017-03-02 16:03:06 +0800655 default 1008000000 if MACH_SUN8I
656 default 1008000000 if MACH_SUN9I
Icenowy Zheng0c01b962018-07-21 16:20:31 +0800657 default 888000000 if MACH_SUN50I_H6
Jernej Skrabece638e052021-01-11 21:11:46 +0100658 default 1008000000 if MACH_SUN50I_H616
Iain Paton630df142015-03-28 10:26:38 +0000659
Maxime Ripard2c519412014-10-03 20:16:29 +0800660config SYS_CONFIG_NAME
Icenowy Zheng8f2d1c02022-01-29 10:23:07 -0500661 default "suniv" if MACH_SUNIV
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100662 default "sun4i" if MACH_SUN4I
663 default "sun5i" if MACH_SUN5I
664 default "sun6i" if MACH_SUN6I
665 default "sun7i" if MACH_SUN7I
666 default "sun8i" if MACH_SUN8I
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100667 default "sun9i" if MACH_SUN9I
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200668 default "sun50i" if MACH_SUN50I
Icenowy Zheng0c01b962018-07-21 16:20:31 +0800669 default "sun50i" if MACH_SUN50I_H6
Jernej Skrabece638e052021-01-11 21:11:46 +0100670 default "sun50i" if MACH_SUN50I_H616
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900671
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900672config SYS_BOARD
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900673 default "sunxi"
674
675config SYS_SOC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900676 default "sunxi"
677
Andre Przywaraa2860fb2022-07-03 00:47:20 +0100678config SUNXI_MINIMUM_DRAM_MB
679 int "minimum DRAM size"
680 default 32 if MACH_SUNIV
681 default 64 if MACH_SUN8I_V3S
682 default 256
683 ---help---
684 Minimum DRAM size expected on the board. Traditionally we assumed
685 256 MB, so that U-Boot would load at 160MB. With co-packaged DRAM
686 we have smaller sizes, though, so that U-Boot's own load address and
687 the default payload addresses must be shifted down.
688 This is expected to be fixed by the SoC selection.
689
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200690config UART0_PORT_F
691 bool "UART0 on MicroSD breakout board"
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200692 ---help---
693 Repurpose the SD card slot for getting access to the UART0 serial
694 console. Primarily useful only for low level u-boot debugging on
695 tablets, where normal UART0 is difficult to access and requires
696 device disassembly and/or soldering. As the SD card can't be used
697 at the same time, the system can be only booted in the FEL mode.
698 Only enable this if you really know what you are doing.
699
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200700config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900701 bool "Enable workarounds for booting old kernels"
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200702 ---help---
703 Set this to enable various workarounds for old kernels, this results in
704 sub-optimal settings for newer kernels, only enable if needed.
705
Samuel Holland51951052021-09-12 10:28:35 -0500706config MMC1_PINS_PH
707 bool "Pins for mmc1 are on Port H"
708 depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100709 ---help---
Samuel Holland51951052021-09-12 10:28:35 -0500710 Select this option for boards where mmc1 uses the Port H pinmux.
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100711
Hans de Goedeaf593e42014-10-02 20:43:50 +0200712config MMC_SUNXI_SLOT_EXTRA
713 int "mmc extra slot number"
714 default -1
715 ---help---
716 sunxi builds always enable mmc0, some boards also have a second sdcard
717 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
718 support for this.
719
Hans de Goedee7b852a2015-01-07 15:26:06 +0100720config USB0_VBUS_PIN
721 string "Vbus enable pin for usb0 (otg)"
722 default ""
723 ---help---
724 Set the Vbus enable pin for usb0 (otg). This takes a string in the
725 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
726
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100727config USB0_VBUS_DET
728 string "Vbus detect pin for usb0 (otg)"
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100729 default ""
730 ---help---
731 Set the Vbus detect pin for usb0 (otg). This takes a string in the
732 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
733
Hans de Goedeaadd97f2015-06-14 17:29:53 +0200734config USB0_ID_DET
735 string "ID detect pin for usb0 (otg)"
736 default ""
737 ---help---
738 Set the ID detect pin for usb0 (otg). This takes a string in the
739 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
740
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100741config USB1_VBUS_PIN
742 string "Vbus enable pin for usb1 (ehci0)"
743 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100744 default "PH27" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100745 ---help---
746 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
747 a string in the format understood by sunxi_name_to_gpio, e.g.
748 PH1 for pin 1 of port H.
749
750config USB2_VBUS_PIN
751 string "Vbus enable pin for usb2 (ehci1)"
752 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100753 default "PH24" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100754 ---help---
755 See USB1_VBUS_PIN help text.
756
Hans de Goedea60c3fc2016-03-18 08:42:01 +0100757config USB3_VBUS_PIN
758 string "Vbus enable pin for usb3 (ehci2)"
759 default ""
760 ---help---
761 See USB1_VBUS_PIN help text.
762
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200763config I2C0_ENABLE
764 bool "Enable I2C/TWI controller 0"
Chen-Yu Tsai478a3c52016-11-30 15:30:30 +0800765 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200766 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede2c526402016-05-15 13:51:58 +0200767 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200768 ---help---
769 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
770 its clock and setting up the bus. This is especially useful on devices
771 with slaves connected to the bus or with pins exposed through e.g. an
772 expansion port/header.
773
774config I2C1_ENABLE
775 bool "Enable I2C/TWI controller 1"
Hans de Goede2c526402016-05-15 13:51:58 +0200776 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200777 ---help---
778 See I2C0_ENABLE help text.
779
Jernej Skrabec55a30a22021-01-11 21:11:38 +0100780if SUNXI_GEN_SUN6I || SUN50I_GEN_H6
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100781config R_I2C_ENABLE
782 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100783 # This is used for the pmic on H3
784 default y if SY8106A_POWER
Hans de Goede2c526402016-05-15 13:51:58 +0200785 select CMD_I2C
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100786 ---help---
787 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100788endif
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100789
Hans de Goede3ae1d132015-04-25 17:25:14 +0200790config AXP_GPIO
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900791 bool "Enable support for gpio-s on axp PMICs"
Samuel Holland623b8042021-10-08 00:17:19 -0500792 depends on AXP_PMIC_BUS
Hans de Goede3ae1d132015-04-25 17:25:14 +0200793 ---help---
794 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
795
Chris Morgan2ff2a1d2022-01-21 13:37:32 +0000796config AXP_DISABLE_BOOT_ON_POWERON
797 bool "Disable device boot on power plug-in"
798 depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
799 default n
800 ---help---
801 Say Y here to prevent the device from booting up because of a plug-in
802 event. When set, the device will boot into the SPL briefly to
803 determine why it was powered on, and if it was determined because of
804 a plug-in event instead of a button press event it will shut back off.
805
Icenowy Zheng1fa956f2017-10-26 11:14:44 +0800806config VIDEO_SUNXI
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900807 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Chen-Yu Tsaifa337462017-03-02 16:03:06 +0800808 depends on !MACH_SUN8I_A83T
809 depends on !MACH_SUNXI_H3_H5
Chen-Yu Tsaicc2605e2016-11-30 14:57:32 +0800810 depends on !MACH_SUN8I_R40
Icenowy Zheng52e61882017-04-08 15:30:12 +0800811 depends on !MACH_SUN8I_V3S
Chen-Yu Tsaifa337462017-03-02 16:03:06 +0800812 depends on !MACH_SUN9I
813 depends on !MACH_SUN50I
Jernej Skrabecda8ae612021-01-11 21:11:34 +0100814 depends on !SUN50I_GEN_H6
Andre Przywara068962b2022-10-05 17:54:19 +0100815 depends on !SUNXI_GEN_NCAT2
Simon Glass52cb5042022-10-18 07:46:31 -0600816 select VIDEO
Jagan Teki5bc34cb2021-02-22 00:12:34 +0000817 select DISPLAY
Icenowy Zheng60e4b8f2017-10-26 11:14:46 +0800818 imply VIDEO_DT_SIMPLEFB
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200819 default y
820 ---help---
Jagan Teki5bc34cb2021-02-22 00:12:34 +0000821 Say Y here to add support for using a graphical console on the HDMI,
822 LCD or VGA output found on older sunxi devices. This will also provide
823 a simple_framebuffer device for Linux.
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100824
Hans de Goedee9544592014-12-23 23:04:35 +0100825config VIDEO_HDMI
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900826 bool "HDMI output support"
Icenowy Zheng8f2d1c02022-01-29 10:23:07 -0500827 depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV
Hans de Goedee9544592014-12-23 23:04:35 +0100828 default y
829 ---help---
830 Say Y here to add support for outputting video over HDMI.
831
Hans de Goede260f5202014-12-25 13:58:06 +0100832config VIDEO_VGA
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900833 bool "VGA output support"
Icenowy Zheng1fa956f2017-10-26 11:14:44 +0800834 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
Hans de Goede260f5202014-12-25 13:58:06 +0100835 ---help---
836 Say Y here to add support for outputting video over VGA.
837
Hans de Goedeac1633c2014-12-24 12:17:07 +0100838config VIDEO_VGA_VIA_LCD
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900839 bool "VGA via LCD controller support"
Icenowy Zheng1fa956f2017-10-26 11:14:44 +0800840 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedeac1633c2014-12-24 12:17:07 +0100841 ---help---
842 Say Y here to add support for external DACs connected to the parallel
843 LCD interface driving a VGA connector, such as found on the
844 Olimex A13 boards.
845
Hans de Goede18366f72015-01-25 15:33:07 +0100846config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900847 bool "Force sync active high for VGA via LCD controller support"
Hans de Goede18366f72015-01-25 15:33:07 +0100848 depends on VIDEO_VGA_VIA_LCD
Hans de Goede18366f72015-01-25 15:33:07 +0100849 ---help---
850 Say Y here if you've a board which uses opendrain drivers for the vga
851 hsync and vsync signals. Opendrain drivers cannot generate steep enough
852 positive edges for a stable video output, so on boards with opendrain
853 drivers the sync signals must always be active high.
854
Chen-Yu Tsai9ed19522015-01-12 18:02:11 +0800855config VIDEO_VGA_EXTERNAL_DAC_EN
856 string "LCD panel power enable pin"
857 depends on VIDEO_VGA_VIA_LCD
858 default ""
859 ---help---
860 Set the enable pin for the external VGA DAC. This takes a string in the
861 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
862
Hans de Goedec06e00e2015-08-03 19:20:26 +0200863config VIDEO_COMPOSITE
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900864 bool "Composite video output support"
Icenowy Zheng1fa956f2017-10-26 11:14:44 +0800865 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
Hans de Goedec06e00e2015-08-03 19:20:26 +0200866 ---help---
867 Say Y here to add support for outputting composite video.
868
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100869config VIDEO_LCD_MODE
870 string "LCD panel timing details"
Icenowy Zheng1fa956f2017-10-26 11:14:44 +0800871 depends on VIDEO_SUNXI
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100872 default ""
873 ---help---
874 LCD panel timing details string, leave empty if there is no LCD panel.
875 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
876 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede924c8932015-08-16 11:23:42 +0200877 Also see: http://linux-sunxi.org/LCD
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100878
Hans de Goede481b6642015-01-13 13:21:46 +0100879config VIDEO_LCD_DCLK_PHASE
880 int "LCD panel display clock phase"
Simon Glass52cb5042022-10-18 07:46:31 -0600881 depends on VIDEO_SUNXI || VIDEO
Hans de Goede481b6642015-01-13 13:21:46 +0100882 default 1
Michal Suchanek5cbc3f22022-07-03 20:49:24 +0200883 range 0 3
Hans de Goede481b6642015-01-13 13:21:46 +0100884 ---help---
Michal Suchanek5cbc3f22022-07-03 20:49:24 +0200885 Select LCD panel display clock phase shift
Hans de Goede481b6642015-01-13 13:21:46 +0100886
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100887config VIDEO_LCD_POWER
888 string "LCD panel power enable pin"
Icenowy Zheng1fa956f2017-10-26 11:14:44 +0800889 depends on VIDEO_SUNXI
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100890 default ""
891 ---help---
892 Set the power enable pin for the LCD panel. This takes a string in the
893 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
894
Hans de Goedece9e3322015-02-16 17:26:41 +0100895config VIDEO_LCD_RESET
896 string "LCD panel reset pin"
Icenowy Zheng1fa956f2017-10-26 11:14:44 +0800897 depends on VIDEO_SUNXI
Hans de Goedece9e3322015-02-16 17:26:41 +0100898 default ""
899 ---help---
900 Set the reset pin for the LCD panel. This takes a string in the format
901 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
902
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100903config VIDEO_LCD_BL_EN
904 string "LCD panel backlight enable pin"
Icenowy Zheng1fa956f2017-10-26 11:14:44 +0800905 depends on VIDEO_SUNXI
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100906 default ""
907 ---help---
908 Set the backlight enable pin for the LCD panel. This takes a string in the
909 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
910 port H.
911
912config VIDEO_LCD_BL_PWM
913 string "LCD panel backlight pwm pin"
Icenowy Zheng1fa956f2017-10-26 11:14:44 +0800914 depends on VIDEO_SUNXI
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100915 default ""
916 ---help---
917 Set the backlight pwm pin for the LCD panel. This takes a string in the
918 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200919
Hans de Goede2d5d3022015-01-22 21:02:42 +0100920config VIDEO_LCD_BL_PWM_ACTIVE_LOW
921 bool "LCD panel backlight pwm is inverted"
Icenowy Zheng1fa956f2017-10-26 11:14:44 +0800922 depends on VIDEO_SUNXI
Hans de Goede2d5d3022015-01-22 21:02:42 +0100923 default y
924 ---help---
925 Set this if the backlight pwm output is active low.
926
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100927config VIDEO_LCD_PANEL_I2C
928 bool "LCD panel needs to be configured via i2c"
Icenowy Zheng1fa956f2017-10-26 11:14:44 +0800929 depends on VIDEO_SUNXI
Samuel Holland75fe0f42021-10-08 00:17:24 -0500930 select DM_I2C_GPIO
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100931 ---help---
932 Say y here if the LCD panel needs to be configured via i2c. This
933 will add a bitbang i2c controller using gpios to talk to the LCD.
934
Samuel Holland75fe0f42021-10-08 00:17:24 -0500935config VIDEO_LCD_PANEL_I2C_NAME
936 string "LCD panel i2c interface node name"
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100937 depends on VIDEO_LCD_PANEL_I2C
Samuel Holland8d6fe612022-04-27 15:31:24 -0500938 default "i2c"
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100939 ---help---
Samuel Holland75fe0f42021-10-08 00:17:24 -0500940 Set the device tree node name for the LCD i2c interface.
Hans de Goede797a0f52015-01-01 22:04:34 +0100941
942# Note only one of these may be selected at a time! But hidden choices are
943# not supported by Kconfig
944config VIDEO_LCD_IF_PARALLEL
945 bool
946
947config VIDEO_LCD_IF_LVDS
948 bool
949
Jernej Skrabec9b4ca922017-03-27 19:22:31 +0200950config SUNXI_DE2
951 bool
Jernej Skrabec9b4ca922017-03-27 19:22:31 +0200952
Jernej Skrabec8d91b462017-03-27 19:22:32 +0200953config VIDEO_DE2
954 bool "Display Engine 2 video driver"
955 depends on SUNXI_DE2
Simon Glass52cb5042022-10-18 07:46:31 -0600956 select VIDEO
Jernej Skrabec8d91b462017-03-27 19:22:32 +0200957 select DISPLAY
Jernej Skrabecc2a50b12021-03-06 20:54:19 +0100958 select VIDEO_DW_HDMI
Icenowy Zheng82576de2017-10-26 11:14:47 +0800959 imply VIDEO_DT_SIMPLEFB
Jernej Skrabec8d91b462017-03-27 19:22:32 +0200960 default y
961 ---help---
962 Say y here if you want to build DE2 video driver which is present on
963 newer SoCs. Currently only HDMI output is supported.
964
Hans de Goede797a0f52015-01-01 22:04:34 +0100965
966choice
967 prompt "LCD panel support"
Icenowy Zheng1fa956f2017-10-26 11:14:44 +0800968 depends on VIDEO_SUNXI
Hans de Goede797a0f52015-01-01 22:04:34 +0100969 ---help---
970 Select which type of LCD panel to support.
971
972config VIDEO_LCD_PANEL_PARALLEL
973 bool "Generic parallel interface LCD panel"
974 select VIDEO_LCD_IF_PARALLEL
975
976config VIDEO_LCD_PANEL_LVDS
977 bool "Generic lvds interface LCD panel"
978 select VIDEO_LCD_IF_LVDS
979
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200980config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
981 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
982 select VIDEO_LCD_SSD2828
983 select VIDEO_LCD_IF_PARALLEL
984 ---help---
Hans de Goede91f1b822015-08-08 16:13:53 +0200985 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
986
987config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
988 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
989 select VIDEO_LCD_ANX9804
990 select VIDEO_LCD_IF_PARALLEL
991 select VIDEO_LCD_PANEL_I2C
992 ---help---
993 Select this for eDP LCD panels with 4 lanes running at 1.62G,
994 connected via an ANX9804 bridge chip.
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200995
Hans de Goede743fb9552015-01-20 09:23:36 +0100996config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
997 bool "Hitachi tx18d42vm LCD panel"
998 select VIDEO_LCD_HITACHI_TX18D42VM
999 select VIDEO_LCD_IF_LVDS
1000 ---help---
1001 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
1002
Hans de Goede613dade2015-02-16 17:49:47 +01001003config VIDEO_LCD_TL059WV5C0
1004 bool "tl059wv5c0 LCD panel"
1005 select VIDEO_LCD_PANEL_I2C
1006 select VIDEO_LCD_IF_PARALLEL
1007 ---help---
1008 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
1009 Aigo M60/M608/M606 tablets.
1010
Hans de Goede797a0f52015-01-01 22:04:34 +01001011endchoice
1012
Hans de Goedebf880fe2015-01-25 12:10:48 +01001013config GMAC_TX_DELAY
1014 int "GMAC Transmit Clock Delay Chain"
1015 default 0
1016 ---help---
1017 Set the GMAC Transmit Clock Delay Chain value.
1018
Hans de Goede66ab79d2015-09-13 13:02:48 +02001019config SPL_STACK_R_ADDR
Icenowy Zheng8f2d1c02022-01-29 10:23:07 -05001020 default 0x81e00000 if MACH_SUNIV
Chen-Yu Tsaifa337462017-03-02 16:03:06 +08001021 default 0x4fe00000 if MACH_SUN4I
1022 default 0x4fe00000 if MACH_SUN5I
1023 default 0x4fe00000 if MACH_SUN6I
1024 default 0x4fe00000 if MACH_SUN7I
1025 default 0x4fe00000 if MACH_SUN8I
Hans de Goede66ab79d2015-09-13 13:02:48 +02001026 default 0x2fe00000 if MACH_SUN9I
Chen-Yu Tsaifa337462017-03-02 16:03:06 +08001027 default 0x4fe00000 if MACH_SUN50I
Jernej Skrabecda8ae612021-01-11 21:11:34 +01001028 default 0x4fe00000 if SUN50I_GEN_H6
Andre Przywara068962b2022-10-05 17:54:19 +01001029 default 0x4fe00000 if SUNXI_GEN_NCAT2
Hans de Goede66ab79d2015-09-13 13:02:48 +02001030
Jagan Teki4e159f82018-02-06 22:42:56 +05301031config SPL_SPI_SUNXI
1032 bool "Support for SPI Flash on Allwinner SoCs in SPL"
Andre Przywarab2b4ff22020-12-13 20:19:43 +00001033 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV
Jagan Teki4e159f82018-02-06 22:42:56 +05301034 help
1035 Enable support for SPI Flash. This option allows SPL to read from
1036 sunxi SPI Flash. It uses the same method as the boot ROM, so does
1037 not need any extra configuration.
1038
Icenowy Zheng2a269d32018-10-25 17:23:02 +08001039config PINE64_DT_SELECTION
1040 bool "Enable Pine64 device tree selection code"
1041 depends on MACH_SUN50I
1042 help
1043 The original Pine A64 and Pine A64+ are similar but different
1044 boards and can be differed by the DRAM size. Pine A64 has
1045 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
1046 option, the device tree selection code specific to Pine64 which
1047 utilizes the DRAM size will be enabled.
1048
Samuel Holland9c7cefc2020-10-24 10:21:52 -05001049config PINEPHONE_DT_SELECTION
1050 bool "Enable PinePhone device tree selection code"
1051 depends on MACH_SUN50I
1052 help
1053 Enable this option to automatically select the device tree for the
1054 correct PinePhone hardware revision during boot.
1055
Andre Heiderbf8c8102021-10-01 19:29:00 +01001056config BLUETOOTH_DT_DEVICE_FIXUP
1057 string "Fixup the Bluetooth controller address"
1058 default ""
1059 help
1060 This option specifies the DT compatible name of the Bluetooth
1061 controller for which to set the "local-bd-address" property.
1062 Set this option if your device ships with the Bluetooth controller
1063 default address.
1064 The used address is "bdaddr" if set, and "ethaddr" with the LSB
1065 flipped elsewise.
1066
Samuel Holland7591a042022-03-18 00:00:45 -05001067source "board/sunxi/Kconfig"
1068
Masahiro Yamadad3ae6782014-07-30 14:08:14 +09001069endif
Kory Maincentfe4c1552021-05-04 19:31:27 +02001070
1071config CHIP_DIP_SCAN
1072 bool "Enable DIPs detection for CHIP board"
1073 select SUPPORT_EXTENSION_SCAN
1074 select W1
1075 select W1_GPIO
1076 select W1_EEPROM
1077 select W1_EEPROM_DS24XXX
1078 select CMD_EXTENSION