| commit | f09b48e5041906ac734e7901305f10511e1c4111 | [log] [tgz] |
|---|---|---|
| author | Icenowy Zheng <icenowy@aosc.xyz> | Sat Jun 03 17:10:18 2017 +0800 |
| committer | Jagan Teki <jagan@amarulasolutions.com> | Thu Jun 08 22:37:55 2017 +0530 |
| tree | 07a6c460c9a922c90ebf00a0522e3845970d4fbc | |
| parent | 200203548d68d8e7a48d950936fcb42321cdaac6 [diff] |
sunxi: Add selective DRAM type and timing DRAM chip varies, and one code cannot satisfy all DRAMs. Add options to select a timing set. Currently only DDR3-1333 (the original set) is added into it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>