blob: a126c3e30140eca32eab869cddb0d3cc2fe01989 [file] [log] [blame]
Ian Campbelld8e69e02014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Siva Durga Prasad Paladugu809438d2016-07-29 15:31:47 +05303config IDENT_STRING
4 default " Allwinner Technology"
5
Simon Glasse304a5e2016-10-17 20:12:36 -06006config PRE_CONSOLE_BUFFER
7 default y
8
Simon Glass0bdfc3e2016-09-12 23:18:39 -06009config SPL_GPIO_SUPPORT
10 default y
11
Simon Glassf2a89462016-09-12 23:18:41 -060012config SPL_LIBCOMMON_SUPPORT
13 default y
14
Simon Glassf6de2572016-09-12 23:18:42 -060015config SPL_LIBDISK_SUPPORT
16 default y
17
Simon Glassb16c92c2016-09-12 23:18:43 -060018config SPL_LIBGENERIC_SUPPORT
19 default y
20
Simon Glassbd58f1d2016-09-12 23:18:44 -060021config SPL_MMC_SUPPORT
22 default y
23
Simon Glass0d7c7e02016-09-12 23:18:54 -060024config SPL_POWER_SUPPORT
25 default y
26
Simon Glasse076d6f2016-09-12 23:18:56 -060027config SPL_SERIAL_SUPPORT
28 default y
29
Hans de Goedef07872b2015-04-06 20:33:34 +020030# Note only one of these may be selected at a time! But hidden choices are
31# not supported by Kconfig
32config SUNXI_GEN_SUN4I
33 bool
34 ---help---
35 Select this for sunxi SoCs which have resets and clocks set up
36 as the original A10 (mach-sun4i).
37
38config SUNXI_GEN_SUN6I
39 bool
40 ---help---
41 Select this for sunxi SoCs which have sun6i like periphery, like
42 separate ahb reset control registers, custom pmic bus, new style
43 watchdog, etc.
44
45
Ian Campbelld8e69e02014-10-24 21:20:44 +010046choice
47 prompt "Sunxi SoC Variant"
Hans de Goedeb05a6482016-06-12 11:57:07 +020048 optional
Ian Campbelld8e69e02014-10-24 21:20:44 +010049
Ian Campbell4a24a1c2014-10-24 21:20:45 +010050config MACH_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010051 bool "sun4i (Allwinner A10)"
52 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020053 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010054 select SUPPORT_SPL
55
Ian Campbell4a24a1c2014-10-24 21:20:45 +010056config MACH_SUN5I
Ian Campbelld8e69e02014-10-24 21:20:44 +010057 bool "sun5i (Allwinner A13)"
58 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020059 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010060 select SUPPORT_SPL
61
Ian Campbell4a24a1c2014-10-24 21:20:45 +010062config MACH_SUN6I
Ian Campbelld8e69e02014-10-24 21:20:44 +010063 bool "sun6i (Allwinner A31)"
64 select CPU_V7
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080065 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090067 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020068 select SUNXI_GEN_SUN6I
Hans de Goedea5403b92014-10-25 20:18:10 +020069 select SUPPORT_SPL
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080070 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010071
Ian Campbell4a24a1c2014-10-24 21:20:45 +010072config MACH_SUN7I
Ian Campbelld8e69e02014-10-24 21:20:44 +010073 bool "sun7i (Allwinner A20)"
74 select CPU_V7
Hans de Goede85437352014-11-14 09:34:30 +010075 select CPU_V7_HAS_NONSEC
76 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090077 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020078 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010079 select SUPPORT_SPL
Hans de Goedea5636382014-10-24 20:12:04 +020080 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010081
Hans de Goedef055ed62015-04-06 20:55:39 +020082config MACH_SUN8I_A23
Ian Campbelld8e69e02014-10-24 21:20:44 +010083 bool "sun8i (Allwinner A23)"
84 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080085 select CPU_V7_HAS_NONSEC
86 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090087 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020088 select SUNXI_GEN_SUN6I
Hans de Goede966d2392014-12-07 14:34:27 +010089 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080090 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010091
Vishnu Patekar3702f142015-03-01 23:47:48 +053092config MACH_SUN8I_A33
93 bool "sun8i (Allwinner A33)"
94 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080095 select CPU_V7_HAS_NONSEC
96 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090097 select ARCH_SUPPORT_PSCI
Vishnu Patekar3702f142015-03-01 23:47:48 +053098 select SUNXI_GEN_SUN6I
99 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +0800100 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar3702f142015-03-01 23:47:48 +0530101
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800102config MACH_SUN8I_A83T
103 bool "sun8i (Allwinner A83T)"
104 select CPU_V7
105 select SUNXI_GEN_SUN6I
106 select SUPPORT_SPL
107
Jens Kuskef9770722015-11-17 15:12:58 +0100108config MACH_SUN8I_H3
109 bool "sun8i (Allwinner H3)"
110 select CPU_V7
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +0800111 select CPU_V7_HAS_NONSEC
112 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +0900113 select ARCH_SUPPORT_PSCI
Jens Kuskef9770722015-11-17 15:12:58 +0100114 select SUNXI_GEN_SUN6I
Jens Kuske53f018e2015-11-17 15:12:59 +0100115 select SUPPORT_SPL
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +0800116 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuskef9770722015-11-17 15:12:58 +0100117
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100118config MACH_SUN9I
119 bool "sun9i (Allwinner A80)"
120 select CPU_V7
121 select SUNXI_GEN_SUN6I
122
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800123config MACH_SUN50I
124 bool "sun50i (Allwinner A64)"
125 select ARM64
126 select SUNXI_GEN_SUN6I
127
Ian Campbelld8e69e02014-10-24 21:20:44 +0100128endchoice
Maxime Ripard2c519412014-10-03 20:16:29 +0800129
Hans de Goedef055ed62015-04-06 20:55:39 +0200130# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
131config MACH_SUN8I
132 bool
vishnupatekarcdf1e482015-11-29 01:07:19 +0800133 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
Hans de Goedef055ed62015-04-06 20:55:39 +0200134
Vishnu Patekarc49936f2016-01-12 01:20:58 +0800135config DRAM_TYPE
136 int "sunxi dram type"
137 depends on MACH_SUN8I_A83T
138 default 3
139 ---help---
140 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goedef055ed62015-04-06 20:55:39 +0200141
Hans de Goede3aeaa282014-11-15 19:46:39 +0100142config DRAM_CLK
Hans de Goede59d9fc72015-01-17 14:24:55 +0100143 int "sunxi dram clock speed"
Philipp Tomsichd36af1c2016-10-28 18:21:28 +0800144 default 792 if MACH_SUN9I
Hans de Goede59d9fc72015-01-17 14:24:55 +0100145 default 312 if MACH_SUN6I || MACH_SUN8I
146 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100147 ---help---
Philipp Tomsichd36af1c2016-10-28 18:21:28 +0800148 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
149 must be a multiple of 24. For the sun9i (A80), the tested values
150 (for DDR3-1600) are 312 to 792.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100151
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200152if MACH_SUN5I || MACH_SUN7I
153config DRAM_MBUS_CLK
154 int "sunxi mbus clock speed"
155 default 300
156 ---help---
157 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
158
159endif
160
Hans de Goede3aeaa282014-11-15 19:46:39 +0100161config DRAM_ZQ
Hans de Goede59d9fc72015-01-17 14:24:55 +0100162 int "sunxi dram zq value"
163 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
164 default 127 if MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100165 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100166 Set the dram zq value.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100167
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200168config DRAM_ODT_EN
169 bool "sunxi dram odt enable"
170 default n if !MACH_SUN8I_A23
171 default y if MACH_SUN8I_A23
172 ---help---
173 Select this to enable dram odt (on die termination).
174
Hans de Goede59d9fc72015-01-17 14:24:55 +0100175if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
176config DRAM_EMR1
177 int "sunxi dram emr1 value"
178 default 0 if MACH_SUN4I
179 default 4 if MACH_SUN5I || MACH_SUN7I
180 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100181 Set the dram controller emr1 value.
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200182
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200183config DRAM_TPR3
184 hex "sunxi dram tpr3 value"
185 default 0
186 ---help---
187 Set the dram controller tpr3 parameter. This parameter configures
188 the delay on the command lane and also phase shifts, which are
189 applied for sampling incoming read data. The default value 0
190 means that no phase/delay adjustments are necessary. Properly
191 configuring this parameter increases reliability at high DRAM
192 clock speeds.
193
194config DRAM_DQS_GATING_DELAY
195 hex "sunxi dram dqs_gating_delay value"
196 default 0
197 ---help---
198 Set the dram controller dqs_gating_delay parmeter. Each byte
199 encodes the DQS gating delay for each byte lane. The delay
200 granularity is 1/4 cycle. For example, the value 0x05060606
201 means that the delay is 5 quarter-cycles for one lane (1.25
202 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
203 The default value 0 means autodetection. The results of hardware
204 autodetection are not very reliable and depend on the chip
205 temperature (sometimes producing different results on cold start
206 and warm reboot). But the accuracy of hardware autodetection
207 is usually good enough, unless running at really high DRAM
208 clocks speeds (up to 600MHz). If unsure, keep as 0.
209
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200210choice
211 prompt "sunxi dram timings"
212 default DRAM_TIMINGS_VENDOR_MAGIC
213 ---help---
214 Select the timings of the DDR3 chips.
215
216config DRAM_TIMINGS_VENDOR_MAGIC
217 bool "Magic vendor timings from Android"
218 ---help---
219 The same DRAM timings as in the Allwinner boot0 bootloader.
220
221config DRAM_TIMINGS_DDR3_1066F_1333H
222 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
223 ---help---
224 Use the timings of the standard JEDEC DDR3-1066F speed bin for
225 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
226 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
227 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
228 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
229 that down binning to DDR3-1066F is supported (because DDR3-1066F
230 uses a bit faster timings than DDR3-1333H).
231
232config DRAM_TIMINGS_DDR3_800E_1066G_1333J
233 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
234 ---help---
235 Use the timings of the slowest possible JEDEC speed bin for the
236 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
237 DDR3-800E, DDR3-1066G or DDR3-1333J.
238
239endchoice
240
Hans de Goede3aeaa282014-11-15 19:46:39 +0100241endif
242
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200243if MACH_SUN8I_A23
244config DRAM_ODT_CORRECTION
245 int "sunxi dram odt correction value"
246 default 0
247 ---help---
248 Set the dram odt correction value (range -255 - 255). In allwinner
249 fex files, this option is found in bits 8-15 of the u32 odt_en variable
250 in the [dram] section. When bit 31 of the odt_en variable is set
251 then the correction is negative. Usually the value for this is 0.
252endif
253
Iain Paton630df142015-03-28 10:26:38 +0000254config SYS_CLK_FREQ
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200255 default 816000000 if MACH_SUN50I
Iain Paton630df142015-03-28 10:26:38 +0000256 default 912000000 if MACH_SUN7I
257 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
258
Maxime Ripard2c519412014-10-03 20:16:29 +0800259config SYS_CONFIG_NAME
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100260 default "sun4i" if MACH_SUN4I
261 default "sun5i" if MACH_SUN5I
262 default "sun6i" if MACH_SUN6I
263 default "sun7i" if MACH_SUN7I
264 default "sun8i" if MACH_SUN8I
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100265 default "sun9i" if MACH_SUN9I
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200266 default "sun50i" if MACH_SUN50I
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900267
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900268config SYS_BOARD
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900269 default "sunxi"
270
271config SYS_SOC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900272 default "sunxi"
273
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200274config UART0_PORT_F
275 bool "UART0 on MicroSD breakout board"
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200276 default n
277 ---help---
278 Repurpose the SD card slot for getting access to the UART0 serial
279 console. Primarily useful only for low level u-boot debugging on
280 tablets, where normal UART0 is difficult to access and requires
281 device disassembly and/or soldering. As the SD card can't be used
282 at the same time, the system can be only booted in the FEL mode.
283 Only enable this if you really know what you are doing.
284
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200285config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900286 bool "Enable workarounds for booting old kernels"
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200287 default n
288 ---help---
289 Set this to enable various workarounds for old kernels, this results in
290 sub-optimal settings for newer kernels, only enable if needed.
291
Maxime Riparde0c7aa42015-10-15 22:04:07 +0200292config MMC
293 depends on !UART0_PORT_F
294 default y if ARCH_SUNXI
295
Hans de Goede7412ef82014-10-02 20:29:26 +0200296config MMC0_CD_PIN
297 string "Card detect pin for mmc0"
Chen-Yu Tsai36741482016-05-02 10:28:08 +0800298 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
Hans de Goede7412ef82014-10-02 20:29:26 +0200299 default ""
300 ---help---
301 Set the card detect pin for mmc0, leave empty to not use cd. This
302 takes a string in the format understood by sunxi_name_to_gpio, e.g.
303 PH1 for pin 1 of port H.
304
305config MMC1_CD_PIN
306 string "Card detect pin for mmc1"
307 default ""
308 ---help---
309 See MMC0_CD_PIN help text.
310
311config MMC2_CD_PIN
312 string "Card detect pin for mmc2"
313 default ""
314 ---help---
315 See MMC0_CD_PIN help text.
316
317config MMC3_CD_PIN
318 string "Card detect pin for mmc3"
319 default ""
320 ---help---
321 See MMC0_CD_PIN help text.
322
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100323config MMC1_PINS
324 string "Pins for mmc1"
325 default ""
326 ---help---
327 Set the pins used for mmc1, when applicable. This takes a string in the
328 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
329
330config MMC2_PINS
331 string "Pins for mmc2"
332 default ""
333 ---help---
334 See MMC1_PINS help text.
335
336config MMC3_PINS
337 string "Pins for mmc3"
338 default ""
339 ---help---
340 See MMC1_PINS help text.
341
Hans de Goedeaf593e42014-10-02 20:43:50 +0200342config MMC_SUNXI_SLOT_EXTRA
343 int "mmc extra slot number"
344 default -1
345 ---help---
346 sunxi builds always enable mmc0, some boards also have a second sdcard
347 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
348 support for this.
349
Hans de Goede99c9fb02016-04-01 22:39:26 +0200350config INITIAL_USB_SCAN_DELAY
351 int "delay initial usb scan by x ms to allow builtin devices to init"
352 default 0
353 ---help---
354 Some boards have on board usb devices which need longer than the
355 USB spec's 1 second to connect from board powerup. Set this config
356 option to a non 0 value to add an extra delay before the first usb
357 bus scan.
358
Hans de Goedee7b852a2015-01-07 15:26:06 +0100359config USB0_VBUS_PIN
360 string "Vbus enable pin for usb0 (otg)"
361 default ""
362 ---help---
363 Set the Vbus enable pin for usb0 (otg). This takes a string in the
364 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
365
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100366config USB0_VBUS_DET
367 string "Vbus detect pin for usb0 (otg)"
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100368 default ""
369 ---help---
370 Set the Vbus detect pin for usb0 (otg). This takes a string in the
371 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
372
Hans de Goedeaadd97f2015-06-14 17:29:53 +0200373config USB0_ID_DET
374 string "ID detect pin for usb0 (otg)"
375 default ""
376 ---help---
377 Set the ID detect pin for usb0 (otg). This takes a string in the
378 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
379
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100380config USB1_VBUS_PIN
381 string "Vbus enable pin for usb1 (ehci0)"
382 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100383 default "PH27" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100384 ---help---
385 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
386 a string in the format understood by sunxi_name_to_gpio, e.g.
387 PH1 for pin 1 of port H.
388
389config USB2_VBUS_PIN
390 string "Vbus enable pin for usb2 (ehci1)"
391 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100392 default "PH24" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100393 ---help---
394 See USB1_VBUS_PIN help text.
395
Hans de Goedea60c3fc2016-03-18 08:42:01 +0100396config USB3_VBUS_PIN
397 string "Vbus enable pin for usb3 (ehci2)"
398 default ""
399 ---help---
400 See USB1_VBUS_PIN help text.
401
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200402config I2C0_ENABLE
403 bool "Enable I2C/TWI controller 0"
404 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
405 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede2c526402016-05-15 13:51:58 +0200406 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200407 ---help---
408 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
409 its clock and setting up the bus. This is especially useful on devices
410 with slaves connected to the bus or with pins exposed through e.g. an
411 expansion port/header.
412
413config I2C1_ENABLE
414 bool "Enable I2C/TWI controller 1"
415 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200416 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200417 ---help---
418 See I2C0_ENABLE help text.
419
420config I2C2_ENABLE
421 bool "Enable I2C/TWI controller 2"
422 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200423 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200424 ---help---
425 See I2C0_ENABLE help text.
426
427if MACH_SUN6I || MACH_SUN7I
428config I2C3_ENABLE
429 bool "Enable I2C/TWI controller 3"
430 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200431 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200432 ---help---
433 See I2C0_ENABLE help text.
434endif
435
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100436if SUNXI_GEN_SUN6I
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100437config R_I2C_ENABLE
438 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100439 # This is used for the pmic on H3
440 default y if SY8106A_POWER
Hans de Goede2c526402016-05-15 13:51:58 +0200441 select CMD_I2C
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100442 ---help---
443 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100444endif
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100445
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200446if MACH_SUN7I
447config I2C4_ENABLE
448 bool "Enable I2C/TWI controller 4"
449 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200450 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200451 ---help---
452 See I2C0_ENABLE help text.
453endif
454
Hans de Goede3ae1d132015-04-25 17:25:14 +0200455config AXP_GPIO
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900456 bool "Enable support for gpio-s on axp PMICs"
Hans de Goede3ae1d132015-04-25 17:25:14 +0200457 default n
458 ---help---
459 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
460
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200461config VIDEO
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900462 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Andre Przywara8f977272016-09-05 01:32:40 +0100463 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200464 default y
465 ---help---
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100466 Say Y here to add support for using a cfb console on the HDMI, LCD
467 or VGA output found on most sunxi devices. See doc/README.video for
468 info on how to select the video output and mode.
469
Hans de Goedee9544592014-12-23 23:04:35 +0100470config VIDEO_HDMI
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900471 bool "HDMI output support"
Hans de Goedee9544592014-12-23 23:04:35 +0100472 depends on VIDEO && !MACH_SUN8I
473 default y
474 ---help---
475 Say Y here to add support for outputting video over HDMI.
476
Hans de Goede260f5202014-12-25 13:58:06 +0100477config VIDEO_VGA
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900478 bool "VGA output support"
Hans de Goede260f5202014-12-25 13:58:06 +0100479 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
480 default n
481 ---help---
482 Say Y here to add support for outputting video over VGA.
483
Hans de Goedeac1633c2014-12-24 12:17:07 +0100484config VIDEO_VGA_VIA_LCD
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900485 bool "VGA via LCD controller support"
Chen-Yu Tsai39ca4c12015-01-12 18:02:10 +0800486 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedeac1633c2014-12-24 12:17:07 +0100487 default n
488 ---help---
489 Say Y here to add support for external DACs connected to the parallel
490 LCD interface driving a VGA connector, such as found on the
491 Olimex A13 boards.
492
Hans de Goede18366f72015-01-25 15:33:07 +0100493config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900494 bool "Force sync active high for VGA via LCD controller support"
Hans de Goede18366f72015-01-25 15:33:07 +0100495 depends on VIDEO_VGA_VIA_LCD
496 default n
497 ---help---
498 Say Y here if you've a board which uses opendrain drivers for the vga
499 hsync and vsync signals. Opendrain drivers cannot generate steep enough
500 positive edges for a stable video output, so on boards with opendrain
501 drivers the sync signals must always be active high.
502
Chen-Yu Tsai9ed19522015-01-12 18:02:11 +0800503config VIDEO_VGA_EXTERNAL_DAC_EN
504 string "LCD panel power enable pin"
505 depends on VIDEO_VGA_VIA_LCD
506 default ""
507 ---help---
508 Set the enable pin for the external VGA DAC. This takes a string in the
509 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
510
Hans de Goedec06e00e2015-08-03 19:20:26 +0200511config VIDEO_COMPOSITE
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900512 bool "Composite video output support"
Hans de Goedec06e00e2015-08-03 19:20:26 +0200513 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
514 default n
515 ---help---
516 Say Y here to add support for outputting composite video.
517
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100518config VIDEO_LCD_MODE
519 string "LCD panel timing details"
520 depends on VIDEO
521 default ""
522 ---help---
523 LCD panel timing details string, leave empty if there is no LCD panel.
524 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
525 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede924c8932015-08-16 11:23:42 +0200526 Also see: http://linux-sunxi.org/LCD
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100527
Hans de Goede481b6642015-01-13 13:21:46 +0100528config VIDEO_LCD_DCLK_PHASE
529 int "LCD panel display clock phase"
530 depends on VIDEO
531 default 1
532 ---help---
533 Select LCD panel display clock phase shift, range 0-3.
534
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100535config VIDEO_LCD_POWER
536 string "LCD panel power enable pin"
537 depends on VIDEO
538 default ""
539 ---help---
540 Set the power enable pin for the LCD panel. This takes a string in the
541 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
542
Hans de Goedece9e3322015-02-16 17:26:41 +0100543config VIDEO_LCD_RESET
544 string "LCD panel reset pin"
545 depends on VIDEO
546 default ""
547 ---help---
548 Set the reset pin for the LCD panel. This takes a string in the format
549 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
550
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100551config VIDEO_LCD_BL_EN
552 string "LCD panel backlight enable pin"
553 depends on VIDEO
554 default ""
555 ---help---
556 Set the backlight enable pin for the LCD panel. This takes a string in the
557 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
558 port H.
559
560config VIDEO_LCD_BL_PWM
561 string "LCD panel backlight pwm pin"
562 depends on VIDEO
563 default ""
564 ---help---
565 Set the backlight pwm pin for the LCD panel. This takes a string in the
566 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200567
Hans de Goede2d5d3022015-01-22 21:02:42 +0100568config VIDEO_LCD_BL_PWM_ACTIVE_LOW
569 bool "LCD panel backlight pwm is inverted"
570 depends on VIDEO
571 default y
572 ---help---
573 Set this if the backlight pwm output is active low.
574
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100575config VIDEO_LCD_PANEL_I2C
576 bool "LCD panel needs to be configured via i2c"
577 depends on VIDEO
Hans de Goede6de9f762015-03-07 12:00:02 +0100578 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200579 select CMD_I2C
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100580 ---help---
581 Say y here if the LCD panel needs to be configured via i2c. This
582 will add a bitbang i2c controller using gpios to talk to the LCD.
583
584config VIDEO_LCD_PANEL_I2C_SDA
585 string "LCD panel i2c interface SDA pin"
586 depends on VIDEO_LCD_PANEL_I2C
587 default "PG12"
588 ---help---
589 Set the SDA pin for the LCD i2c interface. This takes a string in the
590 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
591
592config VIDEO_LCD_PANEL_I2C_SCL
593 string "LCD panel i2c interface SCL pin"
594 depends on VIDEO_LCD_PANEL_I2C
595 default "PG10"
596 ---help---
597 Set the SCL pin for the LCD i2c interface. This takes a string in the
598 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
599
Hans de Goede797a0f52015-01-01 22:04:34 +0100600
601# Note only one of these may be selected at a time! But hidden choices are
602# not supported by Kconfig
603config VIDEO_LCD_IF_PARALLEL
604 bool
605
606config VIDEO_LCD_IF_LVDS
607 bool
608
609
610choice
611 prompt "LCD panel support"
612 depends on VIDEO
613 ---help---
614 Select which type of LCD panel to support.
615
616config VIDEO_LCD_PANEL_PARALLEL
617 bool "Generic parallel interface LCD panel"
618 select VIDEO_LCD_IF_PARALLEL
619
620config VIDEO_LCD_PANEL_LVDS
621 bool "Generic lvds interface LCD panel"
622 select VIDEO_LCD_IF_LVDS
623
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200624config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
625 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
626 select VIDEO_LCD_SSD2828
627 select VIDEO_LCD_IF_PARALLEL
628 ---help---
Hans de Goede91f1b822015-08-08 16:13:53 +0200629 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
630
631config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
632 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
633 select VIDEO_LCD_ANX9804
634 select VIDEO_LCD_IF_PARALLEL
635 select VIDEO_LCD_PANEL_I2C
636 ---help---
637 Select this for eDP LCD panels with 4 lanes running at 1.62G,
638 connected via an ANX9804 bridge chip.
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200639
Hans de Goede743fb9552015-01-20 09:23:36 +0100640config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
641 bool "Hitachi tx18d42vm LCD panel"
642 select VIDEO_LCD_HITACHI_TX18D42VM
643 select VIDEO_LCD_IF_LVDS
644 ---help---
645 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
646
Hans de Goede613dade2015-02-16 17:49:47 +0100647config VIDEO_LCD_TL059WV5C0
648 bool "tl059wv5c0 LCD panel"
649 select VIDEO_LCD_PANEL_I2C
650 select VIDEO_LCD_IF_PARALLEL
651 ---help---
652 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
653 Aigo M60/M608/M606 tablets.
654
Hans de Goede797a0f52015-01-01 22:04:34 +0100655endchoice
656
657
Hans de Goedebf880fe2015-01-25 12:10:48 +0100658config GMAC_TX_DELAY
659 int "GMAC Transmit Clock Delay Chain"
660 default 0
661 ---help---
662 Set the GMAC Transmit Clock Delay Chain value.
663
Hans de Goede66ab79d2015-09-13 13:02:48 +0200664config SPL_STACK_R_ADDR
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200665 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
Hans de Goede66ab79d2015-09-13 13:02:48 +0200666 default 0x2fe00000 if MACH_SUN9I
667
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900668endif