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Ian Campbelld8e69e02014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Hans de Goedef07872b2015-04-06 20:33:34 +02003# Note only one of these may be selected at a time! But hidden choices are
4# not supported by Kconfig
5config SUNXI_GEN_SUN4I
6 bool
7 ---help---
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
10
11config SUNXI_GEN_SUN6I
12 bool
13 ---help---
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
16 watchdog, etc.
17
18
Ian Campbelld8e69e02014-10-24 21:20:44 +010019choice
20 prompt "Sunxi SoC Variant"
Joe Hershbergerf0699602015-05-12 14:46:23 -050021 optional
Ian Campbelld8e69e02014-10-24 21:20:44 +010022
Ian Campbell4a24a1c2014-10-24 21:20:45 +010023config MACH_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010024 bool "sun4i (Allwinner A10)"
25 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020026 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010027 select SUPPORT_SPL
28
Ian Campbell4a24a1c2014-10-24 21:20:45 +010029config MACH_SUN5I
Ian Campbelld8e69e02014-10-24 21:20:44 +010030 bool "sun5i (Allwinner A13)"
31 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020032 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010033 select SUPPORT_SPL
34
Ian Campbell4a24a1c2014-10-24 21:20:45 +010035config MACH_SUN6I
Ian Campbelld8e69e02014-10-24 21:20:44 +010036 bool "sun6i (Allwinner A31)"
37 select CPU_V7
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080038 select CPU_V7_HAS_NONSEC
39 select CPU_V7_HAS_VIRT
Hans de Goedef07872b2015-04-06 20:33:34 +020040 select SUNXI_GEN_SUN6I
Hans de Goedea5403b92014-10-25 20:18:10 +020041 select SUPPORT_SPL
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080042 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010043
Ian Campbell4a24a1c2014-10-24 21:20:45 +010044config MACH_SUN7I
Ian Campbelld8e69e02014-10-24 21:20:44 +010045 bool "sun7i (Allwinner A20)"
46 select CPU_V7
Hans de Goede85437352014-11-14 09:34:30 +010047 select CPU_V7_HAS_NONSEC
48 select CPU_V7_HAS_VIRT
Hans de Goedef07872b2015-04-06 20:33:34 +020049 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010050 select SUPPORT_SPL
Hans de Goedea5636382014-10-24 20:12:04 +020051 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010052
Hans de Goedef055ed62015-04-06 20:55:39 +020053config MACH_SUN8I_A23
Ian Campbelld8e69e02014-10-24 21:20:44 +010054 bool "sun8i (Allwinner A23)"
55 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020056 select SUNXI_GEN_SUN6I
Hans de Goede966d2392014-12-07 14:34:27 +010057 select SUPPORT_SPL
Ian Campbelld8e69e02014-10-24 21:20:44 +010058
Vishnu Patekar3702f142015-03-01 23:47:48 +053059config MACH_SUN8I_A33
60 bool "sun8i (Allwinner A33)"
61 select CPU_V7
62 select SUNXI_GEN_SUN6I
63 select SUPPORT_SPL
64
Hans de Goede7bfe2bb2015-01-13 19:25:06 +010065config MACH_SUN9I
66 bool "sun9i (Allwinner A80)"
67 select CPU_V7
68 select SUNXI_GEN_SUN6I
69
Ian Campbelld8e69e02014-10-24 21:20:44 +010070endchoice
Maxime Ripard2c519412014-10-03 20:16:29 +080071
Hans de Goedef055ed62015-04-06 20:55:39 +020072# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
73config MACH_SUN8I
74 bool
75 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33
76
77
Hans de Goede3aeaa282014-11-15 19:46:39 +010078config DRAM_CLK
Hans de Goede59d9fc72015-01-17 14:24:55 +010079 int "sunxi dram clock speed"
80 default 312 if MACH_SUN6I || MACH_SUN8I
81 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +010082 ---help---
83 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goede06ddc452015-01-25 11:29:27 +010084 of 24.
Hans de Goede3aeaa282014-11-15 19:46:39 +010085
Siarhei Siamashka47359bb2015-02-01 00:27:06 +020086if MACH_SUN5I || MACH_SUN7I
87config DRAM_MBUS_CLK
88 int "sunxi mbus clock speed"
89 default 300
90 ---help---
91 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
92
93endif
94
Hans de Goede3aeaa282014-11-15 19:46:39 +010095config DRAM_ZQ
Hans de Goede59d9fc72015-01-17 14:24:55 +010096 int "sunxi dram zq value"
97 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
98 default 127 if MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +010099 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100100 Set the dram zq value.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100101
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200102config DRAM_ODT_EN
103 bool "sunxi dram odt enable"
104 default n if !MACH_SUN8I_A23
105 default y if MACH_SUN8I_A23
106 ---help---
107 Select this to enable dram odt (on die termination).
108
Hans de Goede59d9fc72015-01-17 14:24:55 +0100109if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
110config DRAM_EMR1
111 int "sunxi dram emr1 value"
112 default 0 if MACH_SUN4I
113 default 4 if MACH_SUN5I || MACH_SUN7I
114 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100115 Set the dram controller emr1 value.
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200116
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200117config DRAM_TPR3
118 hex "sunxi dram tpr3 value"
119 default 0
120 ---help---
121 Set the dram controller tpr3 parameter. This parameter configures
122 the delay on the command lane and also phase shifts, which are
123 applied for sampling incoming read data. The default value 0
124 means that no phase/delay adjustments are necessary. Properly
125 configuring this parameter increases reliability at high DRAM
126 clock speeds.
127
128config DRAM_DQS_GATING_DELAY
129 hex "sunxi dram dqs_gating_delay value"
130 default 0
131 ---help---
132 Set the dram controller dqs_gating_delay parmeter. Each byte
133 encodes the DQS gating delay for each byte lane. The delay
134 granularity is 1/4 cycle. For example, the value 0x05060606
135 means that the delay is 5 quarter-cycles for one lane (1.25
136 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
137 The default value 0 means autodetection. The results of hardware
138 autodetection are not very reliable and depend on the chip
139 temperature (sometimes producing different results on cold start
140 and warm reboot). But the accuracy of hardware autodetection
141 is usually good enough, unless running at really high DRAM
142 clocks speeds (up to 600MHz). If unsure, keep as 0.
143
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200144choice
145 prompt "sunxi dram timings"
146 default DRAM_TIMINGS_VENDOR_MAGIC
147 ---help---
148 Select the timings of the DDR3 chips.
149
150config DRAM_TIMINGS_VENDOR_MAGIC
151 bool "Magic vendor timings from Android"
152 ---help---
153 The same DRAM timings as in the Allwinner boot0 bootloader.
154
155config DRAM_TIMINGS_DDR3_1066F_1333H
156 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
157 ---help---
158 Use the timings of the standard JEDEC DDR3-1066F speed bin for
159 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
160 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
161 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
162 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
163 that down binning to DDR3-1066F is supported (because DDR3-1066F
164 uses a bit faster timings than DDR3-1333H).
165
166config DRAM_TIMINGS_DDR3_800E_1066G_1333J
167 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
168 ---help---
169 Use the timings of the slowest possible JEDEC speed bin for the
170 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
171 DDR3-800E, DDR3-1066G or DDR3-1333J.
172
173endchoice
174
Hans de Goede3aeaa282014-11-15 19:46:39 +0100175endif
176
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200177if MACH_SUN8I_A23
178config DRAM_ODT_CORRECTION
179 int "sunxi dram odt correction value"
180 default 0
181 ---help---
182 Set the dram odt correction value (range -255 - 255). In allwinner
183 fex files, this option is found in bits 8-15 of the u32 odt_en variable
184 in the [dram] section. When bit 31 of the odt_en variable is set
185 then the correction is negative. Usually the value for this is 0.
186endif
187
Iain Paton630df142015-03-28 10:26:38 +0000188config SYS_CLK_FREQ
189 default 912000000 if MACH_SUN7I
190 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
191
Maxime Ripard2c519412014-10-03 20:16:29 +0800192config SYS_CONFIG_NAME
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100193 default "sun4i" if MACH_SUN4I
194 default "sun5i" if MACH_SUN5I
195 default "sun6i" if MACH_SUN6I
196 default "sun7i" if MACH_SUN7I
197 default "sun8i" if MACH_SUN8I
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100198 default "sun9i" if MACH_SUN9I
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900199
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900200config SYS_BOARD
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900201 default "sunxi"
202
203config SYS_SOC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900204 default "sunxi"
205
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200206config UART0_PORT_F
207 bool "UART0 on MicroSD breakout board"
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200208 default n
209 ---help---
210 Repurpose the SD card slot for getting access to the UART0 serial
211 console. Primarily useful only for low level u-boot debugging on
212 tablets, where normal UART0 is difficult to access and requires
213 device disassembly and/or soldering. As the SD card can't be used
214 at the same time, the system can be only booted in the FEL mode.
215 Only enable this if you really know what you are doing.
216
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200217config OLD_SUNXI_KERNEL_COMPAT
218 boolean "Enable workarounds for booting old kernels"
219 default n
220 ---help---
221 Set this to enable various workarounds for old kernels, this results in
222 sub-optimal settings for newer kernels, only enable if needed.
223
Hans de Goede7412ef82014-10-02 20:29:26 +0200224config MMC0_CD_PIN
225 string "Card detect pin for mmc0"
226 default ""
227 ---help---
228 Set the card detect pin for mmc0, leave empty to not use cd. This
229 takes a string in the format understood by sunxi_name_to_gpio, e.g.
230 PH1 for pin 1 of port H.
231
232config MMC1_CD_PIN
233 string "Card detect pin for mmc1"
234 default ""
235 ---help---
236 See MMC0_CD_PIN help text.
237
238config MMC2_CD_PIN
239 string "Card detect pin for mmc2"
240 default ""
241 ---help---
242 See MMC0_CD_PIN help text.
243
244config MMC3_CD_PIN
245 string "Card detect pin for mmc3"
246 default ""
247 ---help---
248 See MMC0_CD_PIN help text.
249
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100250config MMC1_PINS
251 string "Pins for mmc1"
252 default ""
253 ---help---
254 Set the pins used for mmc1, when applicable. This takes a string in the
255 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
256
257config MMC2_PINS
258 string "Pins for mmc2"
259 default ""
260 ---help---
261 See MMC1_PINS help text.
262
263config MMC3_PINS
264 string "Pins for mmc3"
265 default ""
266 ---help---
267 See MMC1_PINS help text.
268
Hans de Goedeaf593e42014-10-02 20:43:50 +0200269config MMC_SUNXI_SLOT_EXTRA
270 int "mmc extra slot number"
271 default -1
272 ---help---
273 sunxi builds always enable mmc0, some boards also have a second sdcard
274 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
275 support for this.
276
Daniel Kochmańskidbbfdc12015-05-26 17:00:42 +0200277config SPL_NAND_SUPPORT
278 bool "SPL/NAND mode support"
279 depends on SPL
280 default n
281 ---help---
282 This enables support for booting from NAND internal
283 memory. U-Boot SPL doesn't detect where is it load from,
284 therefore this option is needed to properly load image from
285 flash. Option also disables MMC functionality on U-Boot due to
286 initialization errors encountered, when both controllers are
287 enabled.
288
Hans de Goedee7b852a2015-01-07 15:26:06 +0100289config USB0_VBUS_PIN
290 string "Vbus enable pin for usb0 (otg)"
291 default ""
292 ---help---
293 Set the Vbus enable pin for usb0 (otg). This takes a string in the
294 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
295
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100296config USB0_VBUS_DET
297 string "Vbus detect pin for usb0 (otg)"
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100298 default ""
299 ---help---
300 Set the Vbus detect pin for usb0 (otg). This takes a string in the
301 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
302
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100303config USB1_VBUS_PIN
304 string "Vbus enable pin for usb1 (ehci0)"
305 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100306 default "PH27" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100307 ---help---
308 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
309 a string in the format understood by sunxi_name_to_gpio, e.g.
310 PH1 for pin 1 of port H.
311
312config USB2_VBUS_PIN
313 string "Vbus enable pin for usb2 (ehci1)"
314 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100315 default "PH24" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100316 ---help---
317 See USB1_VBUS_PIN help text.
318
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200319config I2C0_ENABLE
320 bool "Enable I2C/TWI controller 0"
321 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
322 default n if MACH_SUN6I || MACH_SUN8I
323 ---help---
324 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
325 its clock and setting up the bus. This is especially useful on devices
326 with slaves connected to the bus or with pins exposed through e.g. an
327 expansion port/header.
328
329config I2C1_ENABLE
330 bool "Enable I2C/TWI controller 1"
331 default n
332 ---help---
333 See I2C0_ENABLE help text.
334
335config I2C2_ENABLE
336 bool "Enable I2C/TWI controller 2"
337 default n
338 ---help---
339 See I2C0_ENABLE help text.
340
341if MACH_SUN6I || MACH_SUN7I
342config I2C3_ENABLE
343 bool "Enable I2C/TWI controller 3"
344 default n
345 ---help---
346 See I2C0_ENABLE help text.
347endif
348
349if MACH_SUN7I
350config I2C4_ENABLE
351 bool "Enable I2C/TWI controller 4"
352 default n
353 ---help---
354 See I2C0_ENABLE help text.
355endif
356
Hans de Goede3ae1d132015-04-25 17:25:14 +0200357config AXP_GPIO
358 boolean "Enable support for gpio-s on axp PMICs"
359 default n
360 ---help---
361 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
362
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200363config VIDEO
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100364 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200365 default y
366 ---help---
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100367 Say Y here to add support for using a cfb console on the HDMI, LCD
368 or VGA output found on most sunxi devices. See doc/README.video for
369 info on how to select the video output and mode.
370
Hans de Goedee9544592014-12-23 23:04:35 +0100371config VIDEO_HDMI
372 boolean "HDMI output support"
373 depends on VIDEO && !MACH_SUN8I
374 default y
375 ---help---
376 Say Y here to add support for outputting video over HDMI.
377
Hans de Goede260f5202014-12-25 13:58:06 +0100378config VIDEO_VGA
379 boolean "VGA output support"
380 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
381 default n
382 ---help---
383 Say Y here to add support for outputting video over VGA.
384
Hans de Goedeac1633c2014-12-24 12:17:07 +0100385config VIDEO_VGA_VIA_LCD
386 boolean "VGA via LCD controller support"
Chen-Yu Tsai39ca4c12015-01-12 18:02:10 +0800387 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedeac1633c2014-12-24 12:17:07 +0100388 default n
389 ---help---
390 Say Y here to add support for external DACs connected to the parallel
391 LCD interface driving a VGA connector, such as found on the
392 Olimex A13 boards.
393
Hans de Goede18366f72015-01-25 15:33:07 +0100394config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
395 boolean "Force sync active high for VGA via LCD controller support"
396 depends on VIDEO_VGA_VIA_LCD
397 default n
398 ---help---
399 Say Y here if you've a board which uses opendrain drivers for the vga
400 hsync and vsync signals. Opendrain drivers cannot generate steep enough
401 positive edges for a stable video output, so on boards with opendrain
402 drivers the sync signals must always be active high.
403
Chen-Yu Tsai9ed19522015-01-12 18:02:11 +0800404config VIDEO_VGA_EXTERNAL_DAC_EN
405 string "LCD panel power enable pin"
406 depends on VIDEO_VGA_VIA_LCD
407 default ""
408 ---help---
409 Set the enable pin for the external VGA DAC. This takes a string in the
410 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
411
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100412config VIDEO_LCD_MODE
413 string "LCD panel timing details"
414 depends on VIDEO
415 default ""
416 ---help---
417 LCD panel timing details string, leave empty if there is no LCD panel.
418 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
419 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
420
Hans de Goede481b6642015-01-13 13:21:46 +0100421config VIDEO_LCD_DCLK_PHASE
422 int "LCD panel display clock phase"
423 depends on VIDEO
424 default 1
425 ---help---
426 Select LCD panel display clock phase shift, range 0-3.
427
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100428config VIDEO_LCD_POWER
429 string "LCD panel power enable pin"
430 depends on VIDEO
431 default ""
432 ---help---
433 Set the power enable pin for the LCD panel. This takes a string in the
434 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
435
Hans de Goedece9e3322015-02-16 17:26:41 +0100436config VIDEO_LCD_RESET
437 string "LCD panel reset pin"
438 depends on VIDEO
439 default ""
440 ---help---
441 Set the reset pin for the LCD panel. This takes a string in the format
442 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
443
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100444config VIDEO_LCD_BL_EN
445 string "LCD panel backlight enable pin"
446 depends on VIDEO
447 default ""
448 ---help---
449 Set the backlight enable pin for the LCD panel. This takes a string in the
450 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
451 port H.
452
453config VIDEO_LCD_BL_PWM
454 string "LCD panel backlight pwm pin"
455 depends on VIDEO
456 default ""
457 ---help---
458 Set the backlight pwm pin for the LCD panel. This takes a string in the
459 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200460
Hans de Goede2d5d3022015-01-22 21:02:42 +0100461config VIDEO_LCD_BL_PWM_ACTIVE_LOW
462 bool "LCD panel backlight pwm is inverted"
463 depends on VIDEO
464 default y
465 ---help---
466 Set this if the backlight pwm output is active low.
467
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100468config VIDEO_LCD_PANEL_I2C
469 bool "LCD panel needs to be configured via i2c"
470 depends on VIDEO
Hans de Goede6de9f762015-03-07 12:00:02 +0100471 default n
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100472 ---help---
473 Say y here if the LCD panel needs to be configured via i2c. This
474 will add a bitbang i2c controller using gpios to talk to the LCD.
475
476config VIDEO_LCD_PANEL_I2C_SDA
477 string "LCD panel i2c interface SDA pin"
478 depends on VIDEO_LCD_PANEL_I2C
479 default "PG12"
480 ---help---
481 Set the SDA pin for the LCD i2c interface. This takes a string in the
482 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
483
484config VIDEO_LCD_PANEL_I2C_SCL
485 string "LCD panel i2c interface SCL pin"
486 depends on VIDEO_LCD_PANEL_I2C
487 default "PG10"
488 ---help---
489 Set the SCL pin for the LCD i2c interface. This takes a string in the
490 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
491
Hans de Goede797a0f52015-01-01 22:04:34 +0100492
493# Note only one of these may be selected at a time! But hidden choices are
494# not supported by Kconfig
495config VIDEO_LCD_IF_PARALLEL
496 bool
497
498config VIDEO_LCD_IF_LVDS
499 bool
500
501
502choice
503 prompt "LCD panel support"
504 depends on VIDEO
505 ---help---
506 Select which type of LCD panel to support.
507
508config VIDEO_LCD_PANEL_PARALLEL
509 bool "Generic parallel interface LCD panel"
510 select VIDEO_LCD_IF_PARALLEL
511
512config VIDEO_LCD_PANEL_LVDS
513 bool "Generic lvds interface LCD panel"
514 select VIDEO_LCD_IF_LVDS
515
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200516config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
517 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
518 select VIDEO_LCD_SSD2828
519 select VIDEO_LCD_IF_PARALLEL
520 ---help---
521 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
522
Hans de Goede743fb9552015-01-20 09:23:36 +0100523config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
524 bool "Hitachi tx18d42vm LCD panel"
525 select VIDEO_LCD_HITACHI_TX18D42VM
526 select VIDEO_LCD_IF_LVDS
527 ---help---
528 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
529
Hans de Goede613dade2015-02-16 17:49:47 +0100530config VIDEO_LCD_TL059WV5C0
531 bool "tl059wv5c0 LCD panel"
532 select VIDEO_LCD_PANEL_I2C
533 select VIDEO_LCD_IF_PARALLEL
534 ---help---
535 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
536 Aigo M60/M608/M606 tablets.
537
Hans de Goede797a0f52015-01-01 22:04:34 +0100538endchoice
539
540
Hans de Goedef494cad2015-01-11 17:17:00 +0100541config USB_MUSB_SUNXI
542 bool "Enable sunxi OTG / DRC USB controller in host mode"
543 default n
544 ---help---
545 Say y here to enable support for the sunxi OTG / DRC USB controller
546 used on almost all sunxi boards. Note currently u-boot can only have
547 one usb host controller enabled at a time, so enabling this on boards
548 which also use the ehci host controller will result in build errors.
549
Hans de Goede16030822014-09-18 21:03:34 +0200550config USB_KEYBOARD
551 boolean "Enable USB keyboard support"
552 default y
553 ---help---
554 Say Y here to add support for using a USB keyboard (typically used
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100555 in combination with a graphical console).
Hans de Goede16030822014-09-18 21:03:34 +0200556
Hans de Goedebf880fe2015-01-25 12:10:48 +0100557config GMAC_TX_DELAY
558 int "GMAC Transmit Clock Delay Chain"
559 default 0
560 ---help---
561 Set the GMAC Transmit Clock Delay Chain value.
562
Hans de Goede7976b282015-05-05 12:49:36 +0200563config SYS_MALLOC_CLEAR_ON_INIT
564 default n
565
Hans de Goede03914882015-04-15 20:46:48 +0200566config NET
567 default y
568
569config NETDEVICES
570 default y
571
572config DM_ETH
573 default y
574
575config DM_SERIAL
576 default y
577
Hans de Goede4dba1082015-05-10 14:10:26 +0200578config DM_USB
579 default y if !USB_MUSB_SUNXI
580
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900581endif