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Ian Campbelld8e69e02014-10-24 21:20:44 +01001if ARCH_SUNXI
2
3choice
4 prompt "Sunxi SoC Variant"
5
Ian Campbell4a24a1c2014-10-24 21:20:45 +01006config MACH_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +01007 bool "sun4i (Allwinner A10)"
8 select CPU_V7
9 select SUPPORT_SPL
10
Ian Campbell4a24a1c2014-10-24 21:20:45 +010011config MACH_SUN5I
Ian Campbelld8e69e02014-10-24 21:20:44 +010012 bool "sun5i (Allwinner A13)"
13 select CPU_V7
14 select SUPPORT_SPL
15
Ian Campbell4a24a1c2014-10-24 21:20:45 +010016config MACH_SUN6I
Ian Campbelld8e69e02014-10-24 21:20:44 +010017 bool "sun6i (Allwinner A31)"
18 select CPU_V7
Hans de Goedea5403b92014-10-25 20:18:10 +020019 select SUPPORT_SPL
Ian Campbelld8e69e02014-10-24 21:20:44 +010020
Ian Campbell4a24a1c2014-10-24 21:20:45 +010021config MACH_SUN7I
Ian Campbelld8e69e02014-10-24 21:20:44 +010022 bool "sun7i (Allwinner A20)"
23 select CPU_V7
Hans de Goede85437352014-11-14 09:34:30 +010024 select CPU_V7_HAS_NONSEC
25 select CPU_V7_HAS_VIRT
Ian Campbelld8e69e02014-10-24 21:20:44 +010026 select SUPPORT_SPL
Hans de Goedea5636382014-10-24 20:12:04 +020027 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010028
Ian Campbell4a24a1c2014-10-24 21:20:45 +010029config MACH_SUN8I
Ian Campbelld8e69e02014-10-24 21:20:44 +010030 bool "sun8i (Allwinner A23)"
31 select CPU_V7
Hans de Goede966d2392014-12-07 14:34:27 +010032 select SUPPORT_SPL
Ian Campbelld8e69e02014-10-24 21:20:44 +010033
34endchoice
Maxime Ripard2c519412014-10-03 20:16:29 +080035
Hans de Goede3aeaa282014-11-15 19:46:39 +010036config DRAM_CLK
Hans de Goede59d9fc72015-01-17 14:24:55 +010037 int "sunxi dram clock speed"
38 default 312 if MACH_SUN6I || MACH_SUN8I
39 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +010040 ---help---
41 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goede06ddc452015-01-25 11:29:27 +010042 of 24.
Hans de Goede3aeaa282014-11-15 19:46:39 +010043
Siarhei Siamashka47359bb2015-02-01 00:27:06 +020044if MACH_SUN5I || MACH_SUN7I
45config DRAM_MBUS_CLK
46 int "sunxi mbus clock speed"
47 default 300
48 ---help---
49 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
50
51endif
52
Hans de Goede3aeaa282014-11-15 19:46:39 +010053config DRAM_ZQ
Hans de Goede59d9fc72015-01-17 14:24:55 +010054 int "sunxi dram zq value"
55 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
56 default 127 if MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +010057 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +010058 Set the dram zq value.
Hans de Goede3aeaa282014-11-15 19:46:39 +010059
Hans de Goede59d9fc72015-01-17 14:24:55 +010060if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
61config DRAM_EMR1
62 int "sunxi dram emr1 value"
63 default 0 if MACH_SUN4I
64 default 4 if MACH_SUN5I || MACH_SUN7I
65 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +010066 Set the dram controller emr1 value.
Siarhei Siamashka9900db12015-02-01 00:27:05 +020067
Siarhei Siamashka47359bb2015-02-01 00:27:06 +020068config DRAM_ODT_EN
69 int "sunxi dram odt_en value"
70 default 0
71 ---help---
72 Set the dram controller odt_en parameter. This can be used to
73 enable/disable the ODT feature.
74
75config DRAM_TPR3
76 hex "sunxi dram tpr3 value"
77 default 0
78 ---help---
79 Set the dram controller tpr3 parameter. This parameter configures
80 the delay on the command lane and also phase shifts, which are
81 applied for sampling incoming read data. The default value 0
82 means that no phase/delay adjustments are necessary. Properly
83 configuring this parameter increases reliability at high DRAM
84 clock speeds.
85
86config DRAM_DQS_GATING_DELAY
87 hex "sunxi dram dqs_gating_delay value"
88 default 0
89 ---help---
90 Set the dram controller dqs_gating_delay parmeter. Each byte
91 encodes the DQS gating delay for each byte lane. The delay
92 granularity is 1/4 cycle. For example, the value 0x05060606
93 means that the delay is 5 quarter-cycles for one lane (1.25
94 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
95 The default value 0 means autodetection. The results of hardware
96 autodetection are not very reliable and depend on the chip
97 temperature (sometimes producing different results on cold start
98 and warm reboot). But the accuracy of hardware autodetection
99 is usually good enough, unless running at really high DRAM
100 clocks speeds (up to 600MHz). If unsure, keep as 0.
101
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200102choice
103 prompt "sunxi dram timings"
104 default DRAM_TIMINGS_VENDOR_MAGIC
105 ---help---
106 Select the timings of the DDR3 chips.
107
108config DRAM_TIMINGS_VENDOR_MAGIC
109 bool "Magic vendor timings from Android"
110 ---help---
111 The same DRAM timings as in the Allwinner boot0 bootloader.
112
113config DRAM_TIMINGS_DDR3_1066F_1333H
114 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
115 ---help---
116 Use the timings of the standard JEDEC DDR3-1066F speed bin for
117 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
118 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
119 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
120 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
121 that down binning to DDR3-1066F is supported (because DDR3-1066F
122 uses a bit faster timings than DDR3-1333H).
123
124config DRAM_TIMINGS_DDR3_800E_1066G_1333J
125 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
126 ---help---
127 Use the timings of the slowest possible JEDEC speed bin for the
128 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
129 DDR3-800E, DDR3-1066G or DDR3-1333J.
130
131endchoice
132
Hans de Goede3aeaa282014-11-15 19:46:39 +0100133endif
134
Maxime Ripard2c519412014-10-03 20:16:29 +0800135config SYS_CONFIG_NAME
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100136 default "sun4i" if MACH_SUN4I
137 default "sun5i" if MACH_SUN5I
138 default "sun6i" if MACH_SUN6I
139 default "sun7i" if MACH_SUN7I
140 default "sun8i" if MACH_SUN8I
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900141
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900142config SYS_BOARD
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900143 default "sunxi"
144
145config SYS_SOC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900146 default "sunxi"
147
Ian Campbell8ad104b2014-10-24 21:20:46 +0100148config SPL_FEL
149 bool "SPL/FEL mode support"
150 depends on SPL
151 default n
Simon Glass5debe1f2015-02-07 10:47:30 -0700152 help
153 This enables support for Fast Early Loader (FEL) mode. This
154 allows U-Boot to be loaded to the board over USB by the on-chip
155 boot rom. U-Boot should be sent in two parts: SPL first, with
156 'fel write 0x2000 u-boot-spl.bin; fel exe 0x2000' then U-Boot with
157 'fel write 0x4a000000 u-boot.bin; fel exe 0x4a000000'. This option
158 shrinks the amount of SRAM available to SPL, so only enable it if
159 you need FEL. Note that enabling this option only allows FEL to be
160 used; it is still possible to boot U-Boot from boot media. U-Boot
161 SPL detects when it is being loaded using FEL.
Ian Campbell8ad104b2014-10-24 21:20:46 +0100162
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200163config UART0_PORT_F
164 bool "UART0 on MicroSD breakout board"
165 depends on SPL_FEL
166 default n
167 ---help---
168 Repurpose the SD card slot for getting access to the UART0 serial
169 console. Primarily useful only for low level u-boot debugging on
170 tablets, where normal UART0 is difficult to access and requires
171 device disassembly and/or soldering. As the SD card can't be used
172 at the same time, the system can be only booted in the FEL mode.
173 Only enable this if you really know what you are doing.
174
Ian Campbell9536fc42014-08-31 13:13:43 +0100175config FDTFILE
176 string "Default fdtfile env setting for this board"
Hans de Goede2f60c312014-08-01 09:37:58 +0200177
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200178config OLD_SUNXI_KERNEL_COMPAT
179 boolean "Enable workarounds for booting old kernels"
180 default n
181 ---help---
182 Set this to enable various workarounds for old kernels, this results in
183 sub-optimal settings for newer kernels, only enable if needed.
184
Hans de Goede7412ef82014-10-02 20:29:26 +0200185config MMC0_CD_PIN
186 string "Card detect pin for mmc0"
187 default ""
188 ---help---
189 Set the card detect pin for mmc0, leave empty to not use cd. This
190 takes a string in the format understood by sunxi_name_to_gpio, e.g.
191 PH1 for pin 1 of port H.
192
193config MMC1_CD_PIN
194 string "Card detect pin for mmc1"
195 default ""
196 ---help---
197 See MMC0_CD_PIN help text.
198
199config MMC2_CD_PIN
200 string "Card detect pin for mmc2"
201 default ""
202 ---help---
203 See MMC0_CD_PIN help text.
204
205config MMC3_CD_PIN
206 string "Card detect pin for mmc3"
207 default ""
208 ---help---
209 See MMC0_CD_PIN help text.
210
Hans de Goedeaf593e42014-10-02 20:43:50 +0200211config MMC_SUNXI_SLOT_EXTRA
212 int "mmc extra slot number"
213 default -1
214 ---help---
215 sunxi builds always enable mmc0, some boards also have a second sdcard
216 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
217 support for this.
218
Hans de Goedee7b852a2015-01-07 15:26:06 +0100219config USB0_VBUS_PIN
220 string "Vbus enable pin for usb0 (otg)"
221 default ""
222 ---help---
223 Set the Vbus enable pin for usb0 (otg). This takes a string in the
224 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
225
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100226config USB0_VBUS_DET
227 string "Vbus detect pin for usb0 (otg)"
228 depends on USB_MUSB_SUNXI
229 default ""
230 ---help---
231 Set the Vbus detect pin for usb0 (otg). This takes a string in the
232 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
233
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100234config USB1_VBUS_PIN
235 string "Vbus enable pin for usb1 (ehci0)"
236 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100237 default "PH27" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100238 ---help---
239 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
240 a string in the format understood by sunxi_name_to_gpio, e.g.
241 PH1 for pin 1 of port H.
242
243config USB2_VBUS_PIN
244 string "Vbus enable pin for usb2 (ehci1)"
245 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100246 default "PH24" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100247 ---help---
248 See USB1_VBUS_PIN help text.
249
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200250config VIDEO
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100251 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200252 default y
253 ---help---
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100254 Say Y here to add support for using a cfb console on the HDMI, LCD
255 or VGA output found on most sunxi devices. See doc/README.video for
256 info on how to select the video output and mode.
257
Hans de Goedee9544592014-12-23 23:04:35 +0100258config VIDEO_HDMI
259 boolean "HDMI output support"
260 depends on VIDEO && !MACH_SUN8I
261 default y
262 ---help---
263 Say Y here to add support for outputting video over HDMI.
264
Hans de Goede260f5202014-12-25 13:58:06 +0100265config VIDEO_VGA
266 boolean "VGA output support"
267 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
268 default n
269 ---help---
270 Say Y here to add support for outputting video over VGA.
271
Hans de Goedeac1633c2014-12-24 12:17:07 +0100272config VIDEO_VGA_VIA_LCD
273 boolean "VGA via LCD controller support"
Chen-Yu Tsai39ca4c12015-01-12 18:02:10 +0800274 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedeac1633c2014-12-24 12:17:07 +0100275 default n
276 ---help---
277 Say Y here to add support for external DACs connected to the parallel
278 LCD interface driving a VGA connector, such as found on the
279 Olimex A13 boards.
280
Hans de Goede18366f72015-01-25 15:33:07 +0100281config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
282 boolean "Force sync active high for VGA via LCD controller support"
283 depends on VIDEO_VGA_VIA_LCD
284 default n
285 ---help---
286 Say Y here if you've a board which uses opendrain drivers for the vga
287 hsync and vsync signals. Opendrain drivers cannot generate steep enough
288 positive edges for a stable video output, so on boards with opendrain
289 drivers the sync signals must always be active high.
290
Chen-Yu Tsai9ed19522015-01-12 18:02:11 +0800291config VIDEO_VGA_EXTERNAL_DAC_EN
292 string "LCD panel power enable pin"
293 depends on VIDEO_VGA_VIA_LCD
294 default ""
295 ---help---
296 Set the enable pin for the external VGA DAC. This takes a string in the
297 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
298
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100299config VIDEO_LCD_MODE
300 string "LCD panel timing details"
301 depends on VIDEO
302 default ""
303 ---help---
304 LCD panel timing details string, leave empty if there is no LCD panel.
305 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
306 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
307
Hans de Goede481b6642015-01-13 13:21:46 +0100308config VIDEO_LCD_DCLK_PHASE
309 int "LCD panel display clock phase"
310 depends on VIDEO
311 default 1
312 ---help---
313 Select LCD panel display clock phase shift, range 0-3.
314
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100315config VIDEO_LCD_POWER
316 string "LCD panel power enable pin"
317 depends on VIDEO
318 default ""
319 ---help---
320 Set the power enable pin for the LCD panel. This takes a string in the
321 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
322
Hans de Goedece9e3322015-02-16 17:26:41 +0100323config VIDEO_LCD_RESET
324 string "LCD panel reset pin"
325 depends on VIDEO
326 default ""
327 ---help---
328 Set the reset pin for the LCD panel. This takes a string in the format
329 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
330
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100331config VIDEO_LCD_BL_EN
332 string "LCD panel backlight enable pin"
333 depends on VIDEO
334 default ""
335 ---help---
336 Set the backlight enable pin for the LCD panel. This takes a string in the
337 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
338 port H.
339
340config VIDEO_LCD_BL_PWM
341 string "LCD panel backlight pwm pin"
342 depends on VIDEO
343 default ""
344 ---help---
345 Set the backlight pwm pin for the LCD panel. This takes a string in the
346 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200347
Hans de Goede2d5d3022015-01-22 21:02:42 +0100348config VIDEO_LCD_BL_PWM_ACTIVE_LOW
349 bool "LCD panel backlight pwm is inverted"
350 depends on VIDEO
351 default y
352 ---help---
353 Set this if the backlight pwm output is active low.
354
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100355config VIDEO_LCD_PANEL_I2C
356 bool "LCD panel needs to be configured via i2c"
357 depends on VIDEO
358 default m
359 ---help---
360 Say y here if the LCD panel needs to be configured via i2c. This
361 will add a bitbang i2c controller using gpios to talk to the LCD.
362
363config VIDEO_LCD_PANEL_I2C_SDA
364 string "LCD panel i2c interface SDA pin"
365 depends on VIDEO_LCD_PANEL_I2C
366 default "PG12"
367 ---help---
368 Set the SDA pin for the LCD i2c interface. This takes a string in the
369 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
370
371config VIDEO_LCD_PANEL_I2C_SCL
372 string "LCD panel i2c interface SCL pin"
373 depends on VIDEO_LCD_PANEL_I2C
374 default "PG10"
375 ---help---
376 Set the SCL pin for the LCD i2c interface. This takes a string in the
377 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
378
Hans de Goede797a0f52015-01-01 22:04:34 +0100379
380# Note only one of these may be selected at a time! But hidden choices are
381# not supported by Kconfig
382config VIDEO_LCD_IF_PARALLEL
383 bool
384
385config VIDEO_LCD_IF_LVDS
386 bool
387
388
389choice
390 prompt "LCD panel support"
391 depends on VIDEO
392 ---help---
393 Select which type of LCD panel to support.
394
395config VIDEO_LCD_PANEL_PARALLEL
396 bool "Generic parallel interface LCD panel"
397 select VIDEO_LCD_IF_PARALLEL
398
399config VIDEO_LCD_PANEL_LVDS
400 bool "Generic lvds interface LCD panel"
401 select VIDEO_LCD_IF_LVDS
402
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200403config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
404 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
405 select VIDEO_LCD_SSD2828
406 select VIDEO_LCD_IF_PARALLEL
407 ---help---
408 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
409
Hans de Goede743fb9552015-01-20 09:23:36 +0100410config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
411 bool "Hitachi tx18d42vm LCD panel"
412 select VIDEO_LCD_HITACHI_TX18D42VM
413 select VIDEO_LCD_IF_LVDS
414 ---help---
415 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
416
Hans de Goede613dade2015-02-16 17:49:47 +0100417config VIDEO_LCD_TL059WV5C0
418 bool "tl059wv5c0 LCD panel"
419 select VIDEO_LCD_PANEL_I2C
420 select VIDEO_LCD_IF_PARALLEL
421 ---help---
422 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
423 Aigo M60/M608/M606 tablets.
424
Hans de Goede797a0f52015-01-01 22:04:34 +0100425endchoice
426
427
Hans de Goedef494cad2015-01-11 17:17:00 +0100428config USB_MUSB_SUNXI
429 bool "Enable sunxi OTG / DRC USB controller in host mode"
430 default n
431 ---help---
432 Say y here to enable support for the sunxi OTG / DRC USB controller
433 used on almost all sunxi boards. Note currently u-boot can only have
434 one usb host controller enabled at a time, so enabling this on boards
435 which also use the ehci host controller will result in build errors.
436
Hans de Goede16030822014-09-18 21:03:34 +0200437config USB_KEYBOARD
438 boolean "Enable USB keyboard support"
439 default y
440 ---help---
441 Say Y here to add support for using a USB keyboard (typically used
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100442 in combination with a graphical console).
Hans de Goede16030822014-09-18 21:03:34 +0200443
Hans de Goedebf880fe2015-01-25 12:10:48 +0100444config GMAC_TX_DELAY
445 int "GMAC Transmit Clock Delay Chain"
446 default 0
447 ---help---
448 Set the GMAC Transmit Clock Delay Chain value.
449
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900450endif