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Ian Campbelld8e69e02014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Simon Glass0bdfc3e2016-09-12 23:18:39 -06003config SPL_GPIO_SUPPORT
4 default y
5
Simon Glassf2a89462016-09-12 23:18:41 -06006config SPL_LIBCOMMON_SUPPORT
7 default y
8
Hans de Goedef07872b2015-04-06 20:33:34 +02009# Note only one of these may be selected at a time! But hidden choices are
10# not supported by Kconfig
11config SUNXI_GEN_SUN4I
12 bool
13 ---help---
14 Select this for sunxi SoCs which have resets and clocks set up
15 as the original A10 (mach-sun4i).
16
17config SUNXI_GEN_SUN6I
18 bool
19 ---help---
20 Select this for sunxi SoCs which have sun6i like periphery, like
21 separate ahb reset control registers, custom pmic bus, new style
22 watchdog, etc.
23
24
Ian Campbelld8e69e02014-10-24 21:20:44 +010025choice
26 prompt "Sunxi SoC Variant"
Hans de Goedeb05a6482016-06-12 11:57:07 +020027 optional
Ian Campbelld8e69e02014-10-24 21:20:44 +010028
Ian Campbell4a24a1c2014-10-24 21:20:45 +010029config MACH_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010030 bool "sun4i (Allwinner A10)"
31 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020032 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010033 select SUPPORT_SPL
34
Ian Campbell4a24a1c2014-10-24 21:20:45 +010035config MACH_SUN5I
Ian Campbelld8e69e02014-10-24 21:20:44 +010036 bool "sun5i (Allwinner A13)"
37 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020038 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010039 select SUPPORT_SPL
40
Ian Campbell4a24a1c2014-10-24 21:20:45 +010041config MACH_SUN6I
Ian Campbelld8e69e02014-10-24 21:20:44 +010042 bool "sun6i (Allwinner A31)"
43 select CPU_V7
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080044 select CPU_V7_HAS_NONSEC
45 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090046 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020047 select SUNXI_GEN_SUN6I
Hans de Goedea5403b92014-10-25 20:18:10 +020048 select SUPPORT_SPL
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080049 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010050
Ian Campbell4a24a1c2014-10-24 21:20:45 +010051config MACH_SUN7I
Ian Campbelld8e69e02014-10-24 21:20:44 +010052 bool "sun7i (Allwinner A20)"
53 select CPU_V7
Hans de Goede85437352014-11-14 09:34:30 +010054 select CPU_V7_HAS_NONSEC
55 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090056 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020057 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010058 select SUPPORT_SPL
Hans de Goedea5636382014-10-24 20:12:04 +020059 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010060
Hans de Goedef055ed62015-04-06 20:55:39 +020061config MACH_SUN8I_A23
Ian Campbelld8e69e02014-10-24 21:20:44 +010062 bool "sun8i (Allwinner A23)"
63 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080064 select CPU_V7_HAS_NONSEC
65 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090066 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020067 select SUNXI_GEN_SUN6I
Hans de Goede966d2392014-12-07 14:34:27 +010068 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080069 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010070
Vishnu Patekar3702f142015-03-01 23:47:48 +053071config MACH_SUN8I_A33
72 bool "sun8i (Allwinner A33)"
73 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080074 select CPU_V7_HAS_NONSEC
75 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090076 select ARCH_SUPPORT_PSCI
Vishnu Patekar3702f142015-03-01 23:47:48 +053077 select SUNXI_GEN_SUN6I
78 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080079 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar3702f142015-03-01 23:47:48 +053080
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +080081config MACH_SUN8I_A83T
82 bool "sun8i (Allwinner A83T)"
83 select CPU_V7
84 select SUNXI_GEN_SUN6I
85 select SUPPORT_SPL
86
Jens Kuskef9770722015-11-17 15:12:58 +010087config MACH_SUN8I_H3
88 bool "sun8i (Allwinner H3)"
89 select CPU_V7
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +080090 select CPU_V7_HAS_NONSEC
91 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090092 select ARCH_SUPPORT_PSCI
Jens Kuskef9770722015-11-17 15:12:58 +010093 select SUNXI_GEN_SUN6I
Jens Kuske53f018e2015-11-17 15:12:59 +010094 select SUPPORT_SPL
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +080095 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuskef9770722015-11-17 15:12:58 +010096
Hans de Goede7bfe2bb2015-01-13 19:25:06 +010097config MACH_SUN9I
98 bool "sun9i (Allwinner A80)"
99 select CPU_V7
100 select SUNXI_GEN_SUN6I
101
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800102config MACH_SUN50I
103 bool "sun50i (Allwinner A64)"
104 select ARM64
105 select SUNXI_GEN_SUN6I
106
Ian Campbelld8e69e02014-10-24 21:20:44 +0100107endchoice
Maxime Ripard2c519412014-10-03 20:16:29 +0800108
Hans de Goedef055ed62015-04-06 20:55:39 +0200109# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
110config MACH_SUN8I
111 bool
vishnupatekarcdf1e482015-11-29 01:07:19 +0800112 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
Hans de Goedef055ed62015-04-06 20:55:39 +0200113
Vishnu Patekarc49936f2016-01-12 01:20:58 +0800114config DRAM_TYPE
115 int "sunxi dram type"
116 depends on MACH_SUN8I_A83T
117 default 3
118 ---help---
119 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goedef055ed62015-04-06 20:55:39 +0200120
Hans de Goede3aeaa282014-11-15 19:46:39 +0100121config DRAM_CLK
Hans de Goede59d9fc72015-01-17 14:24:55 +0100122 int "sunxi dram clock speed"
123 default 312 if MACH_SUN6I || MACH_SUN8I
124 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100125 ---help---
126 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goede06ddc452015-01-25 11:29:27 +0100127 of 24.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100128
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200129if MACH_SUN5I || MACH_SUN7I
130config DRAM_MBUS_CLK
131 int "sunxi mbus clock speed"
132 default 300
133 ---help---
134 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
135
136endif
137
Hans de Goede3aeaa282014-11-15 19:46:39 +0100138config DRAM_ZQ
Hans de Goede59d9fc72015-01-17 14:24:55 +0100139 int "sunxi dram zq value"
140 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
141 default 127 if MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100142 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100143 Set the dram zq value.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100144
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200145config DRAM_ODT_EN
146 bool "sunxi dram odt enable"
147 default n if !MACH_SUN8I_A23
148 default y if MACH_SUN8I_A23
149 ---help---
150 Select this to enable dram odt (on die termination).
151
Hans de Goede59d9fc72015-01-17 14:24:55 +0100152if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
153config DRAM_EMR1
154 int "sunxi dram emr1 value"
155 default 0 if MACH_SUN4I
156 default 4 if MACH_SUN5I || MACH_SUN7I
157 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100158 Set the dram controller emr1 value.
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200159
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200160config DRAM_TPR3
161 hex "sunxi dram tpr3 value"
162 default 0
163 ---help---
164 Set the dram controller tpr3 parameter. This parameter configures
165 the delay on the command lane and also phase shifts, which are
166 applied for sampling incoming read data. The default value 0
167 means that no phase/delay adjustments are necessary. Properly
168 configuring this parameter increases reliability at high DRAM
169 clock speeds.
170
171config DRAM_DQS_GATING_DELAY
172 hex "sunxi dram dqs_gating_delay value"
173 default 0
174 ---help---
175 Set the dram controller dqs_gating_delay parmeter. Each byte
176 encodes the DQS gating delay for each byte lane. The delay
177 granularity is 1/4 cycle. For example, the value 0x05060606
178 means that the delay is 5 quarter-cycles for one lane (1.25
179 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
180 The default value 0 means autodetection. The results of hardware
181 autodetection are not very reliable and depend on the chip
182 temperature (sometimes producing different results on cold start
183 and warm reboot). But the accuracy of hardware autodetection
184 is usually good enough, unless running at really high DRAM
185 clocks speeds (up to 600MHz). If unsure, keep as 0.
186
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200187choice
188 prompt "sunxi dram timings"
189 default DRAM_TIMINGS_VENDOR_MAGIC
190 ---help---
191 Select the timings of the DDR3 chips.
192
193config DRAM_TIMINGS_VENDOR_MAGIC
194 bool "Magic vendor timings from Android"
195 ---help---
196 The same DRAM timings as in the Allwinner boot0 bootloader.
197
198config DRAM_TIMINGS_DDR3_1066F_1333H
199 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
200 ---help---
201 Use the timings of the standard JEDEC DDR3-1066F speed bin for
202 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
203 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
204 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
205 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
206 that down binning to DDR3-1066F is supported (because DDR3-1066F
207 uses a bit faster timings than DDR3-1333H).
208
209config DRAM_TIMINGS_DDR3_800E_1066G_1333J
210 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
211 ---help---
212 Use the timings of the slowest possible JEDEC speed bin for the
213 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
214 DDR3-800E, DDR3-1066G or DDR3-1333J.
215
216endchoice
217
Hans de Goede3aeaa282014-11-15 19:46:39 +0100218endif
219
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200220if MACH_SUN8I_A23
221config DRAM_ODT_CORRECTION
222 int "sunxi dram odt correction value"
223 default 0
224 ---help---
225 Set the dram odt correction value (range -255 - 255). In allwinner
226 fex files, this option is found in bits 8-15 of the u32 odt_en variable
227 in the [dram] section. When bit 31 of the odt_en variable is set
228 then the correction is negative. Usually the value for this is 0.
229endif
230
Iain Paton630df142015-03-28 10:26:38 +0000231config SYS_CLK_FREQ
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200232 default 816000000 if MACH_SUN50I
Iain Paton630df142015-03-28 10:26:38 +0000233 default 912000000 if MACH_SUN7I
234 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
235
Maxime Ripard2c519412014-10-03 20:16:29 +0800236config SYS_CONFIG_NAME
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100237 default "sun4i" if MACH_SUN4I
238 default "sun5i" if MACH_SUN5I
239 default "sun6i" if MACH_SUN6I
240 default "sun7i" if MACH_SUN7I
241 default "sun8i" if MACH_SUN8I
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100242 default "sun9i" if MACH_SUN9I
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200243 default "sun50i" if MACH_SUN50I
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900244
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900245config SYS_BOARD
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900246 default "sunxi"
247
248config SYS_SOC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900249 default "sunxi"
250
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200251config UART0_PORT_F
252 bool "UART0 on MicroSD breakout board"
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200253 default n
254 ---help---
255 Repurpose the SD card slot for getting access to the UART0 serial
256 console. Primarily useful only for low level u-boot debugging on
257 tablets, where normal UART0 is difficult to access and requires
258 device disassembly and/or soldering. As the SD card can't be used
259 at the same time, the system can be only booted in the FEL mode.
260 Only enable this if you really know what you are doing.
261
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200262config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900263 bool "Enable workarounds for booting old kernels"
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200264 default n
265 ---help---
266 Set this to enable various workarounds for old kernels, this results in
267 sub-optimal settings for newer kernels, only enable if needed.
268
Maxime Riparde0c7aa42015-10-15 22:04:07 +0200269config MMC
270 depends on !UART0_PORT_F
271 default y if ARCH_SUNXI
272
Hans de Goede7412ef82014-10-02 20:29:26 +0200273config MMC0_CD_PIN
274 string "Card detect pin for mmc0"
Chen-Yu Tsai36741482016-05-02 10:28:08 +0800275 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
Hans de Goede7412ef82014-10-02 20:29:26 +0200276 default ""
277 ---help---
278 Set the card detect pin for mmc0, leave empty to not use cd. This
279 takes a string in the format understood by sunxi_name_to_gpio, e.g.
280 PH1 for pin 1 of port H.
281
282config MMC1_CD_PIN
283 string "Card detect pin for mmc1"
284 default ""
285 ---help---
286 See MMC0_CD_PIN help text.
287
288config MMC2_CD_PIN
289 string "Card detect pin for mmc2"
290 default ""
291 ---help---
292 See MMC0_CD_PIN help text.
293
294config MMC3_CD_PIN
295 string "Card detect pin for mmc3"
296 default ""
297 ---help---
298 See MMC0_CD_PIN help text.
299
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100300config MMC1_PINS
301 string "Pins for mmc1"
302 default ""
303 ---help---
304 Set the pins used for mmc1, when applicable. This takes a string in the
305 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
306
307config MMC2_PINS
308 string "Pins for mmc2"
309 default ""
310 ---help---
311 See MMC1_PINS help text.
312
313config MMC3_PINS
314 string "Pins for mmc3"
315 default ""
316 ---help---
317 See MMC1_PINS help text.
318
Hans de Goedeaf593e42014-10-02 20:43:50 +0200319config MMC_SUNXI_SLOT_EXTRA
320 int "mmc extra slot number"
321 default -1
322 ---help---
323 sunxi builds always enable mmc0, some boards also have a second sdcard
324 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
325 support for this.
326
Hans de Goede99c9fb02016-04-01 22:39:26 +0200327config INITIAL_USB_SCAN_DELAY
328 int "delay initial usb scan by x ms to allow builtin devices to init"
329 default 0
330 ---help---
331 Some boards have on board usb devices which need longer than the
332 USB spec's 1 second to connect from board powerup. Set this config
333 option to a non 0 value to add an extra delay before the first usb
334 bus scan.
335
Hans de Goedee7b852a2015-01-07 15:26:06 +0100336config USB0_VBUS_PIN
337 string "Vbus enable pin for usb0 (otg)"
338 default ""
339 ---help---
340 Set the Vbus enable pin for usb0 (otg). This takes a string in the
341 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
342
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100343config USB0_VBUS_DET
344 string "Vbus detect pin for usb0 (otg)"
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100345 default ""
346 ---help---
347 Set the Vbus detect pin for usb0 (otg). This takes a string in the
348 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
349
Hans de Goedeaadd97f2015-06-14 17:29:53 +0200350config USB0_ID_DET
351 string "ID detect pin for usb0 (otg)"
352 default ""
353 ---help---
354 Set the ID detect pin for usb0 (otg). This takes a string in the
355 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
356
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100357config USB1_VBUS_PIN
358 string "Vbus enable pin for usb1 (ehci0)"
359 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100360 default "PH27" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100361 ---help---
362 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
363 a string in the format understood by sunxi_name_to_gpio, e.g.
364 PH1 for pin 1 of port H.
365
366config USB2_VBUS_PIN
367 string "Vbus enable pin for usb2 (ehci1)"
368 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100369 default "PH24" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100370 ---help---
371 See USB1_VBUS_PIN help text.
372
Hans de Goedea60c3fc2016-03-18 08:42:01 +0100373config USB3_VBUS_PIN
374 string "Vbus enable pin for usb3 (ehci2)"
375 default ""
376 ---help---
377 See USB1_VBUS_PIN help text.
378
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200379config I2C0_ENABLE
380 bool "Enable I2C/TWI controller 0"
381 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
382 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede2c526402016-05-15 13:51:58 +0200383 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200384 ---help---
385 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
386 its clock and setting up the bus. This is especially useful on devices
387 with slaves connected to the bus or with pins exposed through e.g. an
388 expansion port/header.
389
390config I2C1_ENABLE
391 bool "Enable I2C/TWI controller 1"
392 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200393 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200394 ---help---
395 See I2C0_ENABLE help text.
396
397config I2C2_ENABLE
398 bool "Enable I2C/TWI controller 2"
399 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200400 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200401 ---help---
402 See I2C0_ENABLE help text.
403
404if MACH_SUN6I || MACH_SUN7I
405config I2C3_ENABLE
406 bool "Enable I2C/TWI controller 3"
407 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200408 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200409 ---help---
410 See I2C0_ENABLE help text.
411endif
412
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100413if SUNXI_GEN_SUN6I
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100414config R_I2C_ENABLE
415 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100416 # This is used for the pmic on H3
417 default y if SY8106A_POWER
Hans de Goede2c526402016-05-15 13:51:58 +0200418 select CMD_I2C
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100419 ---help---
420 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100421endif
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100422
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200423if MACH_SUN7I
424config I2C4_ENABLE
425 bool "Enable I2C/TWI controller 4"
426 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200427 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200428 ---help---
429 See I2C0_ENABLE help text.
430endif
431
Hans de Goede3ae1d132015-04-25 17:25:14 +0200432config AXP_GPIO
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900433 bool "Enable support for gpio-s on axp PMICs"
Hans de Goede3ae1d132015-04-25 17:25:14 +0200434 default n
435 ---help---
436 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
437
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200438config VIDEO
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900439 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Andre Przywara8f977272016-09-05 01:32:40 +0100440 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200441 default y
442 ---help---
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100443 Say Y here to add support for using a cfb console on the HDMI, LCD
444 or VGA output found on most sunxi devices. See doc/README.video for
445 info on how to select the video output and mode.
446
Hans de Goedee9544592014-12-23 23:04:35 +0100447config VIDEO_HDMI
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900448 bool "HDMI output support"
Hans de Goedee9544592014-12-23 23:04:35 +0100449 depends on VIDEO && !MACH_SUN8I
450 default y
451 ---help---
452 Say Y here to add support for outputting video over HDMI.
453
Hans de Goede260f5202014-12-25 13:58:06 +0100454config VIDEO_VGA
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900455 bool "VGA output support"
Hans de Goede260f5202014-12-25 13:58:06 +0100456 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
457 default n
458 ---help---
459 Say Y here to add support for outputting video over VGA.
460
Hans de Goedeac1633c2014-12-24 12:17:07 +0100461config VIDEO_VGA_VIA_LCD
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900462 bool "VGA via LCD controller support"
Chen-Yu Tsai39ca4c12015-01-12 18:02:10 +0800463 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedeac1633c2014-12-24 12:17:07 +0100464 default n
465 ---help---
466 Say Y here to add support for external DACs connected to the parallel
467 LCD interface driving a VGA connector, such as found on the
468 Olimex A13 boards.
469
Hans de Goede18366f72015-01-25 15:33:07 +0100470config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900471 bool "Force sync active high for VGA via LCD controller support"
Hans de Goede18366f72015-01-25 15:33:07 +0100472 depends on VIDEO_VGA_VIA_LCD
473 default n
474 ---help---
475 Say Y here if you've a board which uses opendrain drivers for the vga
476 hsync and vsync signals. Opendrain drivers cannot generate steep enough
477 positive edges for a stable video output, so on boards with opendrain
478 drivers the sync signals must always be active high.
479
Chen-Yu Tsai9ed19522015-01-12 18:02:11 +0800480config VIDEO_VGA_EXTERNAL_DAC_EN
481 string "LCD panel power enable pin"
482 depends on VIDEO_VGA_VIA_LCD
483 default ""
484 ---help---
485 Set the enable pin for the external VGA DAC. This takes a string in the
486 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
487
Hans de Goedec06e00e2015-08-03 19:20:26 +0200488config VIDEO_COMPOSITE
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900489 bool "Composite video output support"
Hans de Goedec06e00e2015-08-03 19:20:26 +0200490 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
491 default n
492 ---help---
493 Say Y here to add support for outputting composite video.
494
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100495config VIDEO_LCD_MODE
496 string "LCD panel timing details"
497 depends on VIDEO
498 default ""
499 ---help---
500 LCD panel timing details string, leave empty if there is no LCD panel.
501 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
502 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede924c8932015-08-16 11:23:42 +0200503 Also see: http://linux-sunxi.org/LCD
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100504
Hans de Goede481b6642015-01-13 13:21:46 +0100505config VIDEO_LCD_DCLK_PHASE
506 int "LCD panel display clock phase"
507 depends on VIDEO
508 default 1
509 ---help---
510 Select LCD panel display clock phase shift, range 0-3.
511
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100512config VIDEO_LCD_POWER
513 string "LCD panel power enable pin"
514 depends on VIDEO
515 default ""
516 ---help---
517 Set the power enable pin for the LCD panel. This takes a string in the
518 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
519
Hans de Goedece9e3322015-02-16 17:26:41 +0100520config VIDEO_LCD_RESET
521 string "LCD panel reset pin"
522 depends on VIDEO
523 default ""
524 ---help---
525 Set the reset pin for the LCD panel. This takes a string in the format
526 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
527
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100528config VIDEO_LCD_BL_EN
529 string "LCD panel backlight enable pin"
530 depends on VIDEO
531 default ""
532 ---help---
533 Set the backlight enable pin for the LCD panel. This takes a string in the
534 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
535 port H.
536
537config VIDEO_LCD_BL_PWM
538 string "LCD panel backlight pwm pin"
539 depends on VIDEO
540 default ""
541 ---help---
542 Set the backlight pwm pin for the LCD panel. This takes a string in the
543 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200544
Hans de Goede2d5d3022015-01-22 21:02:42 +0100545config VIDEO_LCD_BL_PWM_ACTIVE_LOW
546 bool "LCD panel backlight pwm is inverted"
547 depends on VIDEO
548 default y
549 ---help---
550 Set this if the backlight pwm output is active low.
551
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100552config VIDEO_LCD_PANEL_I2C
553 bool "LCD panel needs to be configured via i2c"
554 depends on VIDEO
Hans de Goede6de9f762015-03-07 12:00:02 +0100555 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200556 select CMD_I2C
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100557 ---help---
558 Say y here if the LCD panel needs to be configured via i2c. This
559 will add a bitbang i2c controller using gpios to talk to the LCD.
560
561config VIDEO_LCD_PANEL_I2C_SDA
562 string "LCD panel i2c interface SDA pin"
563 depends on VIDEO_LCD_PANEL_I2C
564 default "PG12"
565 ---help---
566 Set the SDA pin for the LCD i2c interface. This takes a string in the
567 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
568
569config VIDEO_LCD_PANEL_I2C_SCL
570 string "LCD panel i2c interface SCL pin"
571 depends on VIDEO_LCD_PANEL_I2C
572 default "PG10"
573 ---help---
574 Set the SCL pin for the LCD i2c interface. This takes a string in the
575 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
576
Hans de Goede797a0f52015-01-01 22:04:34 +0100577
578# Note only one of these may be selected at a time! But hidden choices are
579# not supported by Kconfig
580config VIDEO_LCD_IF_PARALLEL
581 bool
582
583config VIDEO_LCD_IF_LVDS
584 bool
585
586
587choice
588 prompt "LCD panel support"
589 depends on VIDEO
590 ---help---
591 Select which type of LCD panel to support.
592
593config VIDEO_LCD_PANEL_PARALLEL
594 bool "Generic parallel interface LCD panel"
595 select VIDEO_LCD_IF_PARALLEL
596
597config VIDEO_LCD_PANEL_LVDS
598 bool "Generic lvds interface LCD panel"
599 select VIDEO_LCD_IF_LVDS
600
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200601config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
602 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
603 select VIDEO_LCD_SSD2828
604 select VIDEO_LCD_IF_PARALLEL
605 ---help---
Hans de Goede91f1b822015-08-08 16:13:53 +0200606 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
607
608config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
609 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
610 select VIDEO_LCD_ANX9804
611 select VIDEO_LCD_IF_PARALLEL
612 select VIDEO_LCD_PANEL_I2C
613 ---help---
614 Select this for eDP LCD panels with 4 lanes running at 1.62G,
615 connected via an ANX9804 bridge chip.
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200616
Hans de Goede743fb9552015-01-20 09:23:36 +0100617config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
618 bool "Hitachi tx18d42vm LCD panel"
619 select VIDEO_LCD_HITACHI_TX18D42VM
620 select VIDEO_LCD_IF_LVDS
621 ---help---
622 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
623
Hans de Goede613dade2015-02-16 17:49:47 +0100624config VIDEO_LCD_TL059WV5C0
625 bool "tl059wv5c0 LCD panel"
626 select VIDEO_LCD_PANEL_I2C
627 select VIDEO_LCD_IF_PARALLEL
628 ---help---
629 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
630 Aigo M60/M608/M606 tablets.
631
Hans de Goede797a0f52015-01-01 22:04:34 +0100632endchoice
633
634
Hans de Goedebf880fe2015-01-25 12:10:48 +0100635config GMAC_TX_DELAY
636 int "GMAC Transmit Clock Delay Chain"
637 default 0
638 ---help---
639 Set the GMAC Transmit Clock Delay Chain value.
640
Hans de Goede66ab79d2015-09-13 13:02:48 +0200641config SPL_STACK_R_ADDR
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200642 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
Hans de Goede66ab79d2015-09-13 13:02:48 +0200643 default 0x2fe00000 if MACH_SUN9I
644
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900645endif