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Ian Campbelld8e69e02014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Hans de Goedef07872b2015-04-06 20:33:34 +02003# Note only one of these may be selected at a time! But hidden choices are
4# not supported by Kconfig
5config SUNXI_GEN_SUN4I
6 bool
7 ---help---
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
10
11config SUNXI_GEN_SUN6I
12 bool
13 ---help---
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
16 watchdog, etc.
17
18
Ian Campbelld8e69e02014-10-24 21:20:44 +010019choice
20 prompt "Sunxi SoC Variant"
21
Ian Campbell4a24a1c2014-10-24 21:20:45 +010022config MACH_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010023 bool "sun4i (Allwinner A10)"
24 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020025 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010026 select SUPPORT_SPL
27
Ian Campbell4a24a1c2014-10-24 21:20:45 +010028config MACH_SUN5I
Ian Campbelld8e69e02014-10-24 21:20:44 +010029 bool "sun5i (Allwinner A13)"
30 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020031 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010032 select SUPPORT_SPL
33
Ian Campbell4a24a1c2014-10-24 21:20:45 +010034config MACH_SUN6I
Ian Campbelld8e69e02014-10-24 21:20:44 +010035 bool "sun6i (Allwinner A31)"
36 select CPU_V7
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080037 select CPU_V7_HAS_NONSEC
38 select CPU_V7_HAS_VIRT
Hans de Goedef07872b2015-04-06 20:33:34 +020039 select SUNXI_GEN_SUN6I
Hans de Goedea5403b92014-10-25 20:18:10 +020040 select SUPPORT_SPL
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080041 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010042
Ian Campbell4a24a1c2014-10-24 21:20:45 +010043config MACH_SUN7I
Ian Campbelld8e69e02014-10-24 21:20:44 +010044 bool "sun7i (Allwinner A20)"
45 select CPU_V7
Hans de Goede85437352014-11-14 09:34:30 +010046 select CPU_V7_HAS_NONSEC
47 select CPU_V7_HAS_VIRT
Hans de Goedef07872b2015-04-06 20:33:34 +020048 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010049 select SUPPORT_SPL
Hans de Goedea5636382014-10-24 20:12:04 +020050 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010051
Hans de Goedef055ed62015-04-06 20:55:39 +020052config MACH_SUN8I_A23
Ian Campbelld8e69e02014-10-24 21:20:44 +010053 bool "sun8i (Allwinner A23)"
54 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080055 select CPU_V7_HAS_NONSEC
56 select CPU_V7_HAS_VIRT
Hans de Goedef07872b2015-04-06 20:33:34 +020057 select SUNXI_GEN_SUN6I
Hans de Goede966d2392014-12-07 14:34:27 +010058 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080059 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010060
Vishnu Patekar3702f142015-03-01 23:47:48 +053061config MACH_SUN8I_A33
62 bool "sun8i (Allwinner A33)"
63 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080064 select CPU_V7_HAS_NONSEC
65 select CPU_V7_HAS_VIRT
Vishnu Patekar3702f142015-03-01 23:47:48 +053066 select SUNXI_GEN_SUN6I
67 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080068 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar3702f142015-03-01 23:47:48 +053069
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +080070config MACH_SUN8I_A83T
71 bool "sun8i (Allwinner A83T)"
72 select CPU_V7
73 select SUNXI_GEN_SUN6I
74 select SUPPORT_SPL
75
Jens Kuskef9770722015-11-17 15:12:58 +010076config MACH_SUN8I_H3
77 bool "sun8i (Allwinner H3)"
78 select CPU_V7
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +080079 select CPU_V7_HAS_NONSEC
80 select CPU_V7_HAS_VIRT
Jens Kuskef9770722015-11-17 15:12:58 +010081 select SUNXI_GEN_SUN6I
Jens Kuske53f018e2015-11-17 15:12:59 +010082 select SUPPORT_SPL
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +080083 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuskef9770722015-11-17 15:12:58 +010084
Hans de Goede7bfe2bb2015-01-13 19:25:06 +010085config MACH_SUN9I
86 bool "sun9i (Allwinner A80)"
87 select CPU_V7
88 select SUNXI_GEN_SUN6I
89
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +080090config MACH_SUN50I
91 bool "sun50i (Allwinner A64)"
92 select ARM64
93 select SUNXI_GEN_SUN6I
94
Ian Campbelld8e69e02014-10-24 21:20:44 +010095endchoice
Maxime Ripard2c519412014-10-03 20:16:29 +080096
Hans de Goedef055ed62015-04-06 20:55:39 +020097# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
98config MACH_SUN8I
99 bool
vishnupatekarcdf1e482015-11-29 01:07:19 +0800100 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
Hans de Goedef055ed62015-04-06 20:55:39 +0200101
Vishnu Patekarc49936f2016-01-12 01:20:58 +0800102config DRAM_TYPE
103 int "sunxi dram type"
104 depends on MACH_SUN8I_A83T
105 default 3
106 ---help---
107 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goedef055ed62015-04-06 20:55:39 +0200108
Hans de Goede3aeaa282014-11-15 19:46:39 +0100109config DRAM_CLK
Hans de Goede59d9fc72015-01-17 14:24:55 +0100110 int "sunxi dram clock speed"
111 default 312 if MACH_SUN6I || MACH_SUN8I
112 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100113 ---help---
114 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goede06ddc452015-01-25 11:29:27 +0100115 of 24.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100116
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200117if MACH_SUN5I || MACH_SUN7I
118config DRAM_MBUS_CLK
119 int "sunxi mbus clock speed"
120 default 300
121 ---help---
122 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
123
124endif
125
Hans de Goede3aeaa282014-11-15 19:46:39 +0100126config DRAM_ZQ
Hans de Goede59d9fc72015-01-17 14:24:55 +0100127 int "sunxi dram zq value"
128 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
129 default 127 if MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100130 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100131 Set the dram zq value.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100132
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200133config DRAM_ODT_EN
134 bool "sunxi dram odt enable"
135 default n if !MACH_SUN8I_A23
136 default y if MACH_SUN8I_A23
137 ---help---
138 Select this to enable dram odt (on die termination).
139
Hans de Goede59d9fc72015-01-17 14:24:55 +0100140if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
141config DRAM_EMR1
142 int "sunxi dram emr1 value"
143 default 0 if MACH_SUN4I
144 default 4 if MACH_SUN5I || MACH_SUN7I
145 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100146 Set the dram controller emr1 value.
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200147
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200148config DRAM_TPR3
149 hex "sunxi dram tpr3 value"
150 default 0
151 ---help---
152 Set the dram controller tpr3 parameter. This parameter configures
153 the delay on the command lane and also phase shifts, which are
154 applied for sampling incoming read data. The default value 0
155 means that no phase/delay adjustments are necessary. Properly
156 configuring this parameter increases reliability at high DRAM
157 clock speeds.
158
159config DRAM_DQS_GATING_DELAY
160 hex "sunxi dram dqs_gating_delay value"
161 default 0
162 ---help---
163 Set the dram controller dqs_gating_delay parmeter. Each byte
164 encodes the DQS gating delay for each byte lane. The delay
165 granularity is 1/4 cycle. For example, the value 0x05060606
166 means that the delay is 5 quarter-cycles for one lane (1.25
167 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
168 The default value 0 means autodetection. The results of hardware
169 autodetection are not very reliable and depend on the chip
170 temperature (sometimes producing different results on cold start
171 and warm reboot). But the accuracy of hardware autodetection
172 is usually good enough, unless running at really high DRAM
173 clocks speeds (up to 600MHz). If unsure, keep as 0.
174
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200175choice
176 prompt "sunxi dram timings"
177 default DRAM_TIMINGS_VENDOR_MAGIC
178 ---help---
179 Select the timings of the DDR3 chips.
180
181config DRAM_TIMINGS_VENDOR_MAGIC
182 bool "Magic vendor timings from Android"
183 ---help---
184 The same DRAM timings as in the Allwinner boot0 bootloader.
185
186config DRAM_TIMINGS_DDR3_1066F_1333H
187 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
188 ---help---
189 Use the timings of the standard JEDEC DDR3-1066F speed bin for
190 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
191 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
192 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
193 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
194 that down binning to DDR3-1066F is supported (because DDR3-1066F
195 uses a bit faster timings than DDR3-1333H).
196
197config DRAM_TIMINGS_DDR3_800E_1066G_1333J
198 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
199 ---help---
200 Use the timings of the slowest possible JEDEC speed bin for the
201 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
202 DDR3-800E, DDR3-1066G or DDR3-1333J.
203
204endchoice
205
Hans de Goede3aeaa282014-11-15 19:46:39 +0100206endif
207
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200208if MACH_SUN8I_A23
209config DRAM_ODT_CORRECTION
210 int "sunxi dram odt correction value"
211 default 0
212 ---help---
213 Set the dram odt correction value (range -255 - 255). In allwinner
214 fex files, this option is found in bits 8-15 of the u32 odt_en variable
215 in the [dram] section. When bit 31 of the odt_en variable is set
216 then the correction is negative. Usually the value for this is 0.
217endif
218
Iain Paton630df142015-03-28 10:26:38 +0000219config SYS_CLK_FREQ
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200220 default 816000000 if MACH_SUN50I
Iain Paton630df142015-03-28 10:26:38 +0000221 default 912000000 if MACH_SUN7I
222 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
223
Maxime Ripard2c519412014-10-03 20:16:29 +0800224config SYS_CONFIG_NAME
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100225 default "sun4i" if MACH_SUN4I
226 default "sun5i" if MACH_SUN5I
227 default "sun6i" if MACH_SUN6I
228 default "sun7i" if MACH_SUN7I
229 default "sun8i" if MACH_SUN8I
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100230 default "sun9i" if MACH_SUN9I
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200231 default "sun50i" if MACH_SUN50I
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900232
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900233config SYS_BOARD
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900234 default "sunxi"
235
236config SYS_SOC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900237 default "sunxi"
238
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200239config UART0_PORT_F
240 bool "UART0 on MicroSD breakout board"
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200241 default n
242 ---help---
243 Repurpose the SD card slot for getting access to the UART0 serial
244 console. Primarily useful only for low level u-boot debugging on
245 tablets, where normal UART0 is difficult to access and requires
246 device disassembly and/or soldering. As the SD card can't be used
247 at the same time, the system can be only booted in the FEL mode.
248 Only enable this if you really know what you are doing.
249
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200250config OLD_SUNXI_KERNEL_COMPAT
251 boolean "Enable workarounds for booting old kernels"
252 default n
253 ---help---
254 Set this to enable various workarounds for old kernels, this results in
255 sub-optimal settings for newer kernels, only enable if needed.
256
Maxime Riparde0c7aa42015-10-15 22:04:07 +0200257config MMC
258 depends on !UART0_PORT_F
259 default y if ARCH_SUNXI
260
Hans de Goede7412ef82014-10-02 20:29:26 +0200261config MMC0_CD_PIN
262 string "Card detect pin for mmc0"
263 default ""
264 ---help---
265 Set the card detect pin for mmc0, leave empty to not use cd. This
266 takes a string in the format understood by sunxi_name_to_gpio, e.g.
267 PH1 for pin 1 of port H.
268
269config MMC1_CD_PIN
270 string "Card detect pin for mmc1"
271 default ""
272 ---help---
273 See MMC0_CD_PIN help text.
274
275config MMC2_CD_PIN
276 string "Card detect pin for mmc2"
277 default ""
278 ---help---
279 See MMC0_CD_PIN help text.
280
281config MMC3_CD_PIN
282 string "Card detect pin for mmc3"
283 default ""
284 ---help---
285 See MMC0_CD_PIN help text.
286
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100287config MMC1_PINS
288 string "Pins for mmc1"
289 default ""
290 ---help---
291 Set the pins used for mmc1, when applicable. This takes a string in the
292 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
293
294config MMC2_PINS
295 string "Pins for mmc2"
296 default ""
297 ---help---
298 See MMC1_PINS help text.
299
300config MMC3_PINS
301 string "Pins for mmc3"
302 default ""
303 ---help---
304 See MMC1_PINS help text.
305
Hans de Goedeaf593e42014-10-02 20:43:50 +0200306config MMC_SUNXI_SLOT_EXTRA
307 int "mmc extra slot number"
308 default -1
309 ---help---
310 sunxi builds always enable mmc0, some boards also have a second sdcard
311 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
312 support for this.
313
Hans de Goede99c9fb02016-04-01 22:39:26 +0200314config INITIAL_USB_SCAN_DELAY
315 int "delay initial usb scan by x ms to allow builtin devices to init"
316 default 0
317 ---help---
318 Some boards have on board usb devices which need longer than the
319 USB spec's 1 second to connect from board powerup. Set this config
320 option to a non 0 value to add an extra delay before the first usb
321 bus scan.
322
Hans de Goedee7b852a2015-01-07 15:26:06 +0100323config USB0_VBUS_PIN
324 string "Vbus enable pin for usb0 (otg)"
325 default ""
326 ---help---
327 Set the Vbus enable pin for usb0 (otg). This takes a string in the
328 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
329
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100330config USB0_VBUS_DET
331 string "Vbus detect pin for usb0 (otg)"
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100332 default ""
333 ---help---
334 Set the Vbus detect pin for usb0 (otg). This takes a string in the
335 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
336
Hans de Goedeaadd97f2015-06-14 17:29:53 +0200337config USB0_ID_DET
338 string "ID detect pin for usb0 (otg)"
339 default ""
340 ---help---
341 Set the ID detect pin for usb0 (otg). This takes a string in the
342 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
343
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100344config USB1_VBUS_PIN
345 string "Vbus enable pin for usb1 (ehci0)"
346 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100347 default "PH27" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100348 ---help---
349 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
350 a string in the format understood by sunxi_name_to_gpio, e.g.
351 PH1 for pin 1 of port H.
352
353config USB2_VBUS_PIN
354 string "Vbus enable pin for usb2 (ehci1)"
355 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100356 default "PH24" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100357 ---help---
358 See USB1_VBUS_PIN help text.
359
Hans de Goedea60c3fc2016-03-18 08:42:01 +0100360config USB3_VBUS_PIN
361 string "Vbus enable pin for usb3 (ehci2)"
362 default ""
363 ---help---
364 See USB1_VBUS_PIN help text.
365
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200366config I2C0_ENABLE
367 bool "Enable I2C/TWI controller 0"
368 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
369 default n if MACH_SUN6I || MACH_SUN8I
370 ---help---
371 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
372 its clock and setting up the bus. This is especially useful on devices
373 with slaves connected to the bus or with pins exposed through e.g. an
374 expansion port/header.
375
376config I2C1_ENABLE
377 bool "Enable I2C/TWI controller 1"
378 default n
379 ---help---
380 See I2C0_ENABLE help text.
381
382config I2C2_ENABLE
383 bool "Enable I2C/TWI controller 2"
384 default n
385 ---help---
386 See I2C0_ENABLE help text.
387
388if MACH_SUN6I || MACH_SUN7I
389config I2C3_ENABLE
390 bool "Enable I2C/TWI controller 3"
391 default n
392 ---help---
393 See I2C0_ENABLE help text.
394endif
395
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100396if SUNXI_GEN_SUN6I
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100397config R_I2C_ENABLE
398 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100399 # This is used for the pmic on H3
400 default y if SY8106A_POWER
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100401 ---help---
402 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100403endif
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100404
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200405if MACH_SUN7I
406config I2C4_ENABLE
407 bool "Enable I2C/TWI controller 4"
408 default n
409 ---help---
410 See I2C0_ENABLE help text.
411endif
412
Hans de Goede3ae1d132015-04-25 17:25:14 +0200413config AXP_GPIO
414 boolean "Enable support for gpio-s on axp PMICs"
415 default n
416 ---help---
417 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
418
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200419config VIDEO
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100420 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
vishnupatekarcdf1e482015-11-29 01:07:19 +0800421 depends on !MACH_SUN8I_A83T
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200422 default y
423 ---help---
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100424 Say Y here to add support for using a cfb console on the HDMI, LCD
425 or VGA output found on most sunxi devices. See doc/README.video for
426 info on how to select the video output and mode.
427
Hans de Goedee9544592014-12-23 23:04:35 +0100428config VIDEO_HDMI
429 boolean "HDMI output support"
430 depends on VIDEO && !MACH_SUN8I
431 default y
432 ---help---
433 Say Y here to add support for outputting video over HDMI.
434
Hans de Goede260f5202014-12-25 13:58:06 +0100435config VIDEO_VGA
436 boolean "VGA output support"
437 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
438 default n
439 ---help---
440 Say Y here to add support for outputting video over VGA.
441
Hans de Goedeac1633c2014-12-24 12:17:07 +0100442config VIDEO_VGA_VIA_LCD
443 boolean "VGA via LCD controller support"
Chen-Yu Tsai39ca4c12015-01-12 18:02:10 +0800444 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedeac1633c2014-12-24 12:17:07 +0100445 default n
446 ---help---
447 Say Y here to add support for external DACs connected to the parallel
448 LCD interface driving a VGA connector, such as found on the
449 Olimex A13 boards.
450
Hans de Goede18366f72015-01-25 15:33:07 +0100451config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
452 boolean "Force sync active high for VGA via LCD controller support"
453 depends on VIDEO_VGA_VIA_LCD
454 default n
455 ---help---
456 Say Y here if you've a board which uses opendrain drivers for the vga
457 hsync and vsync signals. Opendrain drivers cannot generate steep enough
458 positive edges for a stable video output, so on boards with opendrain
459 drivers the sync signals must always be active high.
460
Chen-Yu Tsai9ed19522015-01-12 18:02:11 +0800461config VIDEO_VGA_EXTERNAL_DAC_EN
462 string "LCD panel power enable pin"
463 depends on VIDEO_VGA_VIA_LCD
464 default ""
465 ---help---
466 Set the enable pin for the external VGA DAC. This takes a string in the
467 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
468
Hans de Goedec06e00e2015-08-03 19:20:26 +0200469config VIDEO_COMPOSITE
470 boolean "Composite video output support"
471 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
472 default n
473 ---help---
474 Say Y here to add support for outputting composite video.
475
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100476config VIDEO_LCD_MODE
477 string "LCD panel timing details"
478 depends on VIDEO
479 default ""
480 ---help---
481 LCD panel timing details string, leave empty if there is no LCD panel.
482 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
483 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede924c8932015-08-16 11:23:42 +0200484 Also see: http://linux-sunxi.org/LCD
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100485
Hans de Goede481b6642015-01-13 13:21:46 +0100486config VIDEO_LCD_DCLK_PHASE
487 int "LCD panel display clock phase"
488 depends on VIDEO
489 default 1
490 ---help---
491 Select LCD panel display clock phase shift, range 0-3.
492
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100493config VIDEO_LCD_POWER
494 string "LCD panel power enable pin"
495 depends on VIDEO
496 default ""
497 ---help---
498 Set the power enable pin for the LCD panel. This takes a string in the
499 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
500
Hans de Goedece9e3322015-02-16 17:26:41 +0100501config VIDEO_LCD_RESET
502 string "LCD panel reset pin"
503 depends on VIDEO
504 default ""
505 ---help---
506 Set the reset pin for the LCD panel. This takes a string in the format
507 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
508
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100509config VIDEO_LCD_BL_EN
510 string "LCD panel backlight enable pin"
511 depends on VIDEO
512 default ""
513 ---help---
514 Set the backlight enable pin for the LCD panel. This takes a string in the
515 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
516 port H.
517
518config VIDEO_LCD_BL_PWM
519 string "LCD panel backlight pwm pin"
520 depends on VIDEO
521 default ""
522 ---help---
523 Set the backlight pwm pin for the LCD panel. This takes a string in the
524 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200525
Hans de Goede2d5d3022015-01-22 21:02:42 +0100526config VIDEO_LCD_BL_PWM_ACTIVE_LOW
527 bool "LCD panel backlight pwm is inverted"
528 depends on VIDEO
529 default y
530 ---help---
531 Set this if the backlight pwm output is active low.
532
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100533config VIDEO_LCD_PANEL_I2C
534 bool "LCD panel needs to be configured via i2c"
535 depends on VIDEO
Hans de Goede6de9f762015-03-07 12:00:02 +0100536 default n
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100537 ---help---
538 Say y here if the LCD panel needs to be configured via i2c. This
539 will add a bitbang i2c controller using gpios to talk to the LCD.
540
541config VIDEO_LCD_PANEL_I2C_SDA
542 string "LCD panel i2c interface SDA pin"
543 depends on VIDEO_LCD_PANEL_I2C
544 default "PG12"
545 ---help---
546 Set the SDA pin for the LCD i2c interface. This takes a string in the
547 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
548
549config VIDEO_LCD_PANEL_I2C_SCL
550 string "LCD panel i2c interface SCL pin"
551 depends on VIDEO_LCD_PANEL_I2C
552 default "PG10"
553 ---help---
554 Set the SCL pin for the LCD i2c interface. This takes a string in the
555 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
556
Hans de Goede797a0f52015-01-01 22:04:34 +0100557
558# Note only one of these may be selected at a time! But hidden choices are
559# not supported by Kconfig
560config VIDEO_LCD_IF_PARALLEL
561 bool
562
563config VIDEO_LCD_IF_LVDS
564 bool
565
566
567choice
568 prompt "LCD panel support"
569 depends on VIDEO
570 ---help---
571 Select which type of LCD panel to support.
572
573config VIDEO_LCD_PANEL_PARALLEL
574 bool "Generic parallel interface LCD panel"
575 select VIDEO_LCD_IF_PARALLEL
576
577config VIDEO_LCD_PANEL_LVDS
578 bool "Generic lvds interface LCD panel"
579 select VIDEO_LCD_IF_LVDS
580
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200581config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
582 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
583 select VIDEO_LCD_SSD2828
584 select VIDEO_LCD_IF_PARALLEL
585 ---help---
Hans de Goede91f1b822015-08-08 16:13:53 +0200586 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
587
588config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
589 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
590 select VIDEO_LCD_ANX9804
591 select VIDEO_LCD_IF_PARALLEL
592 select VIDEO_LCD_PANEL_I2C
593 ---help---
594 Select this for eDP LCD panels with 4 lanes running at 1.62G,
595 connected via an ANX9804 bridge chip.
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200596
Hans de Goede743fb9552015-01-20 09:23:36 +0100597config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
598 bool "Hitachi tx18d42vm LCD panel"
599 select VIDEO_LCD_HITACHI_TX18D42VM
600 select VIDEO_LCD_IF_LVDS
601 ---help---
602 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
603
Hans de Goede613dade2015-02-16 17:49:47 +0100604config VIDEO_LCD_TL059WV5C0
605 bool "tl059wv5c0 LCD panel"
606 select VIDEO_LCD_PANEL_I2C
607 select VIDEO_LCD_IF_PARALLEL
608 ---help---
609 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
610 Aigo M60/M608/M606 tablets.
611
Hans de Goede797a0f52015-01-01 22:04:34 +0100612endchoice
613
614
Hans de Goedebf880fe2015-01-25 12:10:48 +0100615config GMAC_TX_DELAY
616 int "GMAC Transmit Clock Delay Chain"
617 default 0
618 ---help---
619 Set the GMAC Transmit Clock Delay Chain value.
620
Hans de Goede66ab79d2015-09-13 13:02:48 +0200621config SPL_STACK_R_ADDR
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200622 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
Hans de Goede66ab79d2015-09-13 13:02:48 +0200623 default 0x2fe00000 if MACH_SUN9I
624
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900625endif